Yuri Stepchenkov | Institute of Informatics Problems of the Russian Academy of Sciences (original) (raw)

Papers by Yuri Stepchenkov

Сборник включает в себя научные работы, отражающие современные мировые достижения в области матер... more Сборник включает в себя научные работы, отражающие современные мировые достижения в области материаловедения электронных компонентов и представляет новые методы математического моделирования и программные решения для разработки прикладных программных систем. Для специалистов в области вычислительного материаловедения, прикладной математики, математического моделирования, проектирования и автоматизации изделий наноэлектроники, разработчиков современных прикладных программных систем, аспирантов и студентов старших курсов университетов и технических вузов. Ключевые слова: математическое моделирование, вычислительное материаловедение, прикладная математика, дизайн материалов, электронные компоненты, наноэлектроника, прикладные программные системы, нейроморфные системы.

Mathematical modeling in materials science of electronic component

The paper proposes design and circuitry solutions for the implementation of high-performance next... more The paper proposes design and circuitry solutions for the implementation of high-performance next generation computers. They are based on self-timed circuit design methodology and provide an increase in the tolerance of computing systems to soft errors resulting from induced noises and radiation exposure.

Context. Self-Timed Circuits, proposed by D. Muller on the rise of the digital era, continues to ... more Context. Self-Timed Circuits, proposed by D. Muller on the rise of the digital era, continues to excite researchers’ minds. These circuits started with the task of improving performance by taking into account real delays. Then Self-Timed Circuits have moved into the field of green computing. At last, they are currently positioned mainly in the field of fault tolerance. There is much redundancy in Self-Timed Circuits. It is believed that Self-Timed Circuits approaches will be in demand in the nano-circuitry when a synchronous approach becomes impossible. Strictly Self-Timed Circuits check transition process completion for each gate’s output. For this, they use so-called D. Muller elements (C-elements, hysteresis flip-flops, G-flip-flops). Usually, Self-Timed Circuits are designed on Uncommitted Logic Array. Now an extensive base of Uncommitted Logic Array Self-Timed gates exists. It is believed that SelfTimed Circuits are not compatible with FPGA technology. However, attempts to crea...

В работе предлагаются конструктивные и схемотехнические решения для реализации высокопроизводител... more В работе предлагаются конструктивные и схемотехнические решения для реализации высокопроизводительных компьютеров следующего поколения. Они основаны на методологии проектирования самосинхронных схем и обеспечивают повышение устойчивости вычислительных систем к логическим сбоям, являющимся следствием наведенных помех и радиационного воздействия

2022 International Russian Automation Conference (RusAutoCon)

Advances in Science, Technology and Engineering Systems Journal, 2020

The paper discusses the features of the implementation and functioning of digital self-timed circ... more The paper discusses the features of the implementation and functioning of digital self-timed circuits. They have a naturally high tolerance to short-term single soft errors caused by various factors, such as nuclear particles, radiation, and others. Combinational self-timed circuits using dual-rail coding of signals are naturally immune to 91% of typical soft errors classified in the paper. The remaining critical soft errors are related to the state of the dual-rail signal, opposite to the spacer and forbidden in traditional dual-rail coding of signals. Paper proposes to consider this state as the second spacer and to indicate it as a spacer to increase the self-timed circuit tolerance to soft errors. Together with an improved indication of the self-timed pipeline, this provides masking of 100% of the considered typical soft errors in combinational self-timed circuits. Due to internal feedback, self-timed latches and flip-flops are less protected from soft errors, as are synchronous memory cells. But thanks to their indication and the input and output signals generation discipline, they are also immune to 89% of typical soft errors. Usage of the self-timed latches and flip-flops with dual-rail coding of information outputs increases the tolerance of self-timed latches and flip-flops to soft errors by 2%. Application of the DICE-like approach to circuitry and layout design of sequential self-timed circuits provide an increase in their tolerance to the single soft errors up to the level of 100%.

2019 IEEE East-West Design & Test Symposium (EWDTS), 2019

Paper discusses a problem of the CMOS self-timed circuits' indication. Large number of indica... more Paper discusses a problem of the CMOS self-timed circuits' indication. Large number of indicating signals in the multi-bit computational devices and registers requires an additional hardware and time for their combining and forming a single control signal that provides a request-acknowledge interaction between interconnected self-timed functional blocks. Indication subcircuit performs this. Multi-input hysteretic triggers allows for accelerating indication subcircuit by factor of 1.1 − 1.6 and reducing its complexity in several times in comparison to standard implementation basis on static and semi-static Muller's elements. A penalty for this is some short-circuit current in the worst case.

2016 IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW), 2016

This paper covers new recurrent data-flow computational model, as well as architecture that imple... more This paper covers new recurrent data-flow computational model, as well as architecture that implements principles and ideas of this model. Basic differences of this model from the existing ones and examine key aspects of this new computational model including its implementation in the form of Hybrid Recurrent Architecture of Digital Signal Processor are described. The approach and methodology of hardware and software modelling and testing based on new architecture are being proposed. We introduce the model of implementation of the proposed architecture as well as imitation modelling tools of recurrent data-flow architecture, implementing said model. Functionality of imitation model and its role in software development suite for new architecture software development is being described. We introduce the notion of the target modelling platform called GAROS IDE. The results of platform testing on several subtasks of isolated words recognition problem are presented.

2020 IEEE 11th International Conference on Dependable Systems, Services and Technologies (DESSERT), 2020

the paper examines the immunity of Quasi Delay-Insensitive (QDI) circuits to soft errors caused b... more the paper examines the immunity of Quasi Delay-Insensitive (QDI) circuits to soft errors caused by noises. The considered noise sources are internal and external events: layout wires crosstalk, interference on the power and ground buses, electromagnetic pulse. The paper suggests using the failsafe QDI circuits discipline and layout methods that reduce dual-rail signal sensitivity to noises. Indication of dual-rail signal forbidden state as a spacer increases QDI circuits immunity to soft errors. Using a modified C-element to implement a pipeline stage register bit reduces the danger of the pipeline deadlock. It improves the immunity of the QDI pipeline to the noise soft errors by 11% (up to 97.8%).

2020 IEEE East-West Design & Test Symposium (EWDTS), 2020

Indication subcircuit is an essential part of the self-timed circuits. It provides acknowledgment... more Indication subcircuit is an essential part of the self-timed circuits. It provides acknowledgment of the self-timed circuit switching completion and ensures correct handshake interaction between functional blocks. Besides, indication subcircuit complexity is comparable with the indicated self-timed circuit's complexity. So short-term soft errors, induced by the external and internal causes in both the indication subcircuit and the indicated self-timed circuit, are equally dangerous. Indication subcircuit soft error tolerance depends, the first, on its immunity to soft errors in the indicated self-timed circuit and, the second, on its failure protection. The first aspect becomes lower critical due to the XOR cell on the first stage of the indication subcircuit. An appropriate circuitry basis decreases indication subcircuit sensitivity to the possible soft errors induced in it. Static and semi-static Muller's C-element is a traditional base component used for indication purpos...

The results of development of multi-core recurrent dataflow architecture (MRDA) focused on effect... more The results of development of multi-core recurrent dataflow architecture (MRDA) focused on effective implementation of parallel digital signal processing (DSP) algorithms are being presented. All stages of MRDA development are integrated into a single iterative design cycle including mathematical modeling tools (imitational model); hardware modeling tools (VHDL-model); FPGA prototype and tools for developing the software meant to run on MRDA. Comparative assessments of effectiveness of DSP algorithms implemented on MRDA in relation to tradition DSP-processor are being presented.

2019 10th International Conference on Dependable Systems, Services and Technologies (DESSERT), 2019

the paper discusses a fault-tolerance problem for digital integrated circuits. Due to their prope... more the paper discusses a fault-tolerance problem for digital integrated circuits. Due to their properties, self-timed circuits, unlike synchronous counterparts, are immune towards the greater part of the short-term logical faults. Indication of an illegal state of the dual-rail signal as second spacer increases fault-tolerance of the combinational self-timed circuits up to 82%. Self-timed triggers, due to their indication features, are immune to 44% logical faults. The use of special methods of doubling transistors and bistable cells, which are the basis of the self-timed triggers, enhances their fault-tolerance up to 80%.

Mathematical modeling in materials science of electronic component

The article considers the problem of developing synchronous and self-timed (ST) digital circuits ... more The article considers the problem of developing synchronous and self-timed (ST) digital circuits that are tolerant to soft errors. Synchronous circuits traditionally use the 2-of-3 voting principle to ensure single failure, resulting in three times the hardware costs. In ST circuits, due to dual-rail signal coding and two-phase control, even duplication provides a soft error tolerance level 2.1 to 3.5 times higher than the triple modular redundant synchronous counterpart. The development of new high-precision software simulating microelectronic failure mechanisms will provide more accurate estimates for the electronic circuits' failure tolerance

2016 IEEE East-West Design & Test Symposium (EWDTS), 2016

The approaches to self-timed hardware design are presented. The conditions of intersystem integra... more The approaches to self-timed hardware design are presented. The conditions of intersystem integration of synchronous and self-timed devices are considered through the example of the quasi-delay-insensitive computing device development. This device performs functions of division and square root extraction. It operates with numbers of single and double precisions corresponding to the IEEE 754 standard.

Сборник включает в себя научные работы, отражающие современные мировые достижения в области матер... more Сборник включает в себя научные работы, отражающие современные мировые достижения в области материаловедения электронных компонентов и представляет новые методы математического моделирования и программные решения для разработки прикладных программных систем. Для специалистов в области вычислительного материаловедения, прикладной математики, математического моделирования, проектирования и автоматизации изделий наноэлектроники, разработчиков современных прикладных программных систем, аспирантов и студентов старших курсов университетов и технических вузов. Ключевые слова: математическое моделирование, вычислительное материаловедение, прикладная математика, дизайн материалов, электронные компоненты, наноэлектроника, прикладные программные системы, нейроморфные системы.

Mathematical modeling in materials science of electronic component

The paper proposes design and circuitry solutions for the implementation of high-performance next... more The paper proposes design and circuitry solutions for the implementation of high-performance next generation computers. They are based on self-timed circuit design methodology and provide an increase in the tolerance of computing systems to soft errors resulting from induced noises and radiation exposure.

Context. Self-Timed Circuits, proposed by D. Muller on the rise of the digital era, continues to ... more Context. Self-Timed Circuits, proposed by D. Muller on the rise of the digital era, continues to excite researchers’ minds. These circuits started with the task of improving performance by taking into account real delays. Then Self-Timed Circuits have moved into the field of green computing. At last, they are currently positioned mainly in the field of fault tolerance. There is much redundancy in Self-Timed Circuits. It is believed that Self-Timed Circuits approaches will be in demand in the nano-circuitry when a synchronous approach becomes impossible. Strictly Self-Timed Circuits check transition process completion for each gate’s output. For this, they use so-called D. Muller elements (C-elements, hysteresis flip-flops, G-flip-flops). Usually, Self-Timed Circuits are designed on Uncommitted Logic Array. Now an extensive base of Uncommitted Logic Array Self-Timed gates exists. It is believed that SelfTimed Circuits are not compatible with FPGA technology. However, attempts to crea...

В работе предлагаются конструктивные и схемотехнические решения для реализации высокопроизводител... more В работе предлагаются конструктивные и схемотехнические решения для реализации высокопроизводительных компьютеров следующего поколения. Они основаны на методологии проектирования самосинхронных схем и обеспечивают повышение устойчивости вычислительных систем к логическим сбоям, являющимся следствием наведенных помех и радиационного воздействия

2022 International Russian Automation Conference (RusAutoCon)

Advances in Science, Technology and Engineering Systems Journal, 2020

The paper discusses the features of the implementation and functioning of digital self-timed circ... more The paper discusses the features of the implementation and functioning of digital self-timed circuits. They have a naturally high tolerance to short-term single soft errors caused by various factors, such as nuclear particles, radiation, and others. Combinational self-timed circuits using dual-rail coding of signals are naturally immune to 91% of typical soft errors classified in the paper. The remaining critical soft errors are related to the state of the dual-rail signal, opposite to the spacer and forbidden in traditional dual-rail coding of signals. Paper proposes to consider this state as the second spacer and to indicate it as a spacer to increase the self-timed circuit tolerance to soft errors. Together with an improved indication of the self-timed pipeline, this provides masking of 100% of the considered typical soft errors in combinational self-timed circuits. Due to internal feedback, self-timed latches and flip-flops are less protected from soft errors, as are synchronous memory cells. But thanks to their indication and the input and output signals generation discipline, they are also immune to 89% of typical soft errors. Usage of the self-timed latches and flip-flops with dual-rail coding of information outputs increases the tolerance of self-timed latches and flip-flops to soft errors by 2%. Application of the DICE-like approach to circuitry and layout design of sequential self-timed circuits provide an increase in their tolerance to the single soft errors up to the level of 100%.

2019 IEEE East-West Design & Test Symposium (EWDTS), 2019

Paper discusses a problem of the CMOS self-timed circuits' indication. Large number of indica... more Paper discusses a problem of the CMOS self-timed circuits' indication. Large number of indicating signals in the multi-bit computational devices and registers requires an additional hardware and time for their combining and forming a single control signal that provides a request-acknowledge interaction between interconnected self-timed functional blocks. Indication subcircuit performs this. Multi-input hysteretic triggers allows for accelerating indication subcircuit by factor of 1.1 − 1.6 and reducing its complexity in several times in comparison to standard implementation basis on static and semi-static Muller's elements. A penalty for this is some short-circuit current in the worst case.

2016 IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW), 2016

This paper covers new recurrent data-flow computational model, as well as architecture that imple... more This paper covers new recurrent data-flow computational model, as well as architecture that implements principles and ideas of this model. Basic differences of this model from the existing ones and examine key aspects of this new computational model including its implementation in the form of Hybrid Recurrent Architecture of Digital Signal Processor are described. The approach and methodology of hardware and software modelling and testing based on new architecture are being proposed. We introduce the model of implementation of the proposed architecture as well as imitation modelling tools of recurrent data-flow architecture, implementing said model. Functionality of imitation model and its role in software development suite for new architecture software development is being described. We introduce the notion of the target modelling platform called GAROS IDE. The results of platform testing on several subtasks of isolated words recognition problem are presented.

2020 IEEE 11th International Conference on Dependable Systems, Services and Technologies (DESSERT), 2020

the paper examines the immunity of Quasi Delay-Insensitive (QDI) circuits to soft errors caused b... more the paper examines the immunity of Quasi Delay-Insensitive (QDI) circuits to soft errors caused by noises. The considered noise sources are internal and external events: layout wires crosstalk, interference on the power and ground buses, electromagnetic pulse. The paper suggests using the failsafe QDI circuits discipline and layout methods that reduce dual-rail signal sensitivity to noises. Indication of dual-rail signal forbidden state as a spacer increases QDI circuits immunity to soft errors. Using a modified C-element to implement a pipeline stage register bit reduces the danger of the pipeline deadlock. It improves the immunity of the QDI pipeline to the noise soft errors by 11% (up to 97.8%).

2020 IEEE East-West Design & Test Symposium (EWDTS), 2020

Indication subcircuit is an essential part of the self-timed circuits. It provides acknowledgment... more Indication subcircuit is an essential part of the self-timed circuits. It provides acknowledgment of the self-timed circuit switching completion and ensures correct handshake interaction between functional blocks. Besides, indication subcircuit complexity is comparable with the indicated self-timed circuit's complexity. So short-term soft errors, induced by the external and internal causes in both the indication subcircuit and the indicated self-timed circuit, are equally dangerous. Indication subcircuit soft error tolerance depends, the first, on its immunity to soft errors in the indicated self-timed circuit and, the second, on its failure protection. The first aspect becomes lower critical due to the XOR cell on the first stage of the indication subcircuit. An appropriate circuitry basis decreases indication subcircuit sensitivity to the possible soft errors induced in it. Static and semi-static Muller's C-element is a traditional base component used for indication purpos...

The results of development of multi-core recurrent dataflow architecture (MRDA) focused on effect... more The results of development of multi-core recurrent dataflow architecture (MRDA) focused on effective implementation of parallel digital signal processing (DSP) algorithms are being presented. All stages of MRDA development are integrated into a single iterative design cycle including mathematical modeling tools (imitational model); hardware modeling tools (VHDL-model); FPGA prototype and tools for developing the software meant to run on MRDA. Comparative assessments of effectiveness of DSP algorithms implemented on MRDA in relation to tradition DSP-processor are being presented.

2019 10th International Conference on Dependable Systems, Services and Technologies (DESSERT), 2019

the paper discusses a fault-tolerance problem for digital integrated circuits. Due to their prope... more the paper discusses a fault-tolerance problem for digital integrated circuits. Due to their properties, self-timed circuits, unlike synchronous counterparts, are immune towards the greater part of the short-term logical faults. Indication of an illegal state of the dual-rail signal as second spacer increases fault-tolerance of the combinational self-timed circuits up to 82%. Self-timed triggers, due to their indication features, are immune to 44% logical faults. The use of special methods of doubling transistors and bistable cells, which are the basis of the self-timed triggers, enhances their fault-tolerance up to 80%.

Mathematical modeling in materials science of electronic component

The article considers the problem of developing synchronous and self-timed (ST) digital circuits ... more The article considers the problem of developing synchronous and self-timed (ST) digital circuits that are tolerant to soft errors. Synchronous circuits traditionally use the 2-of-3 voting principle to ensure single failure, resulting in three times the hardware costs. In ST circuits, due to dual-rail signal coding and two-phase control, even duplication provides a soft error tolerance level 2.1 to 3.5 times higher than the triple modular redundant synchronous counterpart. The development of new high-precision software simulating microelectronic failure mechanisms will provide more accurate estimates for the electronic circuits' failure tolerance

2016 IEEE East-West Design & Test Symposium (EWDTS), 2016

The approaches to self-timed hardware design are presented. The conditions of intersystem integra... more The approaches to self-timed hardware design are presented. The conditions of intersystem integration of synchronous and self-timed devices are considered through the example of the quasi-delay-insensitive computing device development. This device performs functions of division and square root extraction. It operates with numbers of single and double precisions corresponding to the IEEE 754 standard.