Susmita Sur-kolay | Indian Statistical Institute, Calcutta (original) (raw)

Papers by Susmita Sur-kolay

ArXiv, 2018

With aggressively shrinking process technologies, physical design faces severe challenges and ear... more With aggressively shrinking process technologies, physical design faces severe challenges and early detection of failures is mandated. It may otherwise lead to many iterations and thus impact time-to-market. This has encouraged to devise a feedback mechanism from a lower abstraction level of the design flow towards the higher levels. Some of these efforts include placement driven synthesis, routability (timing) driven placement etc. Motivated by this philosophy, we propose a novel global routing method using monotone staircase routing regions (channels), defined at the floorplanning stage. The intent is to identify the feasibility of a floorplan topology of the given design netlist by estimating routability, routed net length and the number of vias while taking into account global congestion scenario across the layout. This framework works on both unreserved as well as HV reserved layer model for M(geq2)M(\geq 2)M(geq2) metal layers and accommodates different capacity profiles of the routing re...

2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016

IC fabrication in nanometer technology nodes faces severe challenges in handling lithography hots... more IC fabrication in nanometer technology nodes faces severe challenges in handling lithography hotspots due to edge placement error (EPE). These hotspots are particularly tackled by wire-spreading or rip-up and reroute during detailed routing, at the cost of more design iterations. They cannot be minimized unless a suitable routing penalty is imposed during global routing. In this paper, we present a new hybrid global route planning framework that follows floor planning. Since an accurate estimation of EPE on a net segment cannot be attained, we employ a routing penalty based on known simulation results, in order to identify a least cost routing path of a net across multiple metal layers. The results of our experiments on IBM HB floor planning benchmarks show an 4%, 53% and 74% improvement in net length, via count and worst case congestion respectively on an average.

2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Physical design of a chip typically entails the global routing (GR) step after detailed placement... more Physical design of a chip typically entails the global routing (GR) step after detailed placement. In this step, the grid graph (GG) model is used widely for the one or two-bend pattern routing stage. While several iterations may be required for GR, these may be reduced with appropriate route planning at the floor planning stage. In this case, the routing regions can be identified as recursive top-down bipartitioning by either straight cut lines or monotone staircases. The capacity of each region is estimated as the number nets that can fit in it without design rule violation. Given a floor plan, identifying a set of monotone staircases such that (a) the balance in area of each bipartition is maximized, (b) the number of nets cut, and (c) the number of bends in a monotone staircase are minimized, is a multi-objective optimization problem and is NP-hard. The existing heuristic methods are based on either max flow or directed search on floor plan adjacency graph. In this paper, we propose a new monotone staircase bipartitioning method using a randomized neighbor search technique. Compared to the earlier methods, our experimental results on a set of floor planning benchmark circuits demonstrate on an average 3% improvement in the cost function, as well as 9% and 7% in the number of vias and congestion after global routing.

The use of general descriptive names, registered names, trademarks, service marks, etc. in this p... more The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use.

Abstract—With more integration in VLSI technology, Intellectual Property (IP) cores are reused to... more Abstract—With more integration in VLSI technology, Intellectual Property (IP) cores are reused to meet the customer’s specifications in time. For intellectual property protection (IPP), various kinds of IP marks, such as watermarks, fingerprints, are embedded into the design for establishing the veracity of a legal IP owner. However, convincing public verification of such marks is not leakageproof. Attackers not only manage to obtain potential clues to tamper public marks rendering public verification invalid, but can also suitably override the marks to include own signature, resulting in wrong public identification of IP vendor and IP buyer. Furthermore, current technique includes a sufficiently large set of public marks containing a header and a message body in addition to private ones to facilitate only public verification at the cost of significant increase in design overhead. We propose a zero-knowledge protocol to ensure robust and leakage proof convincing public verification ...

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2013

This work proposes a new algorithm for global routing using monotone staircase channels obtained ... more This work proposes a new algorithm for global routing using monotone staircase channels obtained from VLSI floorplan topology. Unlike the existing global routers that follow block placement stage, it immediately follows the floorplanning stage of VLSI design. The monotone staircase channels are identified using the results of recent O(nk log n) top-down hierarchical monotone staircase bipartition. The worst case time complexity of the proposed global routing algorithm is O(n2kt), where n, k and t denote the number of blocks, nets and the number of terminals in a given net respectively for a given floorplan. Experimental results on the MCNC/GSRC floorplanning benchmark circuits show that our method obtained 100% routability for each of the nets, without any over-congestion through the monotone staircase channels. The wire length for each of the t-terminal (t ≥ 2) nets is comparable to the steiner length of that net in almost all cases.

Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004

Abstract Power density of high-end microprocessors has been increasing by approximately 80% per t... more Abstract Power density of high-end microprocessors has been increasing by approximately 80% per technology generation, while the voltage is scaling by a factor of 0.8. This leads to 225% increase in current per unit area in successive generation of technologies. The cost ...

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1991

Channel graphs for nonsliceable floorplans are studied for determination of feasible channel rout... more Channel graphs for nonsliceable floorplans are studied for determination of feasible channel routing order. The minimum feedback vertex set (MFVS) formulation is revisited and a polynomial time heuristic is presented. It is shown that feasible routing orders with reserved channels, L-channels, and monotone channels can be obtained from a given MFVS for any floorplan. This approach provides a powerful tool

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001

We address the problem of hierarchically partitioning a VLSI floorplan F using monotone staircase... more We address the problem of hierarchically partitioning a VLSI floorplan F using monotone staircase channels to aid global routing. Our problem is to identify a monotone staircase channel (ms-cut) from one corner of F to its opposite corner, such that (i) the number of nets crossing the ms-cut is minimized, and (ii) the area (or the number of the blocks)

VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design, 2000

This paper presents a fast graph-traversal based greedy approach for solving the problem of topol... more This paper presents a fast graph-traversal based greedy approach for solving the problem of topological routing in the presence o f p olygonal obstacles. The polygonal obstacles represent pre-routed nets or groups of circuit blocks. Routing paths for all the nets are c onstructed incrementally and concurrently. Design rules for separation are m o deled a s c onstraints on edges and vertices. The experimental results obtained are very encouraging.

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, 2005

In this paper we have proposed geometric models that are employed to devise a scheme for identify... more In this paper we have proposed geometric models that are employed to devise a scheme for identifying the hot spots and zones in a chip. These spots or zones need to be guarded thermally to ensure performance and reliability of the chip. Two different models, namely continuous and discrete, are presented to take into account whether the 2D plane of

Lecture Notes in Computer Science, 2005

The strongly NP-complete Double Digest Problem (DDP) for physical mapping of DNA, is now used for... more The strongly NP-complete Double Digest Problem (DDP) for physical mapping of DNA, is now used for efficient genotyping. An instance of DDP has multiple distinct solutions. Existing methods produce a single solution, and are slow for large instances. We employ a type of equivalence among the distinct solutions to obtain almost all of them. Our method comprises of first finding

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014

ABSTRACT Quantum circuits consist of a cascade of quantum gates. In a physical design-unaware qua... more ABSTRACT Quantum circuits consist of a cascade of quantum gates. In a physical design-unaware quantum logic circuit, a gate is assumed to operate on an arbitrary set of quantum bits (qubits), without considering the physical location of the qubits. However, in reality, physical qubits have to be placed on a grid. Each node of the grid represents a qubit. The grid implements the architecture of the quantum computer. A physical constraint often imposed is that quantum gates can only operate on adjacent qubits on the grid. Hence, a communication channel needs to be built if the qubits in the logical circuit are not adjacent. In this paper, we introduce a tool called the physical design-aware fault-tolerant quantum circuit synthesis (PAQCS). It contains two algorithms: one for physical qubit placement and another for routing of communications. With the help of these two algorithms, the overhead of converting a logical to a physical circuit is reduced by 30.1%, on an average, relative to previous work. The optimization algorithms in PAQCS are evaluated on circuits implemented using quantum operations supported by two different quantum physical machine descriptions and three quantum error-correcting codes. They reduce the number of primitive operations by 11.5%–68.6%, and the number of execution cycles by 16.9%–59.4%.

Lecture Notes in Computer Science, 1988

This paper addresses a crucial question in VLSI floorplanning by rectangular dualization method: ... more This paper addresses a crucial question in VLSI floorplanning by rectangular dualization method: for any planar graph having a rectangular dual, does there exist a slicible dual? A minimum counterexample is presented and the concept of inherent nonslicibility is introduced. The problem of transforming a given nonslicible floorplan to a slicible one with change in shapes of a minimal subset

2008 IEEE Region 10 and the Third international Conference on Industrial and Information Systems, 2008

In the DSM VLSI technology, wide-spread design reuse to meet customer&amp;#39;s requireme... more In the DSM VLSI technology, wide-spread design reuse to meet customer&amp;#39;s requirements in time enhances the probability of infringement of intellectual property (IP) of VLSI physical design. In design storage or during design transmission between two parties, encryption of a design file is a well-known technique to protect a design against hacking, although it takes significantly long time to encrypt

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD), 1995

In this paper, it is shown that for any rectangularly dualizable graph, a feasible topology can b... more In this paper, it is shown that for any rectangularly dualizable graph, a feasible topology can be obtained by using only either straight or Z-cutlines recursively within a bounding rectangle. Given an adjacency graph, a potential topology, which may be nonslicible and is likely to yield an optimally sized oorplan, is produced rst in a top-down fashion using heuristic search in AND-OR graphs. The advantage of this technique is four-fold: (i) accelerates topdown search phase, (ii) generates a oorplan with minimal number of nonslice c ores, (iii) ensures safe routing order without addition of pseudo-modules, and (iv) solves the bottom-up algorithm eciently for optimal sizing of general oorplans in the second phase.

Abstract—Traditional power grid analysis is often focused on resistive, i.e. IR-drop only. Recent... more Abstract—Traditional power grid analysis is often focused on resistive, i.e. IR-drop only. Recently, due to the rapidly increasing operating frequency, the transient power fluctuation caused by Ldi/dt has also become significant. Such resistive and inductive drops can cause transient timing failures in the chip. The power grid can be modeled as a distributed RLC circuit. The electrical model that represents the grid can be very large (millions of components and nodes), thus making on-chip power grid analysis a difficult task. Hence, efficient tools for power grid analysis are required for the designers in order to analyze this problem. Further, in deep sub-micron VLSI chips, when several transistors in physical proximity switch simultaneously, a substantial power supply drop, known as droop, may occur because of concurrent load on a via of the power grid. As a result of lower supply voltage, transistors may slow down. Such timing faults are termed as droop faults. Modeling of droop ...

Lecture Notes in Computer Science, 1995

Acyclic-coloring of a graph G = (V,E) is a partitioning of V, such that the induced subgraph of e... more Acyclic-coloring of a graph G = (V,E) is a partitioning of V, such that the induced subgraph of each partition is acyclic. The minimum number of such partitions of V is defined as the vertex arboricity of G. A linear time algorithm for acyclic-coloring of planar graphs with 3 colors is presented. Next, an O(n2) algorithm is proposed which produces

9th International Conference on Information Technology (ICIT'06), 2006

Buffered clock-tree design, with cells at its leaves, are known to meet timing and skew requireme... more Buffered clock-tree design, with cells at its leaves, are known to meet timing and skew requirements better. Clustering of flip-flops leads to reduced clock-tree wirelengths and power-efficient layouts. In this paper, the problem of clustering flip-flops in a given placement is formulated as Multi-way Equi-Partitioning of a given point set, such that (i) total area of the partition (ii) area of the largest partition and (iii) total deviation of the partitions, are minimal. For this computationally expensive multiobjective optimization problem, also relevant to design of semi-synchronous systems, a technique based on genetic algorithm, is proposed. Crossover and mutation operators specific to the k-way equipartitioning problem, have been designed and a new greedy heuristic operator is employed to accelerate the convergence. Results on data sets obtained from layouts of ISCAS89 benchmark circuit demonstrate the effectiveness of the proposed method.

Proceedings of the 1997 international symposium on Physical design - ISPD '97, 1997

... Area-optimal floorplan generation based on graph dualization, appear in [l, 3, 4, lo]. It was... more ... Area-optimal floorplan generation based on graph dualization, appear in [l, 3, 4, lo]. It was established in [G] that there is a &amp;WI of rectangular graphs, called Inherently Nonslicible (INS) (Fig. l), which do not have any slicible floorplan realiza-tion. ...