Piyas Samanta | Jadavpur University, Kolkata, India (original) (raw)

Papers by Piyas Samanta

Research paper thumbnail of Influence of neutral hole traps in thin gate oxides on MOS device degradation during Fowler-Nordheim stress

1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings

oxide-silicon (MOS) device degradation due to trapping of positive charges in thin (27, 33 nm) Si... more oxide-silicon (MOS) device degradation due to trapping of positive charges in thin (27, 33 nm) Si02 gate oxides is presented. n+-polySi-gate (MOS) capacitors are stressed at a low electron injection fluence (<O.OI C/cm2) by Fowler-Nordheim (FN) electron tunneling &om the quantized accumulation layer of (100) n-Si substrate, at constant current and constant applied gate voltage. The present analysis assumes tunneling electron initiated band-lo-band impact ionization (BTBII) in SiO2, as the possible source of trapped holes during stress. The validity of the present analysis has been examined by comparing the theoretical values with the experhental data of FN threshold voltage shift AVFN of Fazan et al.

Research paper thumbnail of Effect of Silicon Wafer Surface Orientation on Gate Oxide Degradation during Constant Current Fowler-Nordheim Stress at Low Electron Fluence

Research paper thumbnail of On the electrical stress-induced degradation of ultrathin SiO2 in direct tunneling regime

Research paper thumbnail of Mechanism of oxide thickness and temperature dependent current conduction in n+-polySi/SiO2/p-Si structures — a new analysis

Journal of Semiconductors

The conduction mechanism of gate leakage current through thermally grown silicon dioxide (SiO 2 )... more The conduction mechanism of gate leakage current through thermally grown silicon dioxide (SiO 2 ) films on (100) p-type silicon has been investigated in detail under negative bias on the degenerately doped n-type polysilicon (n + -polySi) gate. The analysis utilizes the measured gate current density J G at high oxide fields E ox in 5.4 to 12 nm thick SiO 2 films between 25 and 300 °C. The leakage current measured up to 300 °C was due to Fowler–Nordheim (FN) tunneling of electrons from the accumulated n + -polySi gate in conjunction with Poole Frenkel (PF) emission of trapped-electrons from the electron traps located at energy levels ranging from 0.6 to 1.12 eV (depending on the oxide thickness) below the SiO 2 conduction band (CB). It was observed that PF emission current I PF dominates FN electron tunneling current I FN at oxide electric fields E ox between 6 and 10 MV/cm and throughout the temperature range studied here. Understanding of the mechanism of leakage current conduction through SiO 2 films plays a crucial role in simulation of time-dependent dielectric breakdown (TDDB) of metaloxide–semiconductor (MOS) devices and to precisely predict the normal operating field or applied gate voltage for lifetime projection of the MOS integrated circuits.

Research paper thumbnail of Efficient methodology for estimation of metal effective work function, interface trap, and fixed oxide charges in metal-oxide-semiconductor capacitors with dual layer high - κ/SiO2 dielectric

Journal of Vacuum Science & Technology B

A capacitance-voltage (C-V) based efficient methodology is demonstrated for precise estimation of... more A capacitance-voltage (C-V) based efficient methodology is demonstrated for precise estimation of process-induced various fixed charge distributions in the dielectric layer, interface trapped charges at the silicon/oxide interface, and the effective work function (EWF) of the metal gate on double layer high-κ/silicon dioxide (SiO 2) stack in metal-oxide-semiconductor (MOS) capacitors. The present technique takes care of the variation of the work function of the silicon substrate either due to waferto-wafer variation or nonuniformity of the doping level throughout the entire wafer. The analysis is verified with experimentally obtained high-frequency C-V results by varying only the physical thickness t HfO 2 of the hafnium oxide (HfO 2) dielectric layer on an interfacial SiO 2 film of a fixed thickness t ox in tantalum nitride (TaN)/HfO 2 /SiO 2 /p-Si MOS diodes. A value of 4.5 eV was obtained for EWF of physical vapor deposited TaN on HfO 2. Furthermore, the calculations indicate the presence of a significant amount of positive bulk charges in the high-κ layer, in addition to interface trapped positive charges Q it at the Si/SiO 2 interface and negative effective charges at both the high-κ/SiO 2 and Si/SiO 2 interfaces.

Research paper thumbnail of A comprehensive technique for estimation of process-induced fixed charges and effective work function of the metal gate on high-κ/SiO2 stack

Semiconductor Science and Technology

Research paper thumbnail of Mechanistic analysis of temperature-dependent current conduction through thin tunnel oxide in n+-polySi/SiO2/n+-Si structures

Journal of Applied Physics

We present a detailed investigation on temperature-dependent current conduction through thin tunn... more We present a detailed investigation on temperature-dependent current conduction through thin tunnel oxides grown on degenerately doped n-type silicon (n þ-Si) under positive bias (V G) on heavily doped n-type polycrystalline silicon (n þ-polySi) gate in metal-oxide-semiconductor devices. The leakage current measured between 298 and 573 K and at oxide fields ranging from 6 to 10 MV/cm is primarily attributed to Poole-Frenkel (PF) emission of trapped electrons from the neutral electron traps located in the silicon dioxide (SiO 2) band gap in addition to Fowler-Nordheim (FN) tunneling of electrons from n þ-Si acting as the drain node in FLOating gate Tunnel OXide Electrically Erasable Programmable Read-Only Memory devices. Process-induced neutral electron traps are located at 0.18 eV and 0.9 eV below the SiO 2 conduction band. Throughout the temperature range studied here, PF emission current I PF dominates FN electron tunneling current I FN at oxide electric fields E ox between 6 and 10 MV/cm. A physics based new analytical formula has been developed for FN tunneling of electrons from the accumulation layer of degenerate semiconductors at a wide range of temperatures incorporating the image force barrier rounding effect. FN tunneling has been formulated in the framework of Wentzel-Kramers-Brilloiun taking into account the correction factor due to abrupt variation of the energy barrier at the cathode/oxide interface. The effect of interfacial and near-interfacial trapped-oxide charges on FN tunneling has also been investigated in detail at positive V G. The mechanism of leakage current conduction through SiO 2 films plays a crucial role in simulation of time-dependent dielectric breakdown of the memory devices and to precisely predict the normal operating field or applied floating gate (FG) voltage for lifetime projection of the devices. In addition, we present theoretical results showing the effect of drain doping concentration on the FG leakage current.

Research paper thumbnail of Current conduction mechanisms through thin tunnel oxide during erase operation of flash electrically erasable programmable read-only memory devices

Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena

The mechanism of current conduction through thin tunnel oxide during erase operation of flash ele... more The mechanism of current conduction through thin tunnel oxide during erase operation of flash electrically erasable programmable read-only memory devices has been studied both theoretically and experimentally. The floating gate (FG) leakage current measured between 25 and 300 °C and at oxide fields ranging from 6 to 10 MV/cm is primarily attributed to Poole–Frenkel (PF) emission of trapped electrons from the electron traps located at about 1.0 eV below the silicon dioxide conduction band in addition to Fowler–Nordheim (FN) tunneling of electrons from the degenerately doped n-type polycrystalline silicon (n+-polySi) FG. It is observed that PF emission current IPF dominates FN electron tunneling current IFN at oxide electric fields Eox between 6 and 10 MV/cm and throughout the temperature range studied here. The observed thickness dependence of FG leakage current at a given applied oxide field arises due to different electron trap concentrations in the oxide. A physics based new temperature dependent analytical formula has also been developed for FN tunneling of electrons from the accumulation layer of semiconductors. In addition, the authors present theoretical results showing the effect of the FG doping concentration on the leakage current.The mechanism of current conduction through thin tunnel oxide during erase operation of flash electrically erasable programmable read-only memory devices has been studied both theoretically and experimentally. The floating gate (FG) leakage current measured between 25 and 300 °C and at oxide fields ranging from 6 to 10 MV/cm is primarily attributed to Poole–Frenkel (PF) emission of trapped electrons from the electron traps located at about 1.0 eV below the silicon dioxide conduction band in addition to Fowler–Nordheim (FN) tunneling of electrons from the degenerately doped n-type polycrystalline silicon (n+-polySi) FG. It is observed that PF emission current IPF dominates FN electron tunneling current IFN at oxide electric fields Eox between 6 and 10 MV/cm and throughout the temperature range studied here. The observed thickness dependence of FG leakage current at a given applied oxide field arises due to different electron trap concentrations in the oxide. A physics based new temperature dependent analyt...

Research paper thumbnail of Leakage current conduction, hole injection, and time-dependent dielectric breakdown ofn-4H-SiC MOS capacitors during positive bias temperature stress

Journal of Applied Physics

The conduction mechanism(s) of gate leakage current JG through thermally grown silicon dioxide (S... more The conduction mechanism(s) of gate leakage current JG through thermally grown silicon dioxide (SiO2) films on the silicon (Si) face of n-type 4H-silicon carbide (4H-SiC) has been studied in detail under positive gate bias. It was observed that at an oxide field above 5 MV/cm, the leakage current measured up to 303 °C can be explained by Fowler-Nordheim (FN) tunneling of electrons from the accumulated n-4H-SiC and Poole-Frenkel (PF) emission of trapped electrons from the localized neutral traps located at ≈2.5 eV below the SiO2 conduction band. However, the PF emission current IPF dominates the FN electron tunneling current IFN at oxide electric fields Eox between 5 and 10 MV/cm and in the temperature ranging from 31 to 303 °C. In addition, we have presented a comprehensive analysis of injection of holes and their subsequent trapping into as-grown oxide traps eventually leading to time-dependent dielectric breakdown during electron injection under positive bias temperature stress (PBTS) in n-4H-SiC metal-...

Research paper thumbnail of Leakage current conduction and reliability assessment of passivating thin silicon dioxide films on n -4H-SiC

Hard X-Ray, Gamma-Ray, and Neutron Detector Physics XVIII, 2016

We have analyzed the mechanisms of leakage current conduction in passivating silicon dioxide (SiO... more We have analyzed the mechanisms of leakage current conduction in passivating silicon dioxide (SiO2) films grown on (0 0 0 1) silicon (Si) face of n-type 4H-SiC (silicon carbide). It was observed that the experimentally measured gate current density in metal-oxide-silicon carbide (MOSiC) structures under positive gate bias at an oxide field Eox above 5 MV/cm is comprised of Fowler-Nordheim (FN) tunneling of electrons from the accumulated n-4H-SiC and Poole-Frenkel (PF) emission of trapped electrons from the localized neutral traps in the SiO2 gap, IFN and IPF, respectively at temperatures between 27 and 200 °C. In MOSiC structures, PF mechanism dominates FN tunneling of electrons from the accumulation layer of n-4H-SiC due to high density (up to 1013 cm-2) of carbon-related acceptor-like traps located at about 2.5 eV below the SiO2 conduction band (CB). These current conduction mechanisms were taken into account in studying hole injection/trapping into 10 nm-thick tunnel oxide on the Si face of 4H-SiC during electron injection from n-4H-SiC under high-field electrical stress with positive bias on the heavily doped n-type polysilicon (n+-polySi) gate at a wide range of temperatures between 27 and 200 °C. Holes were generated in the n+-polySi anode material by the hot-electrons during their transport through thin oxide films at oxide electric fields Eox from 5.6 to 8.0 MV/cm (prior to the intrinsic oxide breakdown field). Time-to-breakdown tBD of the gate dielectric was found to follow reciprocal field (1/E) model irrespective of stress temperatures. Despite the significant amount of process-induced interfacial electron traps contributing to a large amount of leakage current via PF emission in thermally grown SiO2 on the Si-face of n-4H-SiC, MOSiC devices having a 10 nm-thick SiO2 film can be safely used in 5 V TTL logic circuits over a period of 10 years.

Research paper thumbnail of Simulation of temperature dependent dielectric breakdown in n+-polySi/SiO2/n-6H-SiC structures during Poole-Frenkel stress at positive gate bias

Journal of Applied Physics, 2016

We present for the first time a thorough investigation of trapped-hole induced gate oxide deterio... more We present for the first time a thorough investigation of trapped-hole induced gate oxide deterioration and simulation results of time-dependent dielectric breakdown (TDDB) of thin (7–25 nm) silicon dioxide (SiO2) films thermally grown on (0 0 0 1) silicon (Si) face of n-type 6H-silicon carbide (n-6H-SiC). Gate oxide reliability was studied during both constant voltage and current stress with positive bias on the degenerately doped n-type poly-crystalline silicon (n+-polySi) gate at a wide range of temperatures between 27 and 225 °C. The gate leakage current was identified as the Poole-Frenkel (PF) emission of electrons trapped at an energy 0.92 eV below the SiO2 conduction band. Holes were generated in the n+-polySi anode material as well as in the oxide bulk via band-to-band ionization depending on the film thickness tox and the energy of the hot-electrons (emitted via PF mechanism) during their transport through oxide films at oxide electric fields Eox ranging from 5 to 10 MV/cm. Our simulated time-to-...

Research paper thumbnail of A Comparative Study of Gate Oxide Degradation During Low Fluence Fowler-Nordheim Stress in MOS Capacitors Grown on (100) and (111) n-Si

Physics of Semiconductor Devices, 1998

... INIST Diffusion. 2, Allée du Parc de Brabois F-54514 Vandoeuvre-lès-Nancy Cedex France Phone:... more ... INIST Diffusion. 2, Allée du Parc de Brabois F-54514 Vandoeuvre-lès-Nancy Cedex France Phone: +33 (0)3 83 50 46 64 Fax: +33 (0)3 83 50 46 66. ...

Research paper thumbnail of Trapped Hole Induced MOS Device Degradation During FN Stress

Proceedings of Spie the International Society For Optical Engineering, 1996

Research paper thumbnail of Modeling of trapped hole induced MOS device degradation during Fowler-Nordheim stress

1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings, 1996

Metal-Oxide-Silicon (MOS) device degradation due to trapped holes in the bulk of thin SiO/sub 2/ ... more Metal-Oxide-Silicon (MOS) device degradation due to trapped holes in the bulk of thin SiO/sub 2/ (22-33 nm) gate oxide during low fluence Fowler-Nordheim (FN) injection from the accumulated <100> n-Si of n/sup +/ polySi gate MOS capacitors has been theoretically modeled. The model is based on tunneling electron initiated band-to-band impact ionization (BTBII) as the possible source of generated holes. The validity of the present analysis has been compared with the experimental data of FN voltage shift /spl Delta/V/sub FN/ of Fazan et al. A comparative study of degradation during constant current and voltage FN stress is also presented.

Research paper thumbnail of Electrical Stress-Induced Degradation of HfAlO and HfO<sub>2</sub> Films of Equal EOT

Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials, 2008

Research paper thumbnail of Hole injection and dielectric breakdown in 6H–SiC and 4H–SiC metal–oxide–semiconductor structures during substrate electron injection via Fowler–Nordheim tunneling

Solid-State Electronics, 2015

Abstract Hole injection into silicon dioxide (SiO2) films (8–40 nm thick) is investigated for the... more Abstract Hole injection into silicon dioxide (SiO2) films (8–40 nm thick) is investigated for the first time during substrate electron injection via Fowler–Nordheim (FN) tunneling in n-type 4H- and 6H–SiC (silicon carbide) based metal–oxide–semiconductor (MOS) structures at a wide range of temperatures (T) between 298 and 598 K and oxide electric fields E ox from 6 to 10 MV/cm. Holes are generated in heavily doped n-type polycrystalline silicon ( n + -polySi) gate serving as the anode as well as in the bulk silicon dioxide (SiO2) film via hot-electron initiated band-to-band ionization (BTBI). In absence of oxide trapped charges, it is shown that at a given temperature, the hole injection rates from either of the above two mechanisms are higher in n-4H–SiC MOS devices than those in n-6H–SiC MOS structures when compared at a given E ox and SiO2 thickness ( t ox ). On the other hand, relative to n-4H–SiC devices, n-6H–SiC structures exhibit higher hole injection rates for a given t ox during substrate electron injection at a given FN current density j e , FN throughout the temperature range studied here. These two observations clearly reveal that the substrate material (n-6H–SiC and n-4H–SiC) dependencies on time-to-breakdown ( t BD ) or injected charge (electron) to breakdown ( Q BD ) of the SiO2 film depend on the mode of FN injections (constant field/voltage and current) from the substrate which is further verified from the rigorous device simulation as well.

Research paper thumbnail of Effect of nitridation of hafnium silicate gate dielectric on positive bias temperature instability in pMOS devices

2014 IEEE International Conference on Electron Devices and Solid-State Circuits, 2014

A detailed investigation of the effect of nitridation of hafnium silicate on positive bias temper... more A detailed investigation of the effect of nitridation of hafnium silicate on positive bias temperature instability (PBTI) in n+-polySi gate pMOS capacitor structures has been presented. Our analysis shows that nitridation improves the intrinsic oxide breakdown field, reduces the equivalent oxide thickness (EOT) and as-grown surface state density Dit by an order of magnitude. On the other hand, like NBTI degradation, nitridation significantly enhances PBTI degradation in pMOS devices causing reduction in PBTI lifetime at a given applied voltage VG. However, both nitrided and non-nitrided gate stacks reaches 10 year lifetime at an applied gate bias of 1.2 V.

Research paper thumbnail of A new degradation mechanism and its role on negative bias temperature instability in metal-oxide-semiconductor devices

2014 IEEE International Conference on Electron Devices and Solid-State Circuits, 2014

For the first time, an experimental investigation of dopant passivation/depassivation in the sili... more For the first time, an experimental investigation of dopant passivation/depassivation in the silicon substrate of metal-oxide-semiconductor (MOS) devices is presented during and after negative bias temperature stress (NBTS). It is believed that dopant passivation/depassivation is caused by hydrogen diffusion into the substrate forming complex with the dopant during NBTS and back diffusion of hydrogen from the passivated dopant atom during relaxation phase, respectively. The source of the diffusing hydrogen species responsible for dopant passivation during NBTS is the atomic hydrogen (Ho) liberated during interface state (Nit) generation by the hot electron impact with the Si3 ≡ SiH bonds at the Si/SiO2 interface. Dopant passivation mechanism significantly contributes in the measured threshold and flatband voltage shifts ΔVT and ΔVfb, respectively during NBTS. We propose that the experimentally observed new degradation phenomena should be taken into account in evaluation of the NBTI induced oxide charge trapping and interface trap creation.

Research paper thumbnail of Modeling of hole generation/trapping in ultrathin SiO{IN2} films during gate injection of electrons in direct tunneling regime

2009 2nd International Workshop on Electron Devices and Semiconductor Technology, 2009

An experimental investigation on oxide positive charge buildup in sub 3-nm silicon dioxide (SiO2)... more An experimental investigation on oxide positive charge buildup in sub 3-nm silicon dioxide (SiO2) films is presented during direct tunneling (DT) of electrons at -1.8 V of gate bias. The measurement results can be best explained by hole generation via anode hole injection (AHI) mechanism and the subsequent trapping of holes in the as-fabricated neutral hole traps in the oxide.

Research paper thumbnail of Reliability analysis of thin HfO<inf>2</inf>/SiO<inf>2</inf> gate dielectric stack

2007 International Workshop on Physics of Semiconductor Devices, 2007

Electrical characteristics of hafnium oxide (HfO2)/silicon dioxide (SiO2) gate dielectric stack d... more Electrical characteristics of hafnium oxide (HfO2)/silicon dioxide (SiO2) gate dielectric stack during both constant voltage stress (CVS) and constant current stress (CCS) have been experimentally investigated with varying thickness of the HfO2 layer. The generation kinetics of bulk, interface and border trapped charges have been discussed showing a correlation among them. Nature of intrinsic hole traps in SiO2 has also been studied from an independent charge relaxation experiment. In addition, time-dependent dielectric breakdown (TDDB) has been studied during CVS.

Research paper thumbnail of Influence of neutral hole traps in thin gate oxides on MOS device degradation during Fowler-Nordheim stress

1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings

oxide-silicon (MOS) device degradation due to trapping of positive charges in thin (27, 33 nm) Si... more oxide-silicon (MOS) device degradation due to trapping of positive charges in thin (27, 33 nm) Si02 gate oxides is presented. n+-polySi-gate (MOS) capacitors are stressed at a low electron injection fluence (<O.OI C/cm2) by Fowler-Nordheim (FN) electron tunneling &om the quantized accumulation layer of (100) n-Si substrate, at constant current and constant applied gate voltage. The present analysis assumes tunneling electron initiated band-lo-band impact ionization (BTBII) in SiO2, as the possible source of trapped holes during stress. The validity of the present analysis has been examined by comparing the theoretical values with the experhental data of FN threshold voltage shift AVFN of Fazan et al.

Research paper thumbnail of Effect of Silicon Wafer Surface Orientation on Gate Oxide Degradation during Constant Current Fowler-Nordheim Stress at Low Electron Fluence

Research paper thumbnail of On the electrical stress-induced degradation of ultrathin SiO2 in direct tunneling regime

Research paper thumbnail of Mechanism of oxide thickness and temperature dependent current conduction in n+-polySi/SiO2/p-Si structures — a new analysis

Journal of Semiconductors

The conduction mechanism of gate leakage current through thermally grown silicon dioxide (SiO 2 )... more The conduction mechanism of gate leakage current through thermally grown silicon dioxide (SiO 2 ) films on (100) p-type silicon has been investigated in detail under negative bias on the degenerately doped n-type polysilicon (n + -polySi) gate. The analysis utilizes the measured gate current density J G at high oxide fields E ox in 5.4 to 12 nm thick SiO 2 films between 25 and 300 °C. The leakage current measured up to 300 °C was due to Fowler–Nordheim (FN) tunneling of electrons from the accumulated n + -polySi gate in conjunction with Poole Frenkel (PF) emission of trapped-electrons from the electron traps located at energy levels ranging from 0.6 to 1.12 eV (depending on the oxide thickness) below the SiO 2 conduction band (CB). It was observed that PF emission current I PF dominates FN electron tunneling current I FN at oxide electric fields E ox between 6 and 10 MV/cm and throughout the temperature range studied here. Understanding of the mechanism of leakage current conduction through SiO 2 films plays a crucial role in simulation of time-dependent dielectric breakdown (TDDB) of metaloxide–semiconductor (MOS) devices and to precisely predict the normal operating field or applied gate voltage for lifetime projection of the MOS integrated circuits.

Research paper thumbnail of Efficient methodology for estimation of metal effective work function, interface trap, and fixed oxide charges in metal-oxide-semiconductor capacitors with dual layer high - κ/SiO2 dielectric

Journal of Vacuum Science & Technology B

A capacitance-voltage (C-V) based efficient methodology is demonstrated for precise estimation of... more A capacitance-voltage (C-V) based efficient methodology is demonstrated for precise estimation of process-induced various fixed charge distributions in the dielectric layer, interface trapped charges at the silicon/oxide interface, and the effective work function (EWF) of the metal gate on double layer high-κ/silicon dioxide (SiO 2) stack in metal-oxide-semiconductor (MOS) capacitors. The present technique takes care of the variation of the work function of the silicon substrate either due to waferto-wafer variation or nonuniformity of the doping level throughout the entire wafer. The analysis is verified with experimentally obtained high-frequency C-V results by varying only the physical thickness t HfO 2 of the hafnium oxide (HfO 2) dielectric layer on an interfacial SiO 2 film of a fixed thickness t ox in tantalum nitride (TaN)/HfO 2 /SiO 2 /p-Si MOS diodes. A value of 4.5 eV was obtained for EWF of physical vapor deposited TaN on HfO 2. Furthermore, the calculations indicate the presence of a significant amount of positive bulk charges in the high-κ layer, in addition to interface trapped positive charges Q it at the Si/SiO 2 interface and negative effective charges at both the high-κ/SiO 2 and Si/SiO 2 interfaces.

Research paper thumbnail of A comprehensive technique for estimation of process-induced fixed charges and effective work function of the metal gate on high-κ/SiO2 stack

Semiconductor Science and Technology

Research paper thumbnail of Mechanistic analysis of temperature-dependent current conduction through thin tunnel oxide in n+-polySi/SiO2/n+-Si structures

Journal of Applied Physics

We present a detailed investigation on temperature-dependent current conduction through thin tunn... more We present a detailed investigation on temperature-dependent current conduction through thin tunnel oxides grown on degenerately doped n-type silicon (n þ-Si) under positive bias (V G) on heavily doped n-type polycrystalline silicon (n þ-polySi) gate in metal-oxide-semiconductor devices. The leakage current measured between 298 and 573 K and at oxide fields ranging from 6 to 10 MV/cm is primarily attributed to Poole-Frenkel (PF) emission of trapped electrons from the neutral electron traps located in the silicon dioxide (SiO 2) band gap in addition to Fowler-Nordheim (FN) tunneling of electrons from n þ-Si acting as the drain node in FLOating gate Tunnel OXide Electrically Erasable Programmable Read-Only Memory devices. Process-induced neutral electron traps are located at 0.18 eV and 0.9 eV below the SiO 2 conduction band. Throughout the temperature range studied here, PF emission current I PF dominates FN electron tunneling current I FN at oxide electric fields E ox between 6 and 10 MV/cm. A physics based new analytical formula has been developed for FN tunneling of electrons from the accumulation layer of degenerate semiconductors at a wide range of temperatures incorporating the image force barrier rounding effect. FN tunneling has been formulated in the framework of Wentzel-Kramers-Brilloiun taking into account the correction factor due to abrupt variation of the energy barrier at the cathode/oxide interface. The effect of interfacial and near-interfacial trapped-oxide charges on FN tunneling has also been investigated in detail at positive V G. The mechanism of leakage current conduction through SiO 2 films plays a crucial role in simulation of time-dependent dielectric breakdown of the memory devices and to precisely predict the normal operating field or applied floating gate (FG) voltage for lifetime projection of the devices. In addition, we present theoretical results showing the effect of drain doping concentration on the FG leakage current.

Research paper thumbnail of Current conduction mechanisms through thin tunnel oxide during erase operation of flash electrically erasable programmable read-only memory devices

Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena

The mechanism of current conduction through thin tunnel oxide during erase operation of flash ele... more The mechanism of current conduction through thin tunnel oxide during erase operation of flash electrically erasable programmable read-only memory devices has been studied both theoretically and experimentally. The floating gate (FG) leakage current measured between 25 and 300 °C and at oxide fields ranging from 6 to 10 MV/cm is primarily attributed to Poole–Frenkel (PF) emission of trapped electrons from the electron traps located at about 1.0 eV below the silicon dioxide conduction band in addition to Fowler–Nordheim (FN) tunneling of electrons from the degenerately doped n-type polycrystalline silicon (n+-polySi) FG. It is observed that PF emission current IPF dominates FN electron tunneling current IFN at oxide electric fields Eox between 6 and 10 MV/cm and throughout the temperature range studied here. The observed thickness dependence of FG leakage current at a given applied oxide field arises due to different electron trap concentrations in the oxide. A physics based new temperature dependent analytical formula has also been developed for FN tunneling of electrons from the accumulation layer of semiconductors. In addition, the authors present theoretical results showing the effect of the FG doping concentration on the leakage current.The mechanism of current conduction through thin tunnel oxide during erase operation of flash electrically erasable programmable read-only memory devices has been studied both theoretically and experimentally. The floating gate (FG) leakage current measured between 25 and 300 °C and at oxide fields ranging from 6 to 10 MV/cm is primarily attributed to Poole–Frenkel (PF) emission of trapped electrons from the electron traps located at about 1.0 eV below the silicon dioxide conduction band in addition to Fowler–Nordheim (FN) tunneling of electrons from the degenerately doped n-type polycrystalline silicon (n+-polySi) FG. It is observed that PF emission current IPF dominates FN electron tunneling current IFN at oxide electric fields Eox between 6 and 10 MV/cm and throughout the temperature range studied here. The observed thickness dependence of FG leakage current at a given applied oxide field arises due to different electron trap concentrations in the oxide. A physics based new temperature dependent analyt...

Research paper thumbnail of Leakage current conduction, hole injection, and time-dependent dielectric breakdown ofn-4H-SiC MOS capacitors during positive bias temperature stress

Journal of Applied Physics

The conduction mechanism(s) of gate leakage current JG through thermally grown silicon dioxide (S... more The conduction mechanism(s) of gate leakage current JG through thermally grown silicon dioxide (SiO2) films on the silicon (Si) face of n-type 4H-silicon carbide (4H-SiC) has been studied in detail under positive gate bias. It was observed that at an oxide field above 5 MV/cm, the leakage current measured up to 303 °C can be explained by Fowler-Nordheim (FN) tunneling of electrons from the accumulated n-4H-SiC and Poole-Frenkel (PF) emission of trapped electrons from the localized neutral traps located at ≈2.5 eV below the SiO2 conduction band. However, the PF emission current IPF dominates the FN electron tunneling current IFN at oxide electric fields Eox between 5 and 10 MV/cm and in the temperature ranging from 31 to 303 °C. In addition, we have presented a comprehensive analysis of injection of holes and their subsequent trapping into as-grown oxide traps eventually leading to time-dependent dielectric breakdown during electron injection under positive bias temperature stress (PBTS) in n-4H-SiC metal-...

Research paper thumbnail of Leakage current conduction and reliability assessment of passivating thin silicon dioxide films on n -4H-SiC

Hard X-Ray, Gamma-Ray, and Neutron Detector Physics XVIII, 2016

We have analyzed the mechanisms of leakage current conduction in passivating silicon dioxide (SiO... more We have analyzed the mechanisms of leakage current conduction in passivating silicon dioxide (SiO2) films grown on (0 0 0 1) silicon (Si) face of n-type 4H-SiC (silicon carbide). It was observed that the experimentally measured gate current density in metal-oxide-silicon carbide (MOSiC) structures under positive gate bias at an oxide field Eox above 5 MV/cm is comprised of Fowler-Nordheim (FN) tunneling of electrons from the accumulated n-4H-SiC and Poole-Frenkel (PF) emission of trapped electrons from the localized neutral traps in the SiO2 gap, IFN and IPF, respectively at temperatures between 27 and 200 °C. In MOSiC structures, PF mechanism dominates FN tunneling of electrons from the accumulation layer of n-4H-SiC due to high density (up to 1013 cm-2) of carbon-related acceptor-like traps located at about 2.5 eV below the SiO2 conduction band (CB). These current conduction mechanisms were taken into account in studying hole injection/trapping into 10 nm-thick tunnel oxide on the Si face of 4H-SiC during electron injection from n-4H-SiC under high-field electrical stress with positive bias on the heavily doped n-type polysilicon (n+-polySi) gate at a wide range of temperatures between 27 and 200 °C. Holes were generated in the n+-polySi anode material by the hot-electrons during their transport through thin oxide films at oxide electric fields Eox from 5.6 to 8.0 MV/cm (prior to the intrinsic oxide breakdown field). Time-to-breakdown tBD of the gate dielectric was found to follow reciprocal field (1/E) model irrespective of stress temperatures. Despite the significant amount of process-induced interfacial electron traps contributing to a large amount of leakage current via PF emission in thermally grown SiO2 on the Si-face of n-4H-SiC, MOSiC devices having a 10 nm-thick SiO2 film can be safely used in 5 V TTL logic circuits over a period of 10 years.

Research paper thumbnail of Simulation of temperature dependent dielectric breakdown in n+-polySi/SiO2/n-6H-SiC structures during Poole-Frenkel stress at positive gate bias

Journal of Applied Physics, 2016

We present for the first time a thorough investigation of trapped-hole induced gate oxide deterio... more We present for the first time a thorough investigation of trapped-hole induced gate oxide deterioration and simulation results of time-dependent dielectric breakdown (TDDB) of thin (7–25 nm) silicon dioxide (SiO2) films thermally grown on (0 0 0 1) silicon (Si) face of n-type 6H-silicon carbide (n-6H-SiC). Gate oxide reliability was studied during both constant voltage and current stress with positive bias on the degenerately doped n-type poly-crystalline silicon (n+-polySi) gate at a wide range of temperatures between 27 and 225 °C. The gate leakage current was identified as the Poole-Frenkel (PF) emission of electrons trapped at an energy 0.92 eV below the SiO2 conduction band. Holes were generated in the n+-polySi anode material as well as in the oxide bulk via band-to-band ionization depending on the film thickness tox and the energy of the hot-electrons (emitted via PF mechanism) during their transport through oxide films at oxide electric fields Eox ranging from 5 to 10 MV/cm. Our simulated time-to-...

Research paper thumbnail of A Comparative Study of Gate Oxide Degradation During Low Fluence Fowler-Nordheim Stress in MOS Capacitors Grown on (100) and (111) n-Si

Physics of Semiconductor Devices, 1998

... INIST Diffusion. 2, Allée du Parc de Brabois F-54514 Vandoeuvre-lès-Nancy Cedex France Phone:... more ... INIST Diffusion. 2, Allée du Parc de Brabois F-54514 Vandoeuvre-lès-Nancy Cedex France Phone: +33 (0)3 83 50 46 64 Fax: +33 (0)3 83 50 46 66. ...

Research paper thumbnail of Trapped Hole Induced MOS Device Degradation During FN Stress

Proceedings of Spie the International Society For Optical Engineering, 1996

Research paper thumbnail of Modeling of trapped hole induced MOS device degradation during Fowler-Nordheim stress

1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings, 1996

Metal-Oxide-Silicon (MOS) device degradation due to trapped holes in the bulk of thin SiO/sub 2/ ... more Metal-Oxide-Silicon (MOS) device degradation due to trapped holes in the bulk of thin SiO/sub 2/ (22-33 nm) gate oxide during low fluence Fowler-Nordheim (FN) injection from the accumulated <100> n-Si of n/sup +/ polySi gate MOS capacitors has been theoretically modeled. The model is based on tunneling electron initiated band-to-band impact ionization (BTBII) as the possible source of generated holes. The validity of the present analysis has been compared with the experimental data of FN voltage shift /spl Delta/V/sub FN/ of Fazan et al. A comparative study of degradation during constant current and voltage FN stress is also presented.

Research paper thumbnail of Electrical Stress-Induced Degradation of HfAlO and HfO<sub>2</sub> Films of Equal EOT

Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials, 2008

Research paper thumbnail of Hole injection and dielectric breakdown in 6H–SiC and 4H–SiC metal–oxide–semiconductor structures during substrate electron injection via Fowler–Nordheim tunneling

Solid-State Electronics, 2015

Abstract Hole injection into silicon dioxide (SiO2) films (8–40 nm thick) is investigated for the... more Abstract Hole injection into silicon dioxide (SiO2) films (8–40 nm thick) is investigated for the first time during substrate electron injection via Fowler–Nordheim (FN) tunneling in n-type 4H- and 6H–SiC (silicon carbide) based metal–oxide–semiconductor (MOS) structures at a wide range of temperatures (T) between 298 and 598 K and oxide electric fields E ox from 6 to 10 MV/cm. Holes are generated in heavily doped n-type polycrystalline silicon ( n + -polySi) gate serving as the anode as well as in the bulk silicon dioxide (SiO2) film via hot-electron initiated band-to-band ionization (BTBI). In absence of oxide trapped charges, it is shown that at a given temperature, the hole injection rates from either of the above two mechanisms are higher in n-4H–SiC MOS devices than those in n-6H–SiC MOS structures when compared at a given E ox and SiO2 thickness ( t ox ). On the other hand, relative to n-4H–SiC devices, n-6H–SiC structures exhibit higher hole injection rates for a given t ox during substrate electron injection at a given FN current density j e , FN throughout the temperature range studied here. These two observations clearly reveal that the substrate material (n-6H–SiC and n-4H–SiC) dependencies on time-to-breakdown ( t BD ) or injected charge (electron) to breakdown ( Q BD ) of the SiO2 film depend on the mode of FN injections (constant field/voltage and current) from the substrate which is further verified from the rigorous device simulation as well.

Research paper thumbnail of Effect of nitridation of hafnium silicate gate dielectric on positive bias temperature instability in pMOS devices

2014 IEEE International Conference on Electron Devices and Solid-State Circuits, 2014

A detailed investigation of the effect of nitridation of hafnium silicate on positive bias temper... more A detailed investigation of the effect of nitridation of hafnium silicate on positive bias temperature instability (PBTI) in n+-polySi gate pMOS capacitor structures has been presented. Our analysis shows that nitridation improves the intrinsic oxide breakdown field, reduces the equivalent oxide thickness (EOT) and as-grown surface state density Dit by an order of magnitude. On the other hand, like NBTI degradation, nitridation significantly enhances PBTI degradation in pMOS devices causing reduction in PBTI lifetime at a given applied voltage VG. However, both nitrided and non-nitrided gate stacks reaches 10 year lifetime at an applied gate bias of 1.2 V.

Research paper thumbnail of A new degradation mechanism and its role on negative bias temperature instability in metal-oxide-semiconductor devices

2014 IEEE International Conference on Electron Devices and Solid-State Circuits, 2014

For the first time, an experimental investigation of dopant passivation/depassivation in the sili... more For the first time, an experimental investigation of dopant passivation/depassivation in the silicon substrate of metal-oxide-semiconductor (MOS) devices is presented during and after negative bias temperature stress (NBTS). It is believed that dopant passivation/depassivation is caused by hydrogen diffusion into the substrate forming complex with the dopant during NBTS and back diffusion of hydrogen from the passivated dopant atom during relaxation phase, respectively. The source of the diffusing hydrogen species responsible for dopant passivation during NBTS is the atomic hydrogen (Ho) liberated during interface state (Nit) generation by the hot electron impact with the Si3 ≡ SiH bonds at the Si/SiO2 interface. Dopant passivation mechanism significantly contributes in the measured threshold and flatband voltage shifts ΔVT and ΔVfb, respectively during NBTS. We propose that the experimentally observed new degradation phenomena should be taken into account in evaluation of the NBTI induced oxide charge trapping and interface trap creation.

Research paper thumbnail of Modeling of hole generation/trapping in ultrathin SiO{IN2} films during gate injection of electrons in direct tunneling regime

2009 2nd International Workshop on Electron Devices and Semiconductor Technology, 2009

An experimental investigation on oxide positive charge buildup in sub 3-nm silicon dioxide (SiO2)... more An experimental investigation on oxide positive charge buildup in sub 3-nm silicon dioxide (SiO2) films is presented during direct tunneling (DT) of electrons at -1.8 V of gate bias. The measurement results can be best explained by hole generation via anode hole injection (AHI) mechanism and the subsequent trapping of holes in the as-fabricated neutral hole traps in the oxide.

Research paper thumbnail of Reliability analysis of thin HfO<inf>2</inf>/SiO<inf>2</inf> gate dielectric stack

2007 International Workshop on Physics of Semiconductor Devices, 2007

Electrical characteristics of hafnium oxide (HfO2)/silicon dioxide (SiO2) gate dielectric stack d... more Electrical characteristics of hafnium oxide (HfO2)/silicon dioxide (SiO2) gate dielectric stack during both constant voltage stress (CVS) and constant current stress (CCS) have been experimentally investigated with varying thickness of the HfO2 layer. The generation kinetics of bulk, interface and border trapped charges have been discussed showing a correlation among them. Nature of intrinsic hole traps in SiO2 has also been studied from an independent charge relaxation experiment. In addition, time-dependent dielectric breakdown (TDDB) has been studied during CVS.