Osama A . Abulnaja | King AbdulAziz University (KAU) Jeddah, Saudi Arabia (original) (raw)

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Papers by Osama A . Abulnaja

Research paper thumbnail of Evaluation of HFT

In earlier work we have introduced an efficient hardware fault-tolerant approach for reliable exe... more In earlier work we have introduced an efficient hardware fault-tolerant approach for reliable execution of tasks. The proposed approach called the Hardware Fault-Tolerant (HFT) approach. Also, we have introduced the concept of dynamic group maximum matching, which is used to group nodes of a graph into disjoint groups with different sizes dynamically. Furthermore, we have proposed the Dynamic Group Maximum Matching (DGMM) algorithm for finding the dynamic group maximum matching. In addition, we have proposed several hardware fault-tolerant scheduling algorithms, based on the HFT technique and the DGMM algorithm. In this work, we studied the effect of the HFT technique on system performance for four of the proposed scheduling algorithms. The studied algorithms are: Hardware Fault-Tolerant (FCFS + First

Research paper thumbnail of Performance Evaluation of Integrated Fault-Tolerant Technique: Simulation Study

In earlier work we have proposed the concept of the dynamic group maximum matching for grouping t... more In earlier work we have proposed the concept of the dynamic group maximum matching for grouping the system graph into groups of different sizes according to the tasks arriving at the system. Also, we have developed a more efficient integrated fault-tolerant technique for ultra-reliable execution of tasks where both hardware (processors and communication channels) and software failures, and on-line fault diagnosis are considered. The proposed approach called the Integrated Fault-Tolerant (IFT) approach. Furthermore, we have proposed integrated fault-tolerant scheduling algorithms. The introduced algorithms are based on the dynamic group maximum matching concept and the IFT technique. In this work, we studied the effect of the IFT technique on system performance for four of the proposed scheduling algorithms. The algorithms are: Integrated Fault-Tolerant First-Come, First-Served (FCFS), Integrated Fault-Tolerant (FCFS + Smallest Fits First) (FCFSSFF) scheduling algorithm, Integrated F...

Research paper thumbnail of Evaluation of HFT Technique Performance Using Task-Scheduling Algorithms

In earlier work we have introduced an efficient hardware fault-tolerant approach for reliable exe... more In earlier work we have introduced an efficient hardware fault-tolerant approach for reliable execution of tasks. The proposed approach called the Hardware Fault-Tolerant (HFT) approach. Also, we have introduced the concept of dynamic group maximum matching, which is used to group nodes of a graph into disjoint groups with different sizes dynamically. Furthermore, we have proposed the Dynamic Group Maximum Matching (DGMM) algorithm for finding the dynamic group maximum matching. In addition, we have proposed several hardware fault-tolerant scheduling algorithms, based on the HFT technique and the DGMM algorithm. In this work, we studied the effect of the HFT technique on system performance for four of the proposed scheduling algorithms. The studied algorithms are: Hardware Fault-Tolerant (FCFS + First Disagreement Graph First + First Started First), Hardware Fault-Tolerant (FCFS + First Fit First + First Disagreement Graph First + First Started First), Hardware Fault-Tolerant (FCFS ...

Research paper thumbnail of Analyzing Power and Energy Efficiency of Bitonic Mergesort Based on Performance Evaluation

IEEE Access

In graphics processing unit (GPU) computing community, bitonic mergesort (BM) is recognized as on... more In graphics processing unit (GPU) computing community, bitonic mergesort (BM) is recognized as one of the most investigated sorting algorithms. It is specially designed for parallel architectures, requires minor inter-process communication, can be implemented in-place, and is logically appropriate for single instructions multiple data platforms. In addition, GPUs have shown tremendous improvements in power and performance efficiency and thus have become essential ingredients in pursuit of the prospective exascale systems whose major obstacle is the excessive power consumption. In a recent research work, we found that fundamental software building blocks can offer a reasonable amount of power and energy saving that can offer new ways to tackle the power obstacle of the prospective exascale systems. We evaluated average peak power, average energy, and average kernel runtime of BM under various workloads and compared it with advanced quicksort (AQ). The results showed that BM outperformed AQ based on all the three metrics in most cases. In this paper, we further investigate BM to identify the factors that result in its underlying power and energy efficiency advantage over AQ. We analyze the power and energy efficiency of BM and AQ based on their performance evaluation on NVIDIA K40 GPU. The performance of both the algorithms is investigated using various experiments offered by NVIDIA Nsight Visual Studio.

Research paper thumbnail of Evaluating Power and Energy Efficiency of Bitonic Mergesort on Graphics Processing Unit

IEEE Access

Excessive power consumption is expected to be the major obstacle to achieve exascale performance ... more Excessive power consumption is expected to be the major obstacle to achieve exascale performance within a reasonable power budget in the upcoming years. In addition, graphics processing units (GPUs) are expected to become a significant ingredient in the pursuit of exascale computing due to their fine-grained, highly parallel architecture and advancements in performance and power efficiency. To address the power obstacle of exascale systems, we suggest evaluating power and energy consumption of the fundamental software building blocks. We experimentally investigate power consumption, energy consumption, and kernel runtime of Bitonic Mergesort (a promising sort for parallel architectures) under various workloads on NVIDIA K40 GPU. The results show some insights in terms of power and energy consumption advantage of Bitonic Mergesort compared with NVIDIA's Advanced Quicksort (a highly optimized parallel quicksort).

Research paper thumbnail of Semantic Sentiment Analysis of Arabic Texts

International Journal of Advanced Computer Science and Applications, 2017

Twitter considered as a rich resource to collect people's opinions in different domains and attra... more Twitter considered as a rich resource to collect people's opinions in different domains and attracted researchers to develop an automatic Sentiment Analysis (SA) model for tweets. In this work, a semantic Arabic Twitter Sentiment Analysis (ATSA) model is developed based on supervised machine learning (ML) approaches and semantic analysis. Most of the existing Arabic SA approaches represent tweets based on the bag-ofwords (BoW) model. The main limitation of this model is that it is semantically weak; where words considered as independent features and ignore the semantic associations between them. As a result, synonymous words that appear in two tweets are represented as different independent features. To overcome this limitation, this work proposes enriching the tweets representation with concepts utilizing Arabic WordNet (AWN) as an external knowledge base. In addition, different concepts representation approaches are developed and evaluated with naïve Bayes (NB) and support vector machine (SVM) ML classifiers on an Arabic Twitter dataset. The experimental results indicate that using concepts features improves the performance of the ATSA model compared with the basic BoW representation. The improvement reached 4.48% with the SVM classifier and 5.78% with the NB classifier.

Research paper thumbnail of Evaluation of HFT Technique Performance Using Task-Scheduling Algorithms

In earlier work we have introduced an efficient hardware fault-tolerant approach for reliable exe... more In earlier work we have introduced an efficient hardware fault-tolerant approach for reliable execution of tasks. The proposed approach called the Hardware Fault-Tolerant (HFT) approach. Also, we have introduced the concept of dynamic group maximum matching, which is used to group nodes of a graph into disjoint groups with different sizes dynamically. Furthermore, we have proposed the Dynamic Group Maximum

Research paper thumbnail of On the effect of recovery block scheme on system performance

Proceedings Twenty-First Annual International Computer Software and Applications Conference (COMPSAC'97), 1997

In this work, we study the effect of the traditional Sequential Recovery Block (SRB) and the Dist... more In this work, we study the effect of the traditional Sequential Recovery Block (SRB) and the Distributed Recovery Block (DRB) schemes o n syst e m performance (system average throughput, system mean response time, and percentage of tasks of a certain type completed) f o r two new software faulttolerant scheduling algorithms-Sequential Recovery Block Round-Robin (SRBRR) scheduling algorithm and Distributed Recovery Block Round-Robin (DR-BRR) scheduling algorithm.

Research paper thumbnail of Performability Evaluation of the Recovery Block Scheme

Research paper thumbnail of Evaluating Performability of A System Under N-Version Programming Scheme

Research paper thumbnail of Scheduling Algorithms for Recovery Block Scheme

Research paper thumbnail of Reliable Execution of Tasks Under Both Hardware and Software Faults

Research paper thumbnail of Reliability Evaluation of the N-Modular Redundancy Technique

Research paper thumbnail of Reliability Estimation of Hardware Fault-Tolerant Techniques: Comparison Study

Research paper thumbnail of An Assertion Language for Object-Oriented Systems Testing

Research paper thumbnail of Hardware Fault-Tolerant Scheduling Algorithms

Research paper thumbnail of Software Fault-Tolerant Scheduling Algorithms

Research paper thumbnail of Dynamic Tester for Object-Oriented Systems

Research paper thumbnail of Fault-Tolerant Hardware and Software Co-Design and Performance Evaluation

Research paper thumbnail of Building a New Use Case Sub-Tool for Component-Based Software Development

In this work, we proposed and built a new UML-Based use case sub-tool for analysis of component-b... more In this work, we proposed and built a new UML-Based use case sub-tool for analysis of component-based software systems. The introduced use case sub-tool draws the use case model for application under development. It can be used to generate the use case model for object-oriented applications and component-based applications.

Research paper thumbnail of Evaluation of HFT

In earlier work we have introduced an efficient hardware fault-tolerant approach for reliable exe... more In earlier work we have introduced an efficient hardware fault-tolerant approach for reliable execution of tasks. The proposed approach called the Hardware Fault-Tolerant (HFT) approach. Also, we have introduced the concept of dynamic group maximum matching, which is used to group nodes of a graph into disjoint groups with different sizes dynamically. Furthermore, we have proposed the Dynamic Group Maximum Matching (DGMM) algorithm for finding the dynamic group maximum matching. In addition, we have proposed several hardware fault-tolerant scheduling algorithms, based on the HFT technique and the DGMM algorithm. In this work, we studied the effect of the HFT technique on system performance for four of the proposed scheduling algorithms. The studied algorithms are: Hardware Fault-Tolerant (FCFS + First

Research paper thumbnail of Performance Evaluation of Integrated Fault-Tolerant Technique: Simulation Study

In earlier work we have proposed the concept of the dynamic group maximum matching for grouping t... more In earlier work we have proposed the concept of the dynamic group maximum matching for grouping the system graph into groups of different sizes according to the tasks arriving at the system. Also, we have developed a more efficient integrated fault-tolerant technique for ultra-reliable execution of tasks where both hardware (processors and communication channels) and software failures, and on-line fault diagnosis are considered. The proposed approach called the Integrated Fault-Tolerant (IFT) approach. Furthermore, we have proposed integrated fault-tolerant scheduling algorithms. The introduced algorithms are based on the dynamic group maximum matching concept and the IFT technique. In this work, we studied the effect of the IFT technique on system performance for four of the proposed scheduling algorithms. The algorithms are: Integrated Fault-Tolerant First-Come, First-Served (FCFS), Integrated Fault-Tolerant (FCFS + Smallest Fits First) (FCFSSFF) scheduling algorithm, Integrated F...

Research paper thumbnail of Evaluation of HFT Technique Performance Using Task-Scheduling Algorithms

In earlier work we have introduced an efficient hardware fault-tolerant approach for reliable exe... more In earlier work we have introduced an efficient hardware fault-tolerant approach for reliable execution of tasks. The proposed approach called the Hardware Fault-Tolerant (HFT) approach. Also, we have introduced the concept of dynamic group maximum matching, which is used to group nodes of a graph into disjoint groups with different sizes dynamically. Furthermore, we have proposed the Dynamic Group Maximum Matching (DGMM) algorithm for finding the dynamic group maximum matching. In addition, we have proposed several hardware fault-tolerant scheduling algorithms, based on the HFT technique and the DGMM algorithm. In this work, we studied the effect of the HFT technique on system performance for four of the proposed scheduling algorithms. The studied algorithms are: Hardware Fault-Tolerant (FCFS + First Disagreement Graph First + First Started First), Hardware Fault-Tolerant (FCFS + First Fit First + First Disagreement Graph First + First Started First), Hardware Fault-Tolerant (FCFS ...

Research paper thumbnail of Analyzing Power and Energy Efficiency of Bitonic Mergesort Based on Performance Evaluation

IEEE Access

In graphics processing unit (GPU) computing community, bitonic mergesort (BM) is recognized as on... more In graphics processing unit (GPU) computing community, bitonic mergesort (BM) is recognized as one of the most investigated sorting algorithms. It is specially designed for parallel architectures, requires minor inter-process communication, can be implemented in-place, and is logically appropriate for single instructions multiple data platforms. In addition, GPUs have shown tremendous improvements in power and performance efficiency and thus have become essential ingredients in pursuit of the prospective exascale systems whose major obstacle is the excessive power consumption. In a recent research work, we found that fundamental software building blocks can offer a reasonable amount of power and energy saving that can offer new ways to tackle the power obstacle of the prospective exascale systems. We evaluated average peak power, average energy, and average kernel runtime of BM under various workloads and compared it with advanced quicksort (AQ). The results showed that BM outperformed AQ based on all the three metrics in most cases. In this paper, we further investigate BM to identify the factors that result in its underlying power and energy efficiency advantage over AQ. We analyze the power and energy efficiency of BM and AQ based on their performance evaluation on NVIDIA K40 GPU. The performance of both the algorithms is investigated using various experiments offered by NVIDIA Nsight Visual Studio.

Research paper thumbnail of Evaluating Power and Energy Efficiency of Bitonic Mergesort on Graphics Processing Unit

IEEE Access

Excessive power consumption is expected to be the major obstacle to achieve exascale performance ... more Excessive power consumption is expected to be the major obstacle to achieve exascale performance within a reasonable power budget in the upcoming years. In addition, graphics processing units (GPUs) are expected to become a significant ingredient in the pursuit of exascale computing due to their fine-grained, highly parallel architecture and advancements in performance and power efficiency. To address the power obstacle of exascale systems, we suggest evaluating power and energy consumption of the fundamental software building blocks. We experimentally investigate power consumption, energy consumption, and kernel runtime of Bitonic Mergesort (a promising sort for parallel architectures) under various workloads on NVIDIA K40 GPU. The results show some insights in terms of power and energy consumption advantage of Bitonic Mergesort compared with NVIDIA's Advanced Quicksort (a highly optimized parallel quicksort).

Research paper thumbnail of Semantic Sentiment Analysis of Arabic Texts

International Journal of Advanced Computer Science and Applications, 2017

Twitter considered as a rich resource to collect people's opinions in different domains and attra... more Twitter considered as a rich resource to collect people's opinions in different domains and attracted researchers to develop an automatic Sentiment Analysis (SA) model for tweets. In this work, a semantic Arabic Twitter Sentiment Analysis (ATSA) model is developed based on supervised machine learning (ML) approaches and semantic analysis. Most of the existing Arabic SA approaches represent tweets based on the bag-ofwords (BoW) model. The main limitation of this model is that it is semantically weak; where words considered as independent features and ignore the semantic associations between them. As a result, synonymous words that appear in two tweets are represented as different independent features. To overcome this limitation, this work proposes enriching the tweets representation with concepts utilizing Arabic WordNet (AWN) as an external knowledge base. In addition, different concepts representation approaches are developed and evaluated with naïve Bayes (NB) and support vector machine (SVM) ML classifiers on an Arabic Twitter dataset. The experimental results indicate that using concepts features improves the performance of the ATSA model compared with the basic BoW representation. The improvement reached 4.48% with the SVM classifier and 5.78% with the NB classifier.

Research paper thumbnail of Evaluation of HFT Technique Performance Using Task-Scheduling Algorithms

In earlier work we have introduced an efficient hardware fault-tolerant approach for reliable exe... more In earlier work we have introduced an efficient hardware fault-tolerant approach for reliable execution of tasks. The proposed approach called the Hardware Fault-Tolerant (HFT) approach. Also, we have introduced the concept of dynamic group maximum matching, which is used to group nodes of a graph into disjoint groups with different sizes dynamically. Furthermore, we have proposed the Dynamic Group Maximum

Research paper thumbnail of On the effect of recovery block scheme on system performance

Proceedings Twenty-First Annual International Computer Software and Applications Conference (COMPSAC'97), 1997

In this work, we study the effect of the traditional Sequential Recovery Block (SRB) and the Dist... more In this work, we study the effect of the traditional Sequential Recovery Block (SRB) and the Distributed Recovery Block (DRB) schemes o n syst e m performance (system average throughput, system mean response time, and percentage of tasks of a certain type completed) f o r two new software faulttolerant scheduling algorithms-Sequential Recovery Block Round-Robin (SRBRR) scheduling algorithm and Distributed Recovery Block Round-Robin (DR-BRR) scheduling algorithm.

Research paper thumbnail of Performability Evaluation of the Recovery Block Scheme

Research paper thumbnail of Evaluating Performability of A System Under N-Version Programming Scheme

Research paper thumbnail of Scheduling Algorithms for Recovery Block Scheme

Research paper thumbnail of Reliable Execution of Tasks Under Both Hardware and Software Faults

Research paper thumbnail of Reliability Evaluation of the N-Modular Redundancy Technique

Research paper thumbnail of Reliability Estimation of Hardware Fault-Tolerant Techniques: Comparison Study

Research paper thumbnail of An Assertion Language for Object-Oriented Systems Testing

Research paper thumbnail of Hardware Fault-Tolerant Scheduling Algorithms

Research paper thumbnail of Software Fault-Tolerant Scheduling Algorithms

Research paper thumbnail of Dynamic Tester for Object-Oriented Systems

Research paper thumbnail of Fault-Tolerant Hardware and Software Co-Design and Performance Evaluation

Research paper thumbnail of Building a New Use Case Sub-Tool for Component-Based Software Development

In this work, we proposed and built a new UML-Based use case sub-tool for analysis of component-b... more In this work, we proposed and built a new UML-Based use case sub-tool for analysis of component-based software systems. The introduced use case sub-tool draws the use case model for application under development. It can be used to generate the use case model for object-oriented applications and component-based applications.