Zeinab Ramezani, Ph.D. | University of Miami (original) (raw)

Papers by Zeinab Ramezani, Ph.D.

Research paper thumbnail of Amended Electric Field Distribution: A Reliable Technique for Electrical Performance Improvement in Nano scale SOI MOSFETs

Journal of Electronic Materials, 2017

To achieve reliable transistors, we propose a new silicon-on-insulator (SOI) metal-oxide-semicond... more To achieve reliable transistors, we propose a new silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) with an amended electric field in the channel for improved electrical and thermal performance, with an emphasis on current leakage improvement. The amended electric field leads to lower electric field crowding and thereby we assume enhanced reliability, leakage current, gate-induced drain leakage (GIDL), and electron temperature. To modify the electric field distribution, an additional rectangular metal region (RMR) is utilized in the buried oxide of the SOI MOSFET. The location and dimensions of the RMR have been carefully optimized to achieve the best results. The electrical, thermal, and radiofrequency characteristics of the proposed structure were analyzed using two-dimensional (2-D) numerical simulations and compared with the characteristics of the conventional, fully depleted SOI MOSFET (C-SOI). Also, critical short-channel effects (SCEs) such as threshold voltage, drain-induced barrier lowering (DIBL), subthreshold slope degradation, hot-carrier effect, GIDL, and leakage power consumption are improved. According to the results obtained, the proposed nano SOI MOSFET is a reliable device, especially for use in low-power and high-temperature applications.

Research paper thumbnail of Gated graphene islands enabled tunable charge transfer plasmon terahertz metamodulator

Nanoscale, 2019

Graphene-enhanced optoelectronic terahertz (THz) signal processing offers an exquisite potential ... more Graphene-enhanced optoelectronic terahertz (THz) signal processing offers an exquisite potential for tailoring extreme-subwavelength platforms to develop tunable and high-responsive photonic tools. In this study, we propose a hybrid graphene islands-mediated THz metadevice to support tunable charge transfer plasmon (CTP) resonances. We show that bias variations in the gated graphene significantly change the metadevice transmittance at the CTP frequency, while the capacitive dipolar mode remains unchanged. Our numerical and experimental studies show that tuning the conductivity of graphene islands between a cluster of metallic blocks provides an active and exotic control over the charge transition across the assembly. To experimentally prove the viability of our concept in a practical photonic application, we utilized the presented tunable system as a high modulation-depth THz modulator. This enabled us to facilitate the THz modulation speed of 19 µs and 21 µs for rising and falling durations, respectively, with the modulation depth of 72%.

Research paper thumbnail of A novel symmetrical 4H–SiC MESFET: an effective way to improve the breakdown voltage

Journal of Computational Electronics, 2015

Research paper thumbnail of A novel high frequency SOI MESFET by modified gate capacitances

Superlattices and Microstructures, 2013

ABSTRACT A novel SOI MESFET with high frequency performance over conventional structures is prese... more ABSTRACT A novel SOI MESFET with high frequency performance over conventional structures is presented. The key idea in this work is to control gate capacitances by modifying channel charges. The proposed structure consists of an additional oxide layer in the channel under gate to control the channel charges. We investigate the improvement in device performance with two-dimensional and two-carrier device simulation. The proposed structure improves the gate-source and gate-drain capacitances and the minimum noise figure in comparison with a conventional SOI MESFET (C-SOI). Moreover, it has been decreased the carriers concentrations especially holes around drain. Hence it causes the generation rate decreases by 137% near the source side with a minimum value around the oxide and therefore the break down voltage will increase. The results demonstrate that the proposed structure has better frequency characteristics in comparison with the C-SOI structure.

Research paper thumbnail of A novel high frequency SOI MESFET by modified gate capacitances Article

Superlattices and Microstructures, 2013

A novel SOI MESFET with high frequency performance over conventional structures is presented. The... more A novel SOI MESFET with high frequency performance over conventional structures is presented. The key idea in this work is to control gate capacitances by modifying channel charges. The proposed structure consists of an additional oxide layer in the channel under gate to control the channel charges. We investigate the improvement in device performance with two-dimensional and two-carrier device simulation. The proposed structure improves the gate-source and gate-drain capacitances and the minimum noise figure in comparison with a conventional SOI MESFET (C-SOI). Moreover, it has been decreased the carriers concentrations especially holes around drain. Hence it causes the generation rate decreases by 137% near the source side with a minimum value around the oxide and therefore the break down voltage will increase. The results demonstrate that the proposed structure has better frequency characteristics in comparison with the C-SOI structure.

Research paper thumbnail of A silicon-on-insulator metal–semiconductor field-effect transistor with an L-shaped buried oxide for high output-power density

Materials Science in Semiconductor Processing, 2014

We describe a novel silicon-on-insulator metal–semiconductor field-effect transistor with an L-sh... more We describe a novel silicon-on-insulator metal–semiconductor field-effect transistor with an L-shaped buried oxide (LB-SOI MESFET) and its maximum output power density (Pmax). To optimize the surface electric field and improve the breakdown voltage, we eliminated part of the oxide and replaced it with n-type silicon. By creating an n+–n region on the source side and modifying the electric field distribution, the breakdown voltage improved by 42% compared to a conventional device. Channel control is realized by varying the depletion layer width underneath the metal gate contact. This modulates the thickness of the conducting channel and thus controls the current between the source and the drain. Continuation of the n-type silicon on top of the buried oxide after the gate metal changes the depletion layer and increases the total channel charge for conduction, so the drain current increases by a factor of five compared to a conventional SOI MESFET. In addition, Pmax is increased by a factor of 17.7 with respect to a conventional structure, which is important for large-signal analog applications. Consequently, our novel LB-SOI MESFET has superior electrical characteristics.

Research paper thumbnail of A novel double-recessed 4H-SiC MESFET using scattering the electric field for high power and RF applications

Physica E Low-dimensional Systems and Nanostructures, 2014

In this paper, we present the unique features exhibited by a novel double-recessed 4H-SIC Metal-S... more In this paper, we present the unique features exhibited by a novel double-recessed 4H-SIC Metal-Semiconductor Field Effect Transistor (MESFET) in which the channel consists of a floating metal region (FMR-MESFET). The key idea in this work is to scatter the electric field lines and modify the ionization mechanism. The floating metal region allows more electrons participate in carrying current, so the optimized results show that the breakdown voltage (V-BR) and the drain saturation current (I-Dsat) increase about 54% and 22% compared with a conventional double recessed MESFET (CDR-MESFET), respectively. Therefore the maximum output power density (P-max) improved by factor 3.38 in comparisons with conventional one. Also, the cut-off frequency (f(T)) of 15 GHz and the maximum oscillation frequency (f(Max)) of 135 GHz for 4H-SiC FMR-MESFET is obtained compared to 13 GHz and 120 GHz for that of the CDR-MESFET and the minimum figure noise (F-min) decreased as a result of reducing gate-drain and gate-source capacitances by about 42% and 40%, respectively. Therefore, the FMR-MESFET has superior RF frequency and high electrical performances.

Research paper thumbnail of Improving Self-Heating Effect and Maximum Power Density in SOI MESFETs by Using the Hole’s Well Under Channel

IEEE Transactions on Electron Devices , 2014

In this brief, we present a new silicon-on-insulator MESFET by using an SiGe region as a well for... more In this brief, we present a new silicon-on-insulator MESFET by using an SiGe region as a well for absorbing the holes which are generated in result of the impact ionization mechanism. The key idea in this brief is to improve the breakdown voltage and self-heating effect (SHE) by utilizing an SiGe region to decreasing the crowding of holes around the source. The well is located in the buried oxide under the channel region. Simulation results show two extra peaks created on the electric field distribution that improves the breakdown voltage. Also, the floating body effect improves due to absorbing the holes by the hole’s well and the lattice temperature decreases, so the SHE improves, too.

Research paper thumbnail of A novel high-performance SOI MESFET by stopping the depletion region extension

Superlattices and Microstructures , 2014

A novel power SOI-MESFET is proposed which consists of an insulator region in the channel for hig... more A novel power SOI-MESFET is proposed which consists of an insulator region in the channel for high-power applications. The key idea in this work is to stop the depletion region extension toward the drain and source regions and eliminate the gate adjacent spaces. We called the proposed structure as stopped depletion region extension SOI (SDR-SOI) MESFET. The breakdown voltage (VBR) and small-signal characteristics of the proposed structure improve due to the high critical electric field of the insulator region and less extended depletion region. The optimized results show that the VBR of the SDR-SOI MESFET is 45% larger than that obtained for the conventional SOI MESFET (C-MESFET). Furthermore the maximum output power density of the SDR-SOI MESFET is 0.33 W/mm compared with 0.24 W/mm of the C-MESFET. Meanwhile the elimination of the gate depletion layer extension to source/drain leads to decrease gate–drain capacitance (CGD). So, the proposed structure presents the potential for high-power applications.

Research paper thumbnail of High-performance SOI MESFET with modified depletion region using a triple recessed gate for RF applications

Materials Science in Semiconductor Processing, 2015

A novel SOI MESFET with the modified depletion region using a Triple Recessed Gate (TRG-SOI MESFE... more A novel SOI MESFET with the modified depletion region using a Triple Recessed Gate (TRG-SOI MESFET) is presented for RF applications. The proposed gate consists of lower and upper gate to control the channel thickness and the depletion layer will change by omitting part of total charge due to locating gate in the channel. The key idea of this shaped gate is to modify the depletion region and the charge distribution of the channel in order to lower the electric field of the device and improving the breakdown voltage. In addition the maximum power density, the maximum oscillation frequency, the cutoff frequency, and the minimum noise figure for the proposed structure are improved due to increasing the drain-source resistance and the transconductance and decreasing the gate resistance. Therefore, the TRG-SOI MESFET can be used for high-power and high frequency applications.

Research paper thumbnail of A novel SOI-MESFET structure with double protruded region for RF and high voltage applications

Materials Science in Semiconductor Processing, 2015

This study sets out to analyze a novel SOI MESFET structure by modifying the shape of the buried ... more This study sets out to analyze a novel SOI MESFET structure by modifying the shape of the buried oxide. In order to obtain improved electrical performances in SOI-MESFET devices, we have proposed a new structure in which a double protruded region with a groove (DPG) in the buried oxide is created. This strategy reduces the carrier׳s concentration in the channel and improves the breakdown voltage. The proposed structure is analyzed and optimized carefully by 2-D numerical simulation and compared with a conventional SOI MESFET (C-SOI MESFET). It shows one extra peak created in the electric field distribution near the drain side which improves the breakdown voltage and the maximum output power density (Pmax) 46% and 33% in comparison with the C-SOI MESFET, respectively. Also, the gate-source and the gate-drain capacitances decrease due to reduction of the carrier concentration in the channel. Therefore, the RF characteristics of proposed structure such as Maximum Available Gain (MAG), (current gain), and Unilateral power gain (U) improve about 13%, 24%, and 12%, respectively in comparison with the C-SOI MESFET.

Research paper thumbnail of A novel high-performance SOI MESFET by stopping the depletion region extension

Superlattices and Microstructures, 2014

ABSTRACT A novel power SOI-MESFET is proposed which consists of an insulator region in the channe... more ABSTRACT A novel power SOI-MESFET is proposed which consists of an insulator region in the channel for high-power applications. The key idea in this work is to stop the depletion region extension toward the drain and source regions and eliminate the gate adjacent spaces. We called the proposed structure as stopped depletion region extension SOI (SDR-SOI) MESFET. The breakdown voltage (VBR) and small-signal characteristics of the proposed structure improve due to the high critical electric field of the insulator region and less extended depletion region. The optimized results show that the VBR of the SDR-SOI MESFET is 45% larger than that obtained for the conventional SOI MESFET (C-MESFET). Furthermore the maximum output power density of the SDR-SOI MESFET is 0.33 W/mm compared with 0.24 W/mm of the C-MESFET. Meanwhile the elimination of the gate depletion layer extension to source/drain leads to decrease gate–drain capacitance (CGD). So, the proposed structure presents the potential for high-power applications.

Research paper thumbnail of High-performance SOI MESFET with modified depletion region using a triple recessed gate for RF applications

Materials Science in Semiconductor Processing, 2015

ABSTRACT A novel SOI MESFET with the modified depletion region using a Triple Recessed Gate (TRG-... more ABSTRACT A novel SOI MESFET with the modified depletion region using a Triple Recessed Gate (TRG-SOI MESFET) is presented for RF applications. The proposed gate consists of lower and upper gate to control the channel thickness and the depletion layer will change by omitting part of total charge due to locating gate in the channel. The key idea of this shaped gate is to modify the depletion region and the charge distribution of the channel in order to lower the electric field of the device and improving the breakdown voltage. In addition the maximum power density, the maximum oscillation frequency, the cutoff frequency, and the minimum noise figure for the proposed structure are improved due to increasing the drain-source resistance and the transconductance and decreasing the gate resistance. Therefore, the TRG-SOI MESFET can be used for high-power and high frequency applications.

Research paper thumbnail of A novel double-recessed 4H-SiC MESFET using scattering the electric field for high power and RF applications

Physica E: Low-dimensional Systems and Nanostructures, 2014

ABSTRACT In this paper, we present the unique features exhibited by a novel double-recessed 4H-SI... more ABSTRACT In this paper, we present the unique features exhibited by a novel double-recessed 4H-SIC Metal-Semiconductor Field Effect Transistor (MESFET) in which the channel consists of a floating metal region (FMR-MESFET). The key idea in this work is to scatter the electric field lines and modify the ionization mechanism. The floating metal region allows more electrons participate in carrying current, so the optimized results show that the breakdown voltage (V-BR) and the drain saturation current (I-Dsat) increase about 54% and 22% compared with a conventional double recessed MESFET (CDR-MESFET), respectively. Therefore the maximum output power density (P-max) improved by factor 3.38 in comparisons with conventional one. Also, the cut-off frequency (f(T)) of 15 GHz and the maximum oscillation frequency (f(Max)) of 135 GHz for 4H-SiC FMR-MESFET is obtained compared to 13 GHz and 120 GHz for that of the CDR-MESFET and the minimum figure noise (F-min) decreased as a result of reducing gate-drain and gate-source capacitances by about 42% and 40%, respectively. Therefore, the FMR-MESFET has superior RF frequency and high electrical performances.

Research paper thumbnail of A novel SOI-MESFET structure with double protruded region for RF and high voltage applications

Materials Science in Semiconductor Processing, 2015

ABSTRACT This study sets out to analyze a novel SOI MESFET structure by modifying the shape of th... more ABSTRACT This study sets out to analyze a novel SOI MESFET structure by modifying the shape of the buried oxide. In order to obtain improved electrical performances in SOI-MESFET devices, we have proposed a new structure in which a double protruded region with a groove (DPG) in the buried oxide is created. This strategy reduces the carrier׳s concentration in the channel and improves the breakdown voltage. The proposed structure is analyzed and optimized carefully by 2-D numerical simulation and compared with a conventional SOI MESFET (C-SOI MESFET). It shows one extra peak created in the electric field distribution near the drain side which improves the breakdown voltage and the maximum output power density (Pmax) 46% and 33% in comparison with the C-SOI MESFET, respectively. Also, the gate-source and the gate-drain capacitances decrease due to reduction of the carrier concentration in the channel. Therefore, the RF characteristics of proposed structure such as Maximum Available Gain (MAG), (current gain), and Unilateral power gain (U) improve about 13%, 24%, and 12%, respectively in comparison with the C-SOI MESFET.

Research paper thumbnail of Improving Self-Heating Effect and Maximum Power Density in SOI MESFETs by Using the Hole’s Well Under Channel

IEEE Transactions on Electron Devices, 2014

ABSTRACT In this brief, we present a new silicon-on-insulator MESFET by using an SiGe region as a... more ABSTRACT In this brief, we present a new silicon-on-insulator MESFET by using an SiGe region as a well for absorbing the holes which are generated in result of the impact ionization mechanism. The key idea in this brief is to improve the breakdown voltage and self-heating effect (SHE) by utilizing an SiGe region to decreasing the crowding of holes around the source. The well is located in the buried oxide under the channel region. Simulation results show two extra peaks created on the electric field distribution that improves the breakdown voltage. Also, the floating body effect improves due to absorbing the holes by the hole’s well and the lattice temperature decreases, so the SHE improves, too.

Research paper thumbnail of A silicon-on-insulator metal–semiconductor field-effect transistor with an L-shaped buried oxide for high output-power density

Materials Science in Semiconductor Processing, 2014

ABSTRACT We describe a novel silicon-on-insulator metal–semiconductor field-effect transistor wit... more ABSTRACT We describe a novel silicon-on-insulator metal–semiconductor field-effect transistor with an L-shaped buried oxide (LB-SOI MESFET) and its maximum output power density (Pmax). To optimize the surface electric field and improve the breakdown voltage, we eliminated part of the oxide and replaced it with n-type silicon. By creating an n+–n region on the source side and modifying the electric field distribution, the breakdown voltage improved by 42% compared to a conventional device. Channel control is realized by varying the depletion layer width underneath the metal gate contact. This modulates the thickness of the conducting channel and thus controls the current between the source and the drain. Continuation of the n-type silicon on top of the buried oxide after the gate metal changes the depletion layer and increases the total channel charge for conduction, so the drain current increases by a factor of five compared to a conventional SOI MESFET. In addition, Pmax is increased by a factor of 17.7 with respect to a conventional structure, which is important for large-signal analog applications. Consequently, our novel LB-SOI MESFET has superior electrical characteristics.

Research paper thumbnail of A novel symmetric GaN MESFET by dual extra layers of Si3N4

Physica E: Low-dimensional Systems and Nanostructures, 2015

ABSTRACT In this paper, a novel GaN MESFET structure with Double Extra Layers of Si3N4 (DEL-MESFE... more ABSTRACT In this paper, a novel GaN MESFET structure with Double Extra Layers of Si3N4 (DEL-MESFET) under gate edges has been introduced in order to modify the carrier concentration and the electric field in the channel. The results show that the breakdown voltage (VBR) increases to 200 V in the proposed structure from 119.2 V in a conventional MESFET structure (C-MESFET). Furthermore, the maximum output power density (Pmax) of the proposed structure is 74% higher than that of the conventional one. By modifying the carrier's concentration, the gate-source and gate-drain capacitances decrease that lead to the improvement of the RF characteristics including ft and fmax from 27.5 and 99 GHz of the C-SOI MESFET to 30 and 105 GHz of the DEL-MESFET, respectively. Therefore, the results show that the proposed structure provides the excellent performance compared with the C-MESFET structure and can be taken into consideration for the future of the VLSI applications.

Research paper thumbnail of A novel high frequency SOI MESFET by modified gate capacitances

Superlattices and Microstructures, 2013

ABSTRACT A novel SOI MESFET with high frequency performance over conventional structures is prese... more ABSTRACT A novel SOI MESFET with high frequency performance over conventional structures is presented. The key idea in this work is to control gate capacitances by modifying channel charges. The proposed structure consists of an additional oxide layer in the channel under gate to control the channel charges. We investigate the improvement in device performance with two-dimensional and two-carrier device simulation. The proposed structure improves the gate-source and gate-drain capacitances and the minimum noise figure in comparison with a conventional SOI MESFET (C-SOI). Moreover, it has been decreased the carriers concentrations especially holes around drain. Hence it causes the generation rate decreases by 137% near the source side with a minimum value around the oxide and therefore the break down voltage will increase. The results demonstrate that the proposed structure has better frequency characteristics in comparison with the C-SOI structure.

Research paper thumbnail of A novel double-recessed 4H-SiC MESFET using scattering the electric field for high power and RF applications

Physica E: Low-dimensional Systems and Nanostructures, 2014

ABSTRACT In this paper, we present the unique features exhibited by a novel double-recessed 4H-SI... more ABSTRACT In this paper, we present the unique features exhibited by a novel double-recessed 4H-SIC Metal-Semiconductor Field Effect Transistor (MESFET) in which the channel consists of a floating metal region (FMR-MESFET). The key idea in this work is to scatter the electric field lines and modify the ionization mechanism. The floating metal region allows more electrons participate in carrying current, so the optimized results show that the breakdown voltage (V-BR) and the drain saturation current (I-Dsat) increase about 54% and 22% compared with a conventional double recessed MESFET (CDR-MESFET), respectively. Therefore the maximum output power density (P-max) improved by factor 3.38 in comparisons with conventional one. Also, the cut-off frequency (f(T)) of 15 GHz and the maximum oscillation frequency (f(Max)) of 135 GHz for 4H-SiC FMR-MESFET is obtained compared to 13 GHz and 120 GHz for that of the CDR-MESFET and the minimum figure noise (F-min) decreased as a result of reducing gate-drain and gate-source capacitances by about 42% and 40%, respectively. Therefore, the FMR-MESFET has superior RF frequency and high electrical performances.

Research paper thumbnail of Amended Electric Field Distribution: A Reliable Technique for Electrical Performance Improvement in Nano scale SOI MOSFETs

Journal of Electronic Materials, 2017

To achieve reliable transistors, we propose a new silicon-on-insulator (SOI) metal-oxide-semicond... more To achieve reliable transistors, we propose a new silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) with an amended electric field in the channel for improved electrical and thermal performance, with an emphasis on current leakage improvement. The amended electric field leads to lower electric field crowding and thereby we assume enhanced reliability, leakage current, gate-induced drain leakage (GIDL), and electron temperature. To modify the electric field distribution, an additional rectangular metal region (RMR) is utilized in the buried oxide of the SOI MOSFET. The location and dimensions of the RMR have been carefully optimized to achieve the best results. The electrical, thermal, and radiofrequency characteristics of the proposed structure were analyzed using two-dimensional (2-D) numerical simulations and compared with the characteristics of the conventional, fully depleted SOI MOSFET (C-SOI). Also, critical short-channel effects (SCEs) such as threshold voltage, drain-induced barrier lowering (DIBL), subthreshold slope degradation, hot-carrier effect, GIDL, and leakage power consumption are improved. According to the results obtained, the proposed nano SOI MOSFET is a reliable device, especially for use in low-power and high-temperature applications.

Research paper thumbnail of Gated graphene islands enabled tunable charge transfer plasmon terahertz metamodulator

Nanoscale, 2019

Graphene-enhanced optoelectronic terahertz (THz) signal processing offers an exquisite potential ... more Graphene-enhanced optoelectronic terahertz (THz) signal processing offers an exquisite potential for tailoring extreme-subwavelength platforms to develop tunable and high-responsive photonic tools. In this study, we propose a hybrid graphene islands-mediated THz metadevice to support tunable charge transfer plasmon (CTP) resonances. We show that bias variations in the gated graphene significantly change the metadevice transmittance at the CTP frequency, while the capacitive dipolar mode remains unchanged. Our numerical and experimental studies show that tuning the conductivity of graphene islands between a cluster of metallic blocks provides an active and exotic control over the charge transition across the assembly. To experimentally prove the viability of our concept in a practical photonic application, we utilized the presented tunable system as a high modulation-depth THz modulator. This enabled us to facilitate the THz modulation speed of 19 µs and 21 µs for rising and falling durations, respectively, with the modulation depth of 72%.

Research paper thumbnail of A novel symmetrical 4H–SiC MESFET: an effective way to improve the breakdown voltage

Journal of Computational Electronics, 2015

Research paper thumbnail of A novel high frequency SOI MESFET by modified gate capacitances

Superlattices and Microstructures, 2013

ABSTRACT A novel SOI MESFET with high frequency performance over conventional structures is prese... more ABSTRACT A novel SOI MESFET with high frequency performance over conventional structures is presented. The key idea in this work is to control gate capacitances by modifying channel charges. The proposed structure consists of an additional oxide layer in the channel under gate to control the channel charges. We investigate the improvement in device performance with two-dimensional and two-carrier device simulation. The proposed structure improves the gate-source and gate-drain capacitances and the minimum noise figure in comparison with a conventional SOI MESFET (C-SOI). Moreover, it has been decreased the carriers concentrations especially holes around drain. Hence it causes the generation rate decreases by 137% near the source side with a minimum value around the oxide and therefore the break down voltage will increase. The results demonstrate that the proposed structure has better frequency characteristics in comparison with the C-SOI structure.

Research paper thumbnail of A novel high frequency SOI MESFET by modified gate capacitances Article

Superlattices and Microstructures, 2013

A novel SOI MESFET with high frequency performance over conventional structures is presented. The... more A novel SOI MESFET with high frequency performance over conventional structures is presented. The key idea in this work is to control gate capacitances by modifying channel charges. The proposed structure consists of an additional oxide layer in the channel under gate to control the channel charges. We investigate the improvement in device performance with two-dimensional and two-carrier device simulation. The proposed structure improves the gate-source and gate-drain capacitances and the minimum noise figure in comparison with a conventional SOI MESFET (C-SOI). Moreover, it has been decreased the carriers concentrations especially holes around drain. Hence it causes the generation rate decreases by 137% near the source side with a minimum value around the oxide and therefore the break down voltage will increase. The results demonstrate that the proposed structure has better frequency characteristics in comparison with the C-SOI structure.

Research paper thumbnail of A silicon-on-insulator metal–semiconductor field-effect transistor with an L-shaped buried oxide for high output-power density

Materials Science in Semiconductor Processing, 2014

We describe a novel silicon-on-insulator metal–semiconductor field-effect transistor with an L-sh... more We describe a novel silicon-on-insulator metal–semiconductor field-effect transistor with an L-shaped buried oxide (LB-SOI MESFET) and its maximum output power density (Pmax). To optimize the surface electric field and improve the breakdown voltage, we eliminated part of the oxide and replaced it with n-type silicon. By creating an n+–n region on the source side and modifying the electric field distribution, the breakdown voltage improved by 42% compared to a conventional device. Channel control is realized by varying the depletion layer width underneath the metal gate contact. This modulates the thickness of the conducting channel and thus controls the current between the source and the drain. Continuation of the n-type silicon on top of the buried oxide after the gate metal changes the depletion layer and increases the total channel charge for conduction, so the drain current increases by a factor of five compared to a conventional SOI MESFET. In addition, Pmax is increased by a factor of 17.7 with respect to a conventional structure, which is important for large-signal analog applications. Consequently, our novel LB-SOI MESFET has superior electrical characteristics.

Research paper thumbnail of A novel double-recessed 4H-SiC MESFET using scattering the electric field for high power and RF applications

Physica E Low-dimensional Systems and Nanostructures, 2014

In this paper, we present the unique features exhibited by a novel double-recessed 4H-SIC Metal-S... more In this paper, we present the unique features exhibited by a novel double-recessed 4H-SIC Metal-Semiconductor Field Effect Transistor (MESFET) in which the channel consists of a floating metal region (FMR-MESFET). The key idea in this work is to scatter the electric field lines and modify the ionization mechanism. The floating metal region allows more electrons participate in carrying current, so the optimized results show that the breakdown voltage (V-BR) and the drain saturation current (I-Dsat) increase about 54% and 22% compared with a conventional double recessed MESFET (CDR-MESFET), respectively. Therefore the maximum output power density (P-max) improved by factor 3.38 in comparisons with conventional one. Also, the cut-off frequency (f(T)) of 15 GHz and the maximum oscillation frequency (f(Max)) of 135 GHz for 4H-SiC FMR-MESFET is obtained compared to 13 GHz and 120 GHz for that of the CDR-MESFET and the minimum figure noise (F-min) decreased as a result of reducing gate-drain and gate-source capacitances by about 42% and 40%, respectively. Therefore, the FMR-MESFET has superior RF frequency and high electrical performances.

Research paper thumbnail of Improving Self-Heating Effect and Maximum Power Density in SOI MESFETs by Using the Hole’s Well Under Channel

IEEE Transactions on Electron Devices , 2014

In this brief, we present a new silicon-on-insulator MESFET by using an SiGe region as a well for... more In this brief, we present a new silicon-on-insulator MESFET by using an SiGe region as a well for absorbing the holes which are generated in result of the impact ionization mechanism. The key idea in this brief is to improve the breakdown voltage and self-heating effect (SHE) by utilizing an SiGe region to decreasing the crowding of holes around the source. The well is located in the buried oxide under the channel region. Simulation results show two extra peaks created on the electric field distribution that improves the breakdown voltage. Also, the floating body effect improves due to absorbing the holes by the hole’s well and the lattice temperature decreases, so the SHE improves, too.

Research paper thumbnail of A novel high-performance SOI MESFET by stopping the depletion region extension

Superlattices and Microstructures , 2014

A novel power SOI-MESFET is proposed which consists of an insulator region in the channel for hig... more A novel power SOI-MESFET is proposed which consists of an insulator region in the channel for high-power applications. The key idea in this work is to stop the depletion region extension toward the drain and source regions and eliminate the gate adjacent spaces. We called the proposed structure as stopped depletion region extension SOI (SDR-SOI) MESFET. The breakdown voltage (VBR) and small-signal characteristics of the proposed structure improve due to the high critical electric field of the insulator region and less extended depletion region. The optimized results show that the VBR of the SDR-SOI MESFET is 45% larger than that obtained for the conventional SOI MESFET (C-MESFET). Furthermore the maximum output power density of the SDR-SOI MESFET is 0.33 W/mm compared with 0.24 W/mm of the C-MESFET. Meanwhile the elimination of the gate depletion layer extension to source/drain leads to decrease gate–drain capacitance (CGD). So, the proposed structure presents the potential for high-power applications.

Research paper thumbnail of High-performance SOI MESFET with modified depletion region using a triple recessed gate for RF applications

Materials Science in Semiconductor Processing, 2015

A novel SOI MESFET with the modified depletion region using a Triple Recessed Gate (TRG-SOI MESFE... more A novel SOI MESFET with the modified depletion region using a Triple Recessed Gate (TRG-SOI MESFET) is presented for RF applications. The proposed gate consists of lower and upper gate to control the channel thickness and the depletion layer will change by omitting part of total charge due to locating gate in the channel. The key idea of this shaped gate is to modify the depletion region and the charge distribution of the channel in order to lower the electric field of the device and improving the breakdown voltage. In addition the maximum power density, the maximum oscillation frequency, the cutoff frequency, and the minimum noise figure for the proposed structure are improved due to increasing the drain-source resistance and the transconductance and decreasing the gate resistance. Therefore, the TRG-SOI MESFET can be used for high-power and high frequency applications.

Research paper thumbnail of A novel SOI-MESFET structure with double protruded region for RF and high voltage applications

Materials Science in Semiconductor Processing, 2015

This study sets out to analyze a novel SOI MESFET structure by modifying the shape of the buried ... more This study sets out to analyze a novel SOI MESFET structure by modifying the shape of the buried oxide. In order to obtain improved electrical performances in SOI-MESFET devices, we have proposed a new structure in which a double protruded region with a groove (DPG) in the buried oxide is created. This strategy reduces the carrier׳s concentration in the channel and improves the breakdown voltage. The proposed structure is analyzed and optimized carefully by 2-D numerical simulation and compared with a conventional SOI MESFET (C-SOI MESFET). It shows one extra peak created in the electric field distribution near the drain side which improves the breakdown voltage and the maximum output power density (Pmax) 46% and 33% in comparison with the C-SOI MESFET, respectively. Also, the gate-source and the gate-drain capacitances decrease due to reduction of the carrier concentration in the channel. Therefore, the RF characteristics of proposed structure such as Maximum Available Gain (MAG), (current gain), and Unilateral power gain (U) improve about 13%, 24%, and 12%, respectively in comparison with the C-SOI MESFET.

Research paper thumbnail of A novel high-performance SOI MESFET by stopping the depletion region extension

Superlattices and Microstructures, 2014

ABSTRACT A novel power SOI-MESFET is proposed which consists of an insulator region in the channe... more ABSTRACT A novel power SOI-MESFET is proposed which consists of an insulator region in the channel for high-power applications. The key idea in this work is to stop the depletion region extension toward the drain and source regions and eliminate the gate adjacent spaces. We called the proposed structure as stopped depletion region extension SOI (SDR-SOI) MESFET. The breakdown voltage (VBR) and small-signal characteristics of the proposed structure improve due to the high critical electric field of the insulator region and less extended depletion region. The optimized results show that the VBR of the SDR-SOI MESFET is 45% larger than that obtained for the conventional SOI MESFET (C-MESFET). Furthermore the maximum output power density of the SDR-SOI MESFET is 0.33 W/mm compared with 0.24 W/mm of the C-MESFET. Meanwhile the elimination of the gate depletion layer extension to source/drain leads to decrease gate–drain capacitance (CGD). So, the proposed structure presents the potential for high-power applications.

Research paper thumbnail of High-performance SOI MESFET with modified depletion region using a triple recessed gate for RF applications

Materials Science in Semiconductor Processing, 2015

ABSTRACT A novel SOI MESFET with the modified depletion region using a Triple Recessed Gate (TRG-... more ABSTRACT A novel SOI MESFET with the modified depletion region using a Triple Recessed Gate (TRG-SOI MESFET) is presented for RF applications. The proposed gate consists of lower and upper gate to control the channel thickness and the depletion layer will change by omitting part of total charge due to locating gate in the channel. The key idea of this shaped gate is to modify the depletion region and the charge distribution of the channel in order to lower the electric field of the device and improving the breakdown voltage. In addition the maximum power density, the maximum oscillation frequency, the cutoff frequency, and the minimum noise figure for the proposed structure are improved due to increasing the drain-source resistance and the transconductance and decreasing the gate resistance. Therefore, the TRG-SOI MESFET can be used for high-power and high frequency applications.

Research paper thumbnail of A novel double-recessed 4H-SiC MESFET using scattering the electric field for high power and RF applications

Physica E: Low-dimensional Systems and Nanostructures, 2014

ABSTRACT In this paper, we present the unique features exhibited by a novel double-recessed 4H-SI... more ABSTRACT In this paper, we present the unique features exhibited by a novel double-recessed 4H-SIC Metal-Semiconductor Field Effect Transistor (MESFET) in which the channel consists of a floating metal region (FMR-MESFET). The key idea in this work is to scatter the electric field lines and modify the ionization mechanism. The floating metal region allows more electrons participate in carrying current, so the optimized results show that the breakdown voltage (V-BR) and the drain saturation current (I-Dsat) increase about 54% and 22% compared with a conventional double recessed MESFET (CDR-MESFET), respectively. Therefore the maximum output power density (P-max) improved by factor 3.38 in comparisons with conventional one. Also, the cut-off frequency (f(T)) of 15 GHz and the maximum oscillation frequency (f(Max)) of 135 GHz for 4H-SiC FMR-MESFET is obtained compared to 13 GHz and 120 GHz for that of the CDR-MESFET and the minimum figure noise (F-min) decreased as a result of reducing gate-drain and gate-source capacitances by about 42% and 40%, respectively. Therefore, the FMR-MESFET has superior RF frequency and high electrical performances.

Research paper thumbnail of A novel SOI-MESFET structure with double protruded region for RF and high voltage applications

Materials Science in Semiconductor Processing, 2015

ABSTRACT This study sets out to analyze a novel SOI MESFET structure by modifying the shape of th... more ABSTRACT This study sets out to analyze a novel SOI MESFET structure by modifying the shape of the buried oxide. In order to obtain improved electrical performances in SOI-MESFET devices, we have proposed a new structure in which a double protruded region with a groove (DPG) in the buried oxide is created. This strategy reduces the carrier׳s concentration in the channel and improves the breakdown voltage. The proposed structure is analyzed and optimized carefully by 2-D numerical simulation and compared with a conventional SOI MESFET (C-SOI MESFET). It shows one extra peak created in the electric field distribution near the drain side which improves the breakdown voltage and the maximum output power density (Pmax) 46% and 33% in comparison with the C-SOI MESFET, respectively. Also, the gate-source and the gate-drain capacitances decrease due to reduction of the carrier concentration in the channel. Therefore, the RF characteristics of proposed structure such as Maximum Available Gain (MAG), (current gain), and Unilateral power gain (U) improve about 13%, 24%, and 12%, respectively in comparison with the C-SOI MESFET.

Research paper thumbnail of Improving Self-Heating Effect and Maximum Power Density in SOI MESFETs by Using the Hole’s Well Under Channel

IEEE Transactions on Electron Devices, 2014

ABSTRACT In this brief, we present a new silicon-on-insulator MESFET by using an SiGe region as a... more ABSTRACT In this brief, we present a new silicon-on-insulator MESFET by using an SiGe region as a well for absorbing the holes which are generated in result of the impact ionization mechanism. The key idea in this brief is to improve the breakdown voltage and self-heating effect (SHE) by utilizing an SiGe region to decreasing the crowding of holes around the source. The well is located in the buried oxide under the channel region. Simulation results show two extra peaks created on the electric field distribution that improves the breakdown voltage. Also, the floating body effect improves due to absorbing the holes by the hole’s well and the lattice temperature decreases, so the SHE improves, too.

Research paper thumbnail of A silicon-on-insulator metal–semiconductor field-effect transistor with an L-shaped buried oxide for high output-power density

Materials Science in Semiconductor Processing, 2014

ABSTRACT We describe a novel silicon-on-insulator metal–semiconductor field-effect transistor wit... more ABSTRACT We describe a novel silicon-on-insulator metal–semiconductor field-effect transistor with an L-shaped buried oxide (LB-SOI MESFET) and its maximum output power density (Pmax). To optimize the surface electric field and improve the breakdown voltage, we eliminated part of the oxide and replaced it with n-type silicon. By creating an n+–n region on the source side and modifying the electric field distribution, the breakdown voltage improved by 42% compared to a conventional device. Channel control is realized by varying the depletion layer width underneath the metal gate contact. This modulates the thickness of the conducting channel and thus controls the current between the source and the drain. Continuation of the n-type silicon on top of the buried oxide after the gate metal changes the depletion layer and increases the total channel charge for conduction, so the drain current increases by a factor of five compared to a conventional SOI MESFET. In addition, Pmax is increased by a factor of 17.7 with respect to a conventional structure, which is important for large-signal analog applications. Consequently, our novel LB-SOI MESFET has superior electrical characteristics.

Research paper thumbnail of A novel symmetric GaN MESFET by dual extra layers of Si3N4

Physica E: Low-dimensional Systems and Nanostructures, 2015

ABSTRACT In this paper, a novel GaN MESFET structure with Double Extra Layers of Si3N4 (DEL-MESFE... more ABSTRACT In this paper, a novel GaN MESFET structure with Double Extra Layers of Si3N4 (DEL-MESFET) under gate edges has been introduced in order to modify the carrier concentration and the electric field in the channel. The results show that the breakdown voltage (VBR) increases to 200 V in the proposed structure from 119.2 V in a conventional MESFET structure (C-MESFET). Furthermore, the maximum output power density (Pmax) of the proposed structure is 74% higher than that of the conventional one. By modifying the carrier's concentration, the gate-source and gate-drain capacitances decrease that lead to the improvement of the RF characteristics including ft and fmax from 27.5 and 99 GHz of the C-SOI MESFET to 30 and 105 GHz of the DEL-MESFET, respectively. Therefore, the results show that the proposed structure provides the excellent performance compared with the C-MESFET structure and can be taken into consideration for the future of the VLSI applications.

Research paper thumbnail of A novel high frequency SOI MESFET by modified gate capacitances

Superlattices and Microstructures, 2013

ABSTRACT A novel SOI MESFET with high frequency performance over conventional structures is prese... more ABSTRACT A novel SOI MESFET with high frequency performance over conventional structures is presented. The key idea in this work is to control gate capacitances by modifying channel charges. The proposed structure consists of an additional oxide layer in the channel under gate to control the channel charges. We investigate the improvement in device performance with two-dimensional and two-carrier device simulation. The proposed structure improves the gate-source and gate-drain capacitances and the minimum noise figure in comparison with a conventional SOI MESFET (C-SOI). Moreover, it has been decreased the carriers concentrations especially holes around drain. Hence it causes the generation rate decreases by 137% near the source side with a minimum value around the oxide and therefore the break down voltage will increase. The results demonstrate that the proposed structure has better frequency characteristics in comparison with the C-SOI structure.

Research paper thumbnail of A novel double-recessed 4H-SiC MESFET using scattering the electric field for high power and RF applications

Physica E: Low-dimensional Systems and Nanostructures, 2014

ABSTRACT In this paper, we present the unique features exhibited by a novel double-recessed 4H-SI... more ABSTRACT In this paper, we present the unique features exhibited by a novel double-recessed 4H-SIC Metal-Semiconductor Field Effect Transistor (MESFET) in which the channel consists of a floating metal region (FMR-MESFET). The key idea in this work is to scatter the electric field lines and modify the ionization mechanism. The floating metal region allows more electrons participate in carrying current, so the optimized results show that the breakdown voltage (V-BR) and the drain saturation current (I-Dsat) increase about 54% and 22% compared with a conventional double recessed MESFET (CDR-MESFET), respectively. Therefore the maximum output power density (P-max) improved by factor 3.38 in comparisons with conventional one. Also, the cut-off frequency (f(T)) of 15 GHz and the maximum oscillation frequency (f(Max)) of 135 GHz for 4H-SiC FMR-MESFET is obtained compared to 13 GHz and 120 GHz for that of the CDR-MESFET and the minimum figure noise (F-min) decreased as a result of reducing gate-drain and gate-source capacitances by about 42% and 40%, respectively. Therefore, the FMR-MESFET has superior RF frequency and high electrical performances.

Research paper thumbnail of Analyzing the Fundamental of Semiconductor Physics by Implementing in the Virtual Laboratory

Technical and Vocational University, 2019

In this book, after explaining the fundamentals of electronics physics for a better understanding... more In this book, after explaining the fundamentals of electronics physics for a better understanding of the history of Silavecas software, its applications and how to install it, we will discuss the main explanations of how to work with the software. At this point, descriptions and physical processes are combined with it. Finally, three well-known and widely used electronics (diodes, mosfets, and coppers) are described and simulated physically and electronically. In this book, we are trying to provide a complete physical and basic explanation in real life, so that students of bachelor's bachelors who do not have the lesson of electronics physics in their curriculum can easily understand. In fact, this book teaches electronics physics along with an accurate simulation software for understanding e-science.