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Research paper thumbnail of An Implementation of Area Optimized Low Power MAC

JOURNAL OF MECHANICS OF CONTINUA AND MATHEMATICAL SCIENCES

The objective of the paper is to develop an Area optimized Low power digital circuit for MAC (Mul... more The objective of the paper is to develop an Area optimized Low power digital circuit for MAC (Multiply and Accumulate) operation. We developed implementations of the MAC to avoid using multipliers and prefer to use the combinational circuits like multiplexers. We analyze all the MAC digital circuits to find out the best digital circuit which consumes minimum area and power. MAC is basic building block of many Digital Signal Processing Applications like Noise Cancellation Circuits, Speech Processing, Image Processing, Video Processing, Artificial Neural Networks etc. We also give some suggestions on the system level solutions based on the MAC. The digital circuit which is developed by us will be compatible to FPGAs, as it is developed by the industry standard Synthesis tool i.e. Synopsys Synlipy pro synthesis tool. The MAC which we are developing can be placed in the FPGA Fabric and it can be interfaced to any processors like Cortex M3, Cortex M0, 805 1etc. The overall throughput decreases due high latency and increase in the processing time. So, all the MAC operations must be performed in the hardware by the MAC block developed by us as it is low power, low area and fast hardware. MAC, Digital Signal Processing,

Research paper thumbnail of Image Interpolation Using 5/3 Lifting Scheme Approach

In this paper we proposed fast and accurate interpolation and resizing of images using lifting sc... more In this paper we proposed fast and accurate interpolation and resizing of images using lifting scheme approach. 5/3 lifting scheme is an accurate and computationally inexpensive interpolation technique for image resizing. We compared the bilinear interpolation, Haar lifting scheme and 5/3 lifting scheme in this paper. The lifting scheme algorithm is applied for image interpolation to resize the image. In case of reduction in size, the image components are reduced and the reconstruction will be carried out to the original image. The reconstruction results are better by using Mean Squared Error (MSE) and Peak Signal to Noise Ratio (PSNR) with other techniques like bilinear interpolation and Haar lifting schemes. The interpolation and reconstruction is executed in much less time with better MSE and PSNR as compared to Bilinear and Haar lifting schemes.

Research paper thumbnail of An Implementation of Area Optimized Low Power MAC

JOURNAL OF MECHANICS OF CONTINUA AND MATHEMATICAL SCIENCES

The objective of the paper is to develop an Area optimized Low power digital circuit for MAC (Mul... more The objective of the paper is to develop an Area optimized Low power digital circuit for MAC (Multiply and Accumulate) operation. We developed implementations of the MAC to avoid using multipliers and prefer to use the combinational circuits like multiplexers. We analyze all the MAC digital circuits to find out the best digital circuit which consumes minimum area and power. MAC is basic building block of many Digital Signal Processing Applications like Noise Cancellation Circuits, Speech Processing, Image Processing, Video Processing, Artificial Neural Networks etc. We also give some suggestions on the system level solutions based on the MAC. The digital circuit which is developed by us will be compatible to FPGAs, as it is developed by the industry standard Synthesis tool i.e. Synopsys Synlipy pro synthesis tool. The MAC which we are developing can be placed in the FPGA Fabric and it can be interfaced to any processors like Cortex M3, Cortex M0, 805 1etc. The overall throughput decreases due high latency and increase in the processing time. So, all the MAC operations must be performed in the hardware by the MAC block developed by us as it is low power, low area and fast hardware. MAC, Digital Signal Processing,

Research paper thumbnail of Image Interpolation Using 5/3 Lifting Scheme Approach

In this paper we proposed fast and accurate interpolation and resizing of images using lifting sc... more In this paper we proposed fast and accurate interpolation and resizing of images using lifting scheme approach. 5/3 lifting scheme is an accurate and computationally inexpensive interpolation technique for image resizing. We compared the bilinear interpolation, Haar lifting scheme and 5/3 lifting scheme in this paper. The lifting scheme algorithm is applied for image interpolation to resize the image. In case of reduction in size, the image components are reduced and the reconstruction will be carried out to the original image. The reconstruction results are better by using Mean Squared Error (MSE) and Peak Signal to Noise Ratio (PSNR) with other techniques like bilinear interpolation and Haar lifting schemes. The interpolation and reconstruction is executed in much less time with better MSE and PSNR as compared to Bilinear and Haar lifting schemes.

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