Yu-Jiu Wang | National Chiao Tung University (original) (raw)

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Papers by Yu-Jiu Wang

Research paper thumbnail of Millimeter-wave MMIC single-pole-double-throw passive HEMT switches using impedance-transformation networks

IEEE Transactions on Microwave Theory and Techniques, 2003

Research paper thumbnail of A V-Band MMIC SPDT passive HEMT switch using impedance transformation networks

Research paper thumbnail of A 6-to-18 GHz tunable concurrent dual-band receiver front end for scalable phased arrays in 130nm CMOS

This paper presents a study and design of tunable concurrent dual-band receiver. Different system... more This paper presents a study and design of tunable concurrent dual-band receiver. Different system architectures and building blocks have been compared and analyzed. A tunable concurrent dual-band receiver front end has then been fabricated and characterized. It operates across a tri-tave 6-18 GHz bandwidth with a nominal 17-25 dB conversion gain, worst-case -15 dBm IIP3, and worst-case -24.5 dBm ICP 1 dB.

Research paper thumbnail of A compact low-noise weighted distributed amplifier in CMOS

The noise figure (NF) of a front-end low-noise amplifier (LNA) places a lower bound on the sensit... more The noise figure (NF) of a front-end low-noise amplifier (LNA) places a lower bound on the sensitivity of a receiver. In a conventional LNA, there is a tradeoff between the intrinsic input capacitance of the input transistors and the achievable bandwidth (BW) of the amplifier. This makes it necessary to use smaller transistors at higher gate overdrive voltages to simultaneously achieve greater BW and better NF. Unfortunately, biasing the transistor in this fashion yields a power-inefficient design. Furthermore, the need for a smaller capacitance presents a challenge to electrostatic discharge (ESD) protection of the input due to its added capacitance.

Research paper thumbnail of A tunable concurrent 6-to-18GHz phased-array system in CMOS

This paper presents a scalable phased-array receiver system that covers a tritave bandwidth of 6-... more This paper presents a scalable phased-array receiver system that covers a tritave bandwidth of 6-to-18 GHz implemented in a 130 nm CMOS process. The single receiver element with a 10-bit phase shifting resolution achieves a maximum phase error of 2.5deg within a baseband amplitude variation of 1.5 dB for an arbitrary target angle. This dense interpolation provides excellent phase error/offset calibration capability in the array. A 4-element electrical array pattern is measured at 6 GHz, 13.5 GHz and 18 GHz, showing a worst case peak-to-null ratio of 21.5 dB. The EVM and phase noise improvements of the array compared with the single receiver element are also shown.

Research paper thumbnail of A Scalable 6-to-18GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

Research paper thumbnail of A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

IEEE Journal of Solid-state Circuits, 2008

Research paper thumbnail of Millimeter-wave MMIC single-pole-double-throw passive HEMT switches using impedance-transformation networks

IEEE Transactions on Microwave Theory and Techniques, 2003

Research paper thumbnail of A V-Band MMIC SPDT passive HEMT switch using impedance transformation networks

Research paper thumbnail of A 6-to-18 GHz tunable concurrent dual-band receiver front end for scalable phased arrays in 130nm CMOS

This paper presents a study and design of tunable concurrent dual-band receiver. Different system... more This paper presents a study and design of tunable concurrent dual-band receiver. Different system architectures and building blocks have been compared and analyzed. A tunable concurrent dual-band receiver front end has then been fabricated and characterized. It operates across a tri-tave 6-18 GHz bandwidth with a nominal 17-25 dB conversion gain, worst-case -15 dBm IIP3, and worst-case -24.5 dBm ICP 1 dB.

Research paper thumbnail of A compact low-noise weighted distributed amplifier in CMOS

The noise figure (NF) of a front-end low-noise amplifier (LNA) places a lower bound on the sensit... more The noise figure (NF) of a front-end low-noise amplifier (LNA) places a lower bound on the sensitivity of a receiver. In a conventional LNA, there is a tradeoff between the intrinsic input capacitance of the input transistors and the achievable bandwidth (BW) of the amplifier. This makes it necessary to use smaller transistors at higher gate overdrive voltages to simultaneously achieve greater BW and better NF. Unfortunately, biasing the transistor in this fashion yields a power-inefficient design. Furthermore, the need for a smaller capacitance presents a challenge to electrostatic discharge (ESD) protection of the input due to its added capacitance.

Research paper thumbnail of A tunable concurrent 6-to-18GHz phased-array system in CMOS

This paper presents a scalable phased-array receiver system that covers a tritave bandwidth of 6-... more This paper presents a scalable phased-array receiver system that covers a tritave bandwidth of 6-to-18 GHz implemented in a 130 nm CMOS process. The single receiver element with a 10-bit phase shifting resolution achieves a maximum phase error of 2.5deg within a baseband amplitude variation of 1.5 dB for an arbitrary target angle. This dense interpolation provides excellent phase error/offset calibration capability in the array. A 4-element electrical array pattern is measured at 6 GHz, 13.5 GHz and 18 GHz, showing a worst case peak-to-null ratio of 21.5 dB. The EVM and phase noise improvements of the array compared with the single receiver element are also shown.

Research paper thumbnail of A Scalable 6-to-18GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

Research paper thumbnail of A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

IEEE Journal of Solid-state Circuits, 2008

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