Philip Kohn | National Institutes of Health (original) (raw)

Papers by Philip Kohn

This report proposes a massively parallel computer, the Connectionist Network Supercomputer(CNS-1... more This report proposes a massively parallel computer, the Connectionist Network Supercomputer(CNS-1), which leverages off these fields. By targeting the computer to connectionist networks and related applications, we can focus on custom chip design and efficient ...

We report on recent advances in the ICSI connectionist speech recognition project. Highlights inc... more We report on recent advances in the ICSI connectionist speech recognition project. Highlights include:

Jpdc, 1992

... References. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 14, 248259 (1992) The Ring Array Pr... more ... References. JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 14, 248259 (1992) The Ring Array Processor: A Multiprocessing Peripheral for Connectionist Applications NELSON MORGAN, .TAMES BECK, PHIL KOHN, JEFF BILMES, ERIC ALLMAN, AND ...

In 1989 we designed and implemented a Ring Array Processor (RAP) for fast execution of our contin... more In 1989 we designed and implemented a Ring Array Processor (RAP) for fast execution of our continuous speech recognition training algorithms, which have been dominated by connectionist calculations. The RAP is a multi-DSP system with a low-latency ring interconnection scheme using programmable gate array technology and a signi cant amount of local memory per node (16 MBytes of dynamic memory and 256 KByte of fast static RAM). Theoretical peak performance is 128 MFlops/board, with sustained performance of 30-90% for back-propagation problems of interest to us. Systems with up to 40 nodes have been tested, for which throughputs of up to 574 Million Connections Per Second (MCPS) have been measured, as well as learning rates of up to 106 Million Connection Updates Per Second (MCUPS) for training. While the system is tuned to these algorithms, it is also a fully programmable computer, and users code in C++, C, and assembly language. Practical considerations such as workstation address space and clock skew restrict current implementations to 64 nodes, but in principle the architecture scales to about 16,000 nodes for back-propagation. We now have considerable experience with the RAP as a day-to-day computational tool for our research. With the aid of the RAP hardware and software, we have done network training studies that would have taken a signi cant fraction of a century on a UNIX workstation. We have also used the RAP to simulate variable precision arithmetic to guide us in the design of higher performance neurocomputers that are currently in the early stages of planning.

We propose a new method for reconstructing parameters of physiological interest within tissue. Th... more We propose a new method for reconstructing parameters of physiological interest within tissue. The novel aspect of this work is that we set out to determine not only the attenuation distribution but also the scattering characteristics of the unknown object. The model we propose contains, as a limiting case, the standard problem of X-ray tomography. In that case scattering (or

[1990] Proceedings of the International Conference on Application Specific Array Processors, 1990

... A simplified view of the RAP architecture is shown in Figure 1. In general, units of a ... us... more ... A simplified view of the RAP architecture is shown in Figure 1. In general, units of a ... user may also derive new C++ classes from RapClient for additional applications such as interactivegraphics programs or ... 300 International Conference on Application Specific Array Processors ...

[1992] Proceedings of the International Conference on Application Specific Array Processors, 1992

SPERT (Synthetic PERceptron Testbed) is a fully programmable single chip microprocessor designed ... more SPERT (Synthetic PERceptron Testbed) is a fully programmable single chip microprocessor designed for e cient execution of arti cial neural network algorithms. The rst implementation will be in a 1.2 m CMOS technology with a 50MHz clock rate, and a prototype system is being designed to occupy a double SBus slot within a Sun Sparcstation.

[Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing, 1991

The authors investigate the use of continuous features derived by perceptual linear predictive (P... more The authors investigate the use of continuous features derived by perceptual linear predictive (PLP) analysis, examine the effect of adding temporal features, and compare it to the previously studied use of multiframe input. Comparisons of the MLP (multilayer perceptron) and conventional Gaussian classifiers are also reported. The speaker-dependent portion of the Resource Management database was used for this test. Additionally,

[Proceedings 1992] IJCNN International Joint Conference on Neural Networks, 1992

SPERT (synthetic perceptron testbed) is a fully programmable single chip microprocessor designed ... more SPERT (synthetic perceptron testbed) is a fully programmable single chip microprocessor designed for efficient execution of artificial neural network algorithms. The first implementation will be in a 1.2 μm CMOS technology with a peak 50 MHz clock rate. A prototype system is being designed to occupy a double SBus slot within a sun Sparcstation. With fast external SRAM, SPERT will

The IMA Volumes in Mathematics and its Applications, 1992

Proceedings of SPIE - The International Society for Optical Engineering, 2011

One way to successfully enhance light harvesting of excitonic solar cells is the integration of o... more One way to successfully enhance light harvesting of excitonic solar cells is the integration of optical elements that increase the photon path length in the light absorbing layer. Device architectures which incorporate structural order in form of one- or three-dimensional refractive index lattices can lead to the localization of light in specific parts of the spectrum, while retaining the cell's

VLSI for Neural Networks and Artificial Intelligence, 1994