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Research paper thumbnail of Design and Analysis of a Modified Low Power CMOS Full Adder Using Gate-Diffusion Input Technique

Journal of Low Power Electronics, 2010

Research paper thumbnail of Classification of power quality problems using wavelet based artificial neural network

In this paper, a wavelet based artificial neural network classifier for recognizing power quality... more In this paper, a wavelet based artificial neural network classifier for recognizing power quality disturbances is implemented and tested. Discrete wavelet transforms based multi-resolution signal decomposition technique is integrated with the feed-forward neural network model to develop the power quality problem classifier. Classification of the power quality problems has been carried out in two parts. In first part, multi-resolution signal decomposition analysis with Parseval's energy theorem is used to extract the energy features of the power quality signal. In the second part, this feature information is used to develop neural network classifier. The classifier has been tested on various disturbances viz. voltage sag, swell, momentary interruption, capacitor switching and single line to ground fault. Results obtained show the versatility of the classifier for classifying the most commonly power quality problems.

Research paper thumbnail of Onmitigating power and delay in VLSI interconnects

Long interconnects in very large scale integration (VLSI) circuits result in high delays and powe... more Long interconnects in very large scale integration (VLSI) circuits result in high delays and power dissipation, thereby degrading the performance of an integrated circuit. The feasibilities of minimizing both delay and power dissipation in long interconnects by insertion of voltage-scaled repeaters have been explored in this paper. The results show a decrease in optimum number of repeaters with voltage-scaling, resulting in reduction of silicon area consumed and lesser heating of the chip. The analytical results for delay have been verified using SPICE simulations and a good agreement between the two has been observed. The simulation results for 0.8 mum and 0.18 mum CMOS technologies have been given

Research paper thumbnail of Transition time considerations in repeater-chains

Microelectronics International, 2005

Research paper thumbnail of Impact of process variability on universal gates

The exponential growth in the ULSI technology is due to scaling but the certainity in the perform... more The exponential growth in the ULSI technology is due to scaling but the certainity in the performance of chips is reducing in nano scale regime. The process variation is growing as a major concern and thus need to be analysed necessarily below sub micron regime. In this paper, the effect of process induced parameter variation on the delay of universal gate is analysed. Device variations fluctuations in MOS parameters viz. effective gate length (Leff), threshold voltage (Vth), thickness of the gate oxide (tox), and the drain/source region parasitic resistance (Rdsw) are considered in this work. The analysis is done with Monte Carlo method using T-SPICE for various technologies. The comparisons of the results show that process variations become important in deep sub micron regime and increase the uncertainity in speed.

Research paper thumbnail of Impact of skew and jitter on the performance of VLSI interconnects

The timing characteristics and performance of high-speed VLSI circuits is greatly dependent on th... more The timing characteristics and performance of high-speed VLSI circuits is greatly dependent on the interconnects which distribute power, clock and signal to the entire chip. The delay, power dissipation and cross-talk are the major design constraints for high performance VLSI interconnects. These non-ideal effects are dependent on temperature and timing constraint viz. skew and jitter. This paper presents in depth analysis of skew and jitter variation on the performance of VLSI interconnects. It is shown that variations of skew, jitter and temperature change the behaviour of coupled interconnect lines under different switching patterns. Results are obtained using SPICE simulations for 130nm technology node.

Research paper thumbnail of Investigations on Short-Circuit Power Dissipation in Repeater Loaded VLSI Interconnects

Journal of Low Power Electronics, 2007

Research paper thumbnail of Analysis of non-ideal effects in coupled VLSI interconnects with active and passive load variations

Microelectronics International, 2009

... Previous research works (Deutsch et al., 1997; Venkatesan et al., 2003; El-Moursy and Friedma... more ... Previous research works (Deutsch et al., 1997; Venkatesan et al., 2003; El-Moursy and Friedman, 2004; Ismail and Friedman, 2000; Ismail et al., 1999; Kahng and Muddu, 1997) focused on a driver-interconnect load model, where the load at far-end of ... In Kaushik et al. ...

Research paper thumbnail of Repeater insertion in global interconnects in VLSI circuits

Microelectronics International, 2005

... lines to be common features in VLSI chips. The long interconnections lead to prohibitively hi... more ... lines to be common features in VLSI chips. The long interconnections lead to prohibitively high propagation delays. Buffers are needed to drive the high capacitive nodes in order to keep pace with the required speed. For driving long interconnects, a single buffer is not a good ...

Research paper thumbnail of An analysis of interconnect delay minimization by low-voltage repeater insertion

Microelectronics Journal, 2007

The effect of voltage-scaling on interconnect delay minimization by CMOS-repeater insertion is an... more The effect of voltage-scaling on interconnect delay minimization by CMOS-repeater insertion is analyzed. Analytical models are developed to calculate the optimum number of repeaters as function of CMOS supply voltage. The analytically obtained results are in good agreement with SPICE extracted results. Analysis shows that voltage-scaling decreases power dissipation and the optimum number of repeaters required for delay minimization in long interconnects. Both resistive and inductive interconnects have been considered. At highly scaled voltages, the inductive interconnect has the advantage of lower power-delay product. It is also seen that voltage-scaling affects delay improvement due to repeater insertion. r

Research paper thumbnail of Repeater stage timing analysis for VLSI resistive interconnects

Microelectronics International, 2006

Research paper thumbnail of Delay analysis of a single voltage-scaled-repeater driven long interconnect

Microelectronics International, 2005

Research paper thumbnail of DELAY AND POWER MANAGEMENT OF VOLTAGE-SCALED REPEATER DRIVEN LONG INTERCONNECTS

International Journal of Modelling and Simulation, 2007

... 8. S. Dhar & MA Franklin, Optimum buffer circuits for driving long uniform lines ... ... more ... 8. S. Dhar & MA Franklin, Optimum buffer circuits for driving long uniform lines ... Friedman, & JL Neves, Exploiting the on-chip inductance in high-speed clock distribution ... Belleville, & J. Chilo, Inductance and capacitance analytic formulas for VLSI interconnects, Electronics Letters ...

Research paper thumbnail of Design and Analysis of Sub-DT Sub-Domino Logic Circuits for Ultra Low Power Applications

Journal of Low Power Electronics, 2010

Research paper thumbnail of Design and Analysis of a Modified Low Power CMOS Full Adder Using Gate-Diffusion Input Technique

Journal of Low Power Electronics, 2010

Research paper thumbnail of Classification of power quality problems using wavelet based artificial neural network

In this paper, a wavelet based artificial neural network classifier for recognizing power quality... more In this paper, a wavelet based artificial neural network classifier for recognizing power quality disturbances is implemented and tested. Discrete wavelet transforms based multi-resolution signal decomposition technique is integrated with the feed-forward neural network model to develop the power quality problem classifier. Classification of the power quality problems has been carried out in two parts. In first part, multi-resolution signal decomposition analysis with Parseval's energy theorem is used to extract the energy features of the power quality signal. In the second part, this feature information is used to develop neural network classifier. The classifier has been tested on various disturbances viz. voltage sag, swell, momentary interruption, capacitor switching and single line to ground fault. Results obtained show the versatility of the classifier for classifying the most commonly power quality problems.

Research paper thumbnail of Onmitigating power and delay in VLSI interconnects

Long interconnects in very large scale integration (VLSI) circuits result in high delays and powe... more Long interconnects in very large scale integration (VLSI) circuits result in high delays and power dissipation, thereby degrading the performance of an integrated circuit. The feasibilities of minimizing both delay and power dissipation in long interconnects by insertion of voltage-scaled repeaters have been explored in this paper. The results show a decrease in optimum number of repeaters with voltage-scaling, resulting in reduction of silicon area consumed and lesser heating of the chip. The analytical results for delay have been verified using SPICE simulations and a good agreement between the two has been observed. The simulation results for 0.8 mum and 0.18 mum CMOS technologies have been given

Research paper thumbnail of Transition time considerations in repeater-chains

Microelectronics International, 2005

Research paper thumbnail of Impact of process variability on universal gates

The exponential growth in the ULSI technology is due to scaling but the certainity in the perform... more The exponential growth in the ULSI technology is due to scaling but the certainity in the performance of chips is reducing in nano scale regime. The process variation is growing as a major concern and thus need to be analysed necessarily below sub micron regime. In this paper, the effect of process induced parameter variation on the delay of universal gate is analysed. Device variations fluctuations in MOS parameters viz. effective gate length (Leff), threshold voltage (Vth), thickness of the gate oxide (tox), and the drain/source region parasitic resistance (Rdsw) are considered in this work. The analysis is done with Monte Carlo method using T-SPICE for various technologies. The comparisons of the results show that process variations become important in deep sub micron regime and increase the uncertainity in speed.

Research paper thumbnail of Impact of skew and jitter on the performance of VLSI interconnects

The timing characteristics and performance of high-speed VLSI circuits is greatly dependent on th... more The timing characteristics and performance of high-speed VLSI circuits is greatly dependent on the interconnects which distribute power, clock and signal to the entire chip. The delay, power dissipation and cross-talk are the major design constraints for high performance VLSI interconnects. These non-ideal effects are dependent on temperature and timing constraint viz. skew and jitter. This paper presents in depth analysis of skew and jitter variation on the performance of VLSI interconnects. It is shown that variations of skew, jitter and temperature change the behaviour of coupled interconnect lines under different switching patterns. Results are obtained using SPICE simulations for 130nm technology node.

Research paper thumbnail of Investigations on Short-Circuit Power Dissipation in Repeater Loaded VLSI Interconnects

Journal of Low Power Electronics, 2007

Research paper thumbnail of Analysis of non-ideal effects in coupled VLSI interconnects with active and passive load variations

Microelectronics International, 2009

... Previous research works (Deutsch et al., 1997; Venkatesan et al., 2003; El-Moursy and Friedma... more ... Previous research works (Deutsch et al., 1997; Venkatesan et al., 2003; El-Moursy and Friedman, 2004; Ismail and Friedman, 2000; Ismail et al., 1999; Kahng and Muddu, 1997) focused on a driver-interconnect load model, where the load at far-end of ... In Kaushik et al. ...

Research paper thumbnail of Repeater insertion in global interconnects in VLSI circuits

Microelectronics International, 2005

... lines to be common features in VLSI chips. The long interconnections lead to prohibitively hi... more ... lines to be common features in VLSI chips. The long interconnections lead to prohibitively high propagation delays. Buffers are needed to drive the high capacitive nodes in order to keep pace with the required speed. For driving long interconnects, a single buffer is not a good ...

Research paper thumbnail of An analysis of interconnect delay minimization by low-voltage repeater insertion

Microelectronics Journal, 2007

The effect of voltage-scaling on interconnect delay minimization by CMOS-repeater insertion is an... more The effect of voltage-scaling on interconnect delay minimization by CMOS-repeater insertion is analyzed. Analytical models are developed to calculate the optimum number of repeaters as function of CMOS supply voltage. The analytically obtained results are in good agreement with SPICE extracted results. Analysis shows that voltage-scaling decreases power dissipation and the optimum number of repeaters required for delay minimization in long interconnects. Both resistive and inductive interconnects have been considered. At highly scaled voltages, the inductive interconnect has the advantage of lower power-delay product. It is also seen that voltage-scaling affects delay improvement due to repeater insertion. r

Research paper thumbnail of Repeater stage timing analysis for VLSI resistive interconnects

Microelectronics International, 2006

Research paper thumbnail of Delay analysis of a single voltage-scaled-repeater driven long interconnect

Microelectronics International, 2005

Research paper thumbnail of DELAY AND POWER MANAGEMENT OF VOLTAGE-SCALED REPEATER DRIVEN LONG INTERCONNECTS

International Journal of Modelling and Simulation, 2007

... 8. S. Dhar & MA Franklin, Optimum buffer circuits for driving long uniform lines ... ... more ... 8. S. Dhar & MA Franklin, Optimum buffer circuits for driving long uniform lines ... Friedman, & JL Neves, Exploiting the on-chip inductance in high-speed clock distribution ... Belleville, & J. Chilo, Inductance and capacitance analytic formulas for VLSI interconnects, Electronics Letters ...

Research paper thumbnail of Design and Analysis of Sub-DT Sub-Domino Logic Circuits for Ultra Low Power Applications

Journal of Low Power Electronics, 2010