rajeevan chandel | NIT Hamirpur (original) (raw)

Papers by rajeevan chandel

The performance analysis of the two-stage CMOS operational amplifiers employing Miller capacitor ... more The performance analysis of the two-stage CMOS operational amplifiers employing Miller capacitor in conjunction with the common-gate current buffer is presented. Unlike the previously reported design strategy of the opamp of this type, which results in the opamp with a lower power supply requirements, better phase margin and better speed. The Opamp is designed to exhibit a unity gain frequency of 1.46GHz and exhibits a gain of 115dB with a 117˚ phase margin. As compared to the conventional approach, the indirect compensation method results in a higher unity gain frequency under the same load condition. Simulation has been carried out in LT-SPICE.

Analog Integrated Circuits and Signal Processing, 2019

Microelectronics International, 2009

PurposeThe aim of this paper is to analyze the effects of aggressor‐line load variations (both ac... more PurposeThe aim of this paper is to analyze the effects of aggressor‐line load variations (both active gate and passive capacitive loads) on the non‐ideal effects of a coupled VLSI‐interconnect system.Design/methodology/approachSignal delay, power dissipation and crosstalk noise in interconnect can be influenced by variation in load of another interconnect which is coupled to it. For active gate and passive capacitive load variations, such effects are studied through SPICE simulations of a coupled interconnect pair in a 0.13 μm technology. Crosstalk between a coupled pair, is affected by transition time of the coupled signal, interconnect length, distance between interconnects, size of driver and receiver, pattern of input, direction of flow of signal and clock skew. In this work, influence of an aggressor‐line load variations (both active gate and passive capacitive loads) on the non‐ideal effects of delay, power consumption and crosstalk in a victim‐line of a coupled VLSI‐interconn...

2017 Tenth International Conference on Contemporary Computing (IC3), 2017

In modern technologies, read stability and write ability have become major concerns in nano regim... more In modern technologies, read stability and write ability have become major concerns in nano regime for static random access memory (SRAM) cell. This paper provides the stability analysis of 6T-SRAM cell using the N-curve method. Various performance parameters namely SVNM, SINM, WTV, and WTI are evaluated for SRAM. Variation of SVNM, SINM, WTV and WTI with scaled supply voltage has been presented. A comparative analysis of CNTFET and GNRFET with conventional CMOS technology using HSPICE tool has been performed. To ensure a fair comparison of (19,0) CNTFET(DCNT=1.49nm) and (13,0) GNRFET(width=1.49nm) dimensions have been chosen for proper circuit size integration. The simulation results show that the SRAM cells designed using CNT and GNR field effect transistors (FETs) have better stability as compared to CMOS technology.

A modified inductance-capacitance voltage controlled oscillator (LC-VCO) topology is presented in... more A modified inductance-capacitance voltage controlled oscillator (LC-VCO) topology is presented in this paper. NMOS only varactor has been used instead of variable capacitance. The frequency of oscillation of the VCO is 7.68GHz with a power dissipation of 5.68mW. The designed oscillator is characterized by a tuning range of 26.73%. Compared to the reference circuit, there is an improvement in frequency of oscillation of the LC-VCO. The design is verified using SPICE simulations. Key WordsInductance Capacitance-Voltage Controlled Oscillator, Ultra-wideband frequency, VCO.

International Journal of Global Technology Initiatives, 2014

Scaling of silicon technology has led to its curtailed use for high-performance digital circuits.... more Scaling of silicon technology has led to its curtailed use for high-performance digital circuits. Subsequently, researchers are investigating other novel materials, structures and devices for enhancing circuit performance. Carbon nanotubes (CNTs) have come out as a possibility for the same due to their excellent carrier mobility and faster carrier transport properties. This paper overviews CNTFETs and some compact models. Using the available models, CNT based digital circuits have been analyzed. The parameters like chirality, diameter and threshold voltage for CNTFET and their influence of these parameters on the device characteristics are investigated. A comparative analysis of CMOS and CNTFET logic circuits is carried out. Voltage and current transfer characteristics of CNTFET inverter are presented. Performance metrics viz. delay, power and power delay product (PDP) are analyzed. It is found that CNTFET based circuits are energy efficient. All the circuits have been simulated on ...

International Journal of Modelling and Simulation, 2015

Current-mode signalling significantly increases the bandwidth of on-chip interconnects and reduce... more Current-mode signalling significantly increases the bandwidth of on-chip interconnects and reduces the overall propagation delay. The inductive effect of interconnects is more dominant in submicron technologies. This is because an RC interconnects model results in a significant error in delay estimation. Consequently to avoid such errors, a delay model for current-mode signalling is proposed for RLC interconnect line in the present work. RLC interconnect line is modelled using characteristic impedance of line. The inductive effects which are dominant at lower technology nodes are modelled as an equivalent resistance (). RLC line is modelled into a new equivalent ReffC interconnect line. The efficacy of the proposed model is validated for 8 and 10 mm interconnect lines. It is inferred that current mode provides better performance compared to the voltage-mode signalling. It is found that current-mode signal transporting technique provides higher speed improvements. Secondly, the damping factor of a lumped RLC circuit is shown to be a useful figure of merit. The analysis is carried out for 180 nm technology node.

IETE Journal of Research, 2000

Silicon micromachining has become a fundamental tool for the realization of micro-electromechanic... more Silicon micromachining has become a fundamental tool for the realization of micro-electromechanical devices. In the work presented here silicon dioxide based cantilevers are used as the basis for the development of the electrostatic microactuators. Direct wafer bonding technology has been utilized for the formation of the microactuators. The fabrication of cantilever beam microactuators has been accomplished. The complete design and fabrication feasibilities of the dielectric based electrostatic microswitch using direct wafer bonding have been proposed. The optimization of the various fabrication processes for these microactuators has been reported in this paper.

Energy Systems in Electrical Engineering, 2014

As technology advances toward the nanometer regime, process variability has emerged as a serious ... more As technology advances toward the nanometer regime, process variability has emerged as a serious concern in the design of VLSI circuits including interconnects. The process variations result in performance fluctuations in the circuit design and pose challenges as technology scales down. According to ITRS, scaled down VLSI technology together with novel process steps adds to the improvement and performance of deep submicron devices. However, fabrication process tolerances have not scaled proportionally with device dimensions. This has significantly increased the variation susceptibility in several key process parameters during the device fabrication. The increase in variability affects the design of low-power circuits in the nanometer regime. This causes fluctuations in the IC performance. Therefore, the relative impact of process variations on power and timing has become more significant with each technology generation.

Materials and Manufacturing Processes, 1998

A new welding method, flux bands constricting arc (FBCA) welding, is proposed to compensate for t... more A new welding method, flux bands constricting arc (FBCA) welding, is proposed to compensate for the shortage of insufficient weld width of laser welding T-joints in high steel sandwich panels. The arc behavior (arc burning position, arc shape, arc heat, and arc stability) before and after sticking the flux bands (GMAW and FBCA welding) to the ultra-narrow gap groove was tested. Results indicate that flux bands have solid-wall constricting effect (SWCE) and thermo-compression effect (TCE) on the arc and self-producing slag and gas function in FBCA welding. In ultra-narrow gap groove, the arc burning position climbing up phenomenon (APCP) occurs without flux bands. The SWCE of flux bands on the arc effectively suppresses the APCP because of the insulation of flux bands. In the FBCA welding process, the effective heating area of the arc is increased by at least 5 mm 2 compared with that in GMAW. When the groove gap decreases, flux bands not only compress the arc from an inverted bell shape to a rectangular shape, but also make the 660 • C isotherm on the core-plate to increase from 3 mm to 8 mm. In the end, the proportion of unstable arc burning time is reduced by 86.85%, the fluctuation of arc voltage and welding current are also significantly reduced by the flux bands because of their SWCE on the arc.

2020 7th International Conference on Smart Structures and Systems (ICSSS), 2020

India is world's largest democracy and the essence of any democracy lies in the fact that peo... more India is world's largest democracy and the essence of any democracy lies in the fact that people choose their own representatives. But in present era, the fair election process is facing a lot of problems like booth capturing, rigging, fake voting, tampering with the Electronic Voting Machines (EVMs) etc. Being responsible engineers, it's our duty to do something to curb this menace. In the commonly used EVMs, the voting process takes place electronically and this eliminates the use of ballot paper to cast votes in elections as it is very time consuming and errors might crawl in intentionally or unintentionally. Today authenticity of the voter is a big concern and it also should be made sure that a same voter is not able to vote two times. This issue can be dealt with by introducing biometric based voting system, where the authenticity of a voter is established based on fingerprints. Hence, the principle shall be one person, one authentic vote. In the present work, a prototype fingerprint based biometric voting machine has been developed. It is proposed that a feature that will link the Aadhaar database of Unique Identification Authority of India (UIDAI), Govt. of India, New Delhi; can be embedded. This shall facilitate all the voters to get registered on the portal automatically, which can be classified on the basis of regions and constituencies based on their unique identification i.e. their finger prints. This shall enable the device developed in the present research work, at the national level of application by using it in elections conducted around the country. This shall lead to a significant contribution for the betterment of the Indian election system.

Proceedings of the International Conference & Workshop on Emerging Trends in Technology - ICWET '11

... 6. REFERENCES [1] Alam N., Kureshi AK, Hasan Mohd., and Arslan T., Analysis of Carbon Nanotu... more ... 6. REFERENCES [1] Alam N., Kureshi AK, Hasan Mohd., and Arslan T., Analysis of Carbon Nanotube Interconnects and their comparison with Cu Interconnects, International Multimedia, Signal Processing and Communication Technologies, pp. 124-127, 2009. ...

International Journal of Modeling, Simulation, and Scientific Computing

With technology scaling, stability, power dissipation, and device variability, the impact of proc... more With technology scaling, stability, power dissipation, and device variability, the impact of process, voltage and temperature (PVT) variations has become dominant for static random access memory (SRAM) analysis for productivity and failure. In this paper, ten-transistors (10T) and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors (FGMOS). Power centric parameters viz. read power, write power, hold power and delay are the performance analysis metrics. Further, the stochastic parameter variation to study the variability tolerance of the redesigned cell, PVT variations and Monte Carlo simulations have been carried out for 10T FGMOS SRAM cell. Stability has been illustrated with the conventional butterfly method giving read static noise margin (RSNM) and write static noise margin (WSNM) metrics for read stability and write ability, respectively. A comparative analysis with standard six-transistor SRAM cell is carried out. HSPICE simulative analysi...

2021 Innovations in Power and Advanced Computing Technologies (i-PACT), 2021

Code Excited Linear Prediction (CELP) leads to enhancement over Linear Prediction Coefficient (LP... more Code Excited Linear Prediction (CELP) leads to enhancement over Linear Prediction Coefficient (LPC) coder in terms of decoded speech superiority and the encoded bit rate (4.8Kbps). The proposed work shows the different types of codebooks and their advantages, design, and implementation for the stochastic excitation codebook (ternary codebook) with reduced memory requirement along with an address generator module. A recursive filter namely, perceptual weighting filter is designed to achieve enhanced speech quality with reduced hardware requirements.

i-manager's Journal on Electronics Engineering, 2010

Energy Systems in Electrical Engineering, 2020

Over the years, a rapid growth has been witnessed in electronics semiconductor industry because o... more Over the years, a rapid growth has been witnessed in electronics semiconductor industry because of the huge demand for system-level designs. System-level designs are prominently used for various applications such as high-performance computing, controls, telecommunications, image and video processing, consumer electronics and others. Hence to accomplish such applications using very largescale integration (VLSI) design, it is recommended to have an efficient registertransfer-level (RTL) design abstraction, as it can provide a low power and highperformance outcome (Wu and Liu in IEEE Trans Very Large Scale Integr (VLSI) Syst 6:707-718, Wu and Liu 1998). In digital integrated circuit (IC) design, RTL models a synchronous digital circuit in terms of the flow of digital signals or data between hardware registers and the logical operations performed on these signals. RTL abstraction is used in hardware description languages (HDLs) to create highlevel representations of a circuit (Chinedu et al. in 3rd IEEE international conference on adaptive science and technology (ICAST 2011). IEEE, pp 262-267, Chinedu et al. 2011). From these lower-level representations, ultimately actual circuitry can be derived. Design at the RTL level is a typical practice in modern digital system designs. This chapter mainly focuses on design of RTLs for application-specific integrated circuits (ASICs) and how it differs for field-programmable gate arrays (FPGAs). The examples and modules discussed in this chapter are written in HDL, viz. Verilog language.

In this paper a technique is presented which improves the noise immunity of TSPC circuit. This te... more In this paper a technique is presented which improves the noise immunity of TSPC circuit. This technique is compared with other existing techniques. Analysis is carried out both for super and sub-threshold regions of operation. Investigations consider different performance criteria viz. n ooise immunity curve, power consumption, delay, average noise threshold energy (ANTE), PANTE and DANTE. The new technique gives better results in the form of improved noise immunity of the TSPC logic. It is found that power dissipation is decreased by over three orders in sub-threshold regime. Scaled technology offers better noise immunity in sub-threshold regime. Simulation results are presented for 180nm technology node.

2017 International Conference on Inventive Communication and Computational Technologies (ICICCT), 2017

Due to the scaling of devices in nanometer regime speed and power related issues rises in digital... more Due to the scaling of devices in nanometer regime speed and power related issues rises in digital circuits. Carbon nanotube field effect transistor (CNTFET) has been used in the present work as a low power circuit element. The major advantage of CNTFET is low power and energy consumption as compared to the conventional CMOS. This paper proposes the basic implementation of CNTFET inverter, MUX and DEMUX circuits. A comparative analysis with conventional CMOS technology using HSPICE tool in 32nm technology with 1.42nm CNT diameter is performed. The simulation results show nearly 94%, 97% and 98% reduction in energy for CNTFET based Inverter circuit, 8:1 MUX and 1:8 DEMUX respectively as compared to CMOS technology.