Gerardo Pelosi | Politecnico di Milano (original) (raw)

Papers by Gerardo Pelosi

Research paper thumbnail of Elliptic Curve Cryptography

Research paper thumbnail of Secure Audit Logs

Research paper thumbnail of Secure Index

Research paper thumbnail of Securing software cryptographic primitives for embedded systems against side channel attacks

2014 International Carnahan Conference on Security Technology (ICCST), 2014

Research paper thumbnail of Smart Meters and Home Gateway Scenarios

Research paper thumbnail of Towards Transparently Tackling Functionality and Performance Issues across Different OpenCL Platforms

2014 Second International Symposium on Computing and Networking, 2014

Research paper thumbnail of Snake: An End-to-End Encrypted Online Social Network

2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC,CSS,ICESS), 2014

Research paper thumbnail of Simulation-Time Security Margin Assessment against Power-Based Side Channel Attacks

Research paper thumbnail of Protecting access confidentiality with data distribution and swapping

Research paper thumbnail of High speed cipher cracking: the case of Keeloq on CUDA

Research paper thumbnail of Design time engineering of side channel resistant cipher implementations

Research paper thumbnail of Differential Fault Analysis for Block Ciphers

Proceedings of the 7th International Conference on Security of Information and Networks - SIN '14, 2014

Research paper thumbnail of Symmetric Key Encryption Acceleration on Heterogeneous Many-Core Architectures

Algorithms and Implementations Using C++, 2014

Research paper thumbnail of Trace-based schedulability analysis to enhance passive side-channel attack resilience of embedded software

Information Processing Letters, 2015

Research paper thumbnail of Security challenges in building automation and SCADA

2014 International Carnahan Conference on Security Technology (ICCST), 2014

Research paper thumbnail of Design space extension for secure implementation of block ciphers

IET Computers & Digital Techniques, 2014

Research paper thumbnail of Fault Sensitivity Analysis at Design Time

Trusted Computing for Embedded Systems, 2014

Research paper thumbnail of Computer Security Anchors in Smart Grids: The Smart Metering Scenario and Challenges

Trusted Computing for Embedded Systems, 2014

Research paper thumbnail of Software implementation of tate pairing over GF(2m)

Proceedings -Design, Automation and Test in Europe, DATE, 2006

Recently, the interest about the Tate pairing over binary fields has decreased due to the existen... more Recently, the interest about the Tate pairing over binary fields has decreased due to the existence of efficient attacks to the discrete logarithm problem in the subgroups of such fields. We show that the choice of fields of large size to make these attacks infeasible does not lead to a degradation of the computation performance of the pairing. We describe

Research paper thumbnail of Parallel hardware architectures for the cryptographic tate pairing

Research paper thumbnail of Elliptic Curve Cryptography

Research paper thumbnail of Secure Audit Logs

Research paper thumbnail of Secure Index

Research paper thumbnail of Securing software cryptographic primitives for embedded systems against side channel attacks

2014 International Carnahan Conference on Security Technology (ICCST), 2014

Research paper thumbnail of Smart Meters and Home Gateway Scenarios

Research paper thumbnail of Towards Transparently Tackling Functionality and Performance Issues across Different OpenCL Platforms

2014 Second International Symposium on Computing and Networking, 2014

Research paper thumbnail of Snake: An End-to-End Encrypted Online Social Network

2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC,CSS,ICESS), 2014

Research paper thumbnail of Simulation-Time Security Margin Assessment against Power-Based Side Channel Attacks

Research paper thumbnail of Protecting access confidentiality with data distribution and swapping

Research paper thumbnail of High speed cipher cracking: the case of Keeloq on CUDA

Research paper thumbnail of Design time engineering of side channel resistant cipher implementations

Research paper thumbnail of Differential Fault Analysis for Block Ciphers

Proceedings of the 7th International Conference on Security of Information and Networks - SIN '14, 2014

Research paper thumbnail of Symmetric Key Encryption Acceleration on Heterogeneous Many-Core Architectures

Algorithms and Implementations Using C++, 2014

Research paper thumbnail of Trace-based schedulability analysis to enhance passive side-channel attack resilience of embedded software

Information Processing Letters, 2015

Research paper thumbnail of Security challenges in building automation and SCADA

2014 International Carnahan Conference on Security Technology (ICCST), 2014

Research paper thumbnail of Design space extension for secure implementation of block ciphers

IET Computers & Digital Techniques, 2014

Research paper thumbnail of Fault Sensitivity Analysis at Design Time

Trusted Computing for Embedded Systems, 2014

Research paper thumbnail of Computer Security Anchors in Smart Grids: The Smart Metering Scenario and Challenges

Trusted Computing for Embedded Systems, 2014

Research paper thumbnail of Software implementation of tate pairing over GF(2m)

Proceedings -Design, Automation and Test in Europe, DATE, 2006

Recently, the interest about the Tate pairing over binary fields has decreased due to the existen... more Recently, the interest about the Tate pairing over binary fields has decreased due to the existence of efficient attacks to the discrete logarithm problem in the subgroups of such fields. We show that the choice of fields of large size to make these attacks infeasible does not lead to a degradation of the computation performance of the pairing. We describe

Research paper thumbnail of Parallel hardware architectures for the cryptographic tate pairing