Felipe Kuentzer | Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS) (original) (raw)

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Papers by Felipe Kuentzer

2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

IEEE Transactions on Circuits and Systems I: Regular Papers

Analog Integrated Circuits and Signal Processing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016

— Type D flip-flop cell and its scannable version called Muxed-D are the most used sequential com... more — Type D flip-flop cell and its scannable version called Muxed-D are the most used sequential components in cell-based synchronous designs because it simplifies timing analysis and it is less susceptible to race problems. However, as technology nodes shrink, it becomes more difficult, especially for high-performance designs, to cope with a hard global timing boundary. The use of latches emerges as a possible solution to the contemporary design challenges such as clock skew/jitter, PVT variation, and low-power and high-performance designs. Moreover, latches are also gaining popularity among asynchronous and timing resilient circuits. One of the available scannable cells for latches is called level sensitivity scan-based design (LSSD). The goal of this brief is to present an open design of an optimized single-latch LSSD cell, which has better tradeoffs between propagation delay, power, energy, and silicon area than the original LSSD design, thus reducing the cost for testing latch-based designs. Index Terms— Latch-based design, level sensitive scan-based design (LSSD), scan cell, VLSI testing.

—Resilient architectures emerged as a promising solution to remove worst-case timing margins adde... more —Resilient architectures emerged as a promising solution to remove worst-case timing margins added due to process, voltage and temperature variation, improving system performance while reducing energy consumption. Asynchronous circuits can also improve energy efficiency and performance due to the absence of a global clock. A recently proposed circuit template, called Blade, leverages the advantages of both asynchronous and resilient techniques. However, Blade still presents challenges in terms of testing, which hinder its practical application. This paper evaluates the fault behavior of the Error Detection Logic (EDL) block of Blade with single stuck-at or propagation delay fault models. We propose a fault classification based on the effects observed in the overall circuit operation while in the presence of a fault. This classification shows the obtained fault coverage assuming three different testability scenarios and it also shows that a single fault can entirely disable an EDL, disabling its resilience. The proposed classification can be used in the future to improve the design for testability of resilient architectures.

Analysis by Transcriptogram was developed as a solution to reduce the noise in the micro array me... more Analysis by Transcriptogram was developed as a solution to reduce the noise in the micro array measuring technique of the Transcriptome, and has demonstrated potential to be applied as a method of disease diagnostics. The noise reduction in the measurement is achieved by ordering the proteins of a given protein interaction network in a linear way, allowing gene expression analysis in whole genome scale. The ordering process uses a seriation technique, which models a protein-protein association network into an undirected graph. So far, the viability of the diagnosis method was hindered by the high runtime of the ordering algorithm, since the Homo sapiens network can have around 30 thousand proteins. This paper presents some optimizations applied to the seriation problem, which lead to a significant reduction of execution time and the problem complexity analysed. Results show that the algorithm produces good results in reasonable time, e.g. Order an undirected network of 9684 nodes in about 35 minutes, which is faster if compared with other seriation techniques evaluated.