Santosh Kurinec | Rochester Institute of Technology (original) (raw)

Papers by Santosh Kurinec

Research paper thumbnail of A Comparative Study of n- and p- Channel FeFETs with Ferroelectric HZO Gate Dielectric

This study investigates the electrical characteristics observed in n- channel and p-channel ferro... more This study investigates the electrical characteristics observed in n- channel and p-channel ferroelectric field effect transistor (FeFET) devices fabricated through a similar process flow with 10 nm of ferroelectric hafnium zirconium oxide (HZO) as the gate dielectric. The n-FeFETs demonstrate a faster complete polarization switching compared to the p-channel counterparts. Detailed and systematic investigations using TCAD simulations reveal the role of fixed charges and interface traps at the HZO-interfacial layer (HZO/IL) interface in modulating the subthreshold characteristics of the devices. A characteristic crossover point observed in the transfer characteristics of n-channel devices is attributed with the temporary switching between ferroelectric-based operation to charge-based operation, caused by the pinning effect due to the presence of different traps. This experimental study helps understand the role of charge trapping effects in switching characteristics of n- and p-chann...

Research paper thumbnail of Trap Capture and Emission Dynamics in Ferroelectric Field-Effect Transistors and their Impact on Device Operation and Reliability

2021 IEEE International Electron Devices Meeting (IEDM), 2021

We track carrier capture and emission dynamics during write operations in n-type ferroelectric-fi... more We track carrier capture and emission dynamics during write operations in n-type ferroelectric-field-effect transistors (FEFETs) by directly and separately measuring the trap related hole and electron currents through the body terminal and shorted source-drain, respectively. Both electron and hole currents are simultaneously observed during polarization switching, irrespective of whether the channel is in hole accumulation or electron inversion. This allows us to discover the exact mechanism of emission and capture of carriers, which leads to partial neutralization of the traps charged in the previous write cycle. With fatigue cycling, the neutralization of trapped charges progressively decreases, and the density of trap states increases leading to IGI_{G}IG, SS and peak gmg_{m}gm degradation. An increase in the effective time constant of trap states is also evident with cycling as a fatigued FEFET requires longer time to reach a given memory window after a write operation. We conclude that the memory window in FEFETs is facilitated by neutralization of traps, previously charged by carriers captured during FE switching (i. e., write operation) that screen the ferroelectric polarization. These emission and capture dynamics place the trap levels close to EcE_{c}Ec and EvE_{v}Ev and inside the SiO2 and at the SiO2/HZO interface, and currently hinders high-speed read-after-write in front-end FEFETs. The universality of the suggested mechanisms is confirmed in FEFETs fabricated in different facilities.

Research paper thumbnail of Unraveling the Dynamics of Charge Trapping and De-Trapping in Ferroelectric FETs

IEEE Transactions on Electron Devices, 2022

In this work, a comprehensive study of charge trapping and de-trapping dynamics is performed on n... more In this work, a comprehensive study of charge trapping and de-trapping dynamics is performed on n-channel ferroelectric field-effect transistors (nFeFETs) and pFeFETs. It is discovered that: 1) the degree of charge trapping depends on the substrate that nFeFETs exhibit significant electron trapping but negligible hole trapping during memory write while pFeFETs exhibit much less electron trapping but significant hole trapping when heavily stressed; 2) due to enhanced electric field in the interlayer and semiconductor, the like initial polarization states (i.e., initialized by a pulse of the same polarity as the write pulse) could exacerbate charge trapping induced by the write pulse; 3) electron trapping is fully recoverable while hole trapping shows a semi-permanent component which involves interface trap generation; and 4) less significant charge trapping in pFeFETs allows immediate read-after-write at normal operating conditions.

Research paper thumbnail of FeFET-Based Neuromorphic Architecture with On-Device Feedback Alignment Training

2020 21st International Symposium on Quality Electronic Design (ISQED), 2020

With the onset of on-device learning in neuromorphic systems, there are a requisition for compute... more With the onset of on-device learning in neuromorphic systems, there are a requisition for compute-lite learning rules and novel emerging devices that address the memory bottleneck. In this research, we propose a neuromorphic architecture with FeFET synapse arrays and study the efficacy of write schemes for feedback alignment backpropagation algorithm. The proposed architecture is benchmarked for two write programming schemes, sawtooth pulse and incremental pulse. The sawtooth write programming scheme is further simplified for resource efficient training, by sharing the pulse generator with local control circuitry across multiple neurons. When the overall architecture is benchmarked for on-device learning, we observed that both writing schemes result in comparable performance, but the sawtooth is more efficient in terms of power consumption and area.

Research paper thumbnail of Utilization of electroluminescence from avalanche p-n junctions for optical testing of silicon integrated circuits

Proceedings., Eighth University/Government/Industry Microelectronics Symposium

ABSTRACT

Research paper thumbnail of Development and characterization of 10 nm, N/sub 2/-implanted nitrided oxides for gate dielectrics

Proceedings of the Thirteenth Biennial University/Government/Industry Microelectronics Symposium (Cat. No.99CH36301)

ABSTRACT

Research paper thumbnail of AVT-RIT-NSF partnership for the development of low voltage thin film phosphor for field emission display devices

Proceedings of the Thirteenth Biennial University/Government/Industry Microelectronics Symposium (Cat. No.99CH36301)

... 6, No. 3, p. 181. 1998. [2] Philip D. Rack, Michael D. Potter, Andrew Woodard and Santosh Kur... more ... 6, No. 3, p. 181. 1998. [2] Philip D. Rack, Michael D. Potter, Andrew Woodard and Santosh Kurinec, “Negative Ion Re-sputtering in Ta2Zn308 Thin Films,” Materials Research Society National Spring Meeting, April 1999, E4.4. [3] G. Blasse, Structure and Bonding. ...

Research paper thumbnail of A new program at RIT: master of engineering in microelectronics manufacturing engineering

Proceedings., Eighth University/Government/Industry Microelectronics Symposium

Rochester Institute of Technology, College of Engineering, has established a new master of engine... more Rochester Institute of Technology, College of Engineering, has established a new master of engineering degree program in microelectronics manufacturing engineering. The program is one year (four quarters) in duration and is designed for BS graduates in engineering or science. The core courses are Microelectronics I, II, III, Microlithography I, II, and Manufacturing Science I, II. Concentration courses may be selected from a list of courses including computer integrated manufacturing, statistical design of experiments, facilities design, safety, and others. The core courses are discussed, and the facilities are described

Research paper thumbnail of Challenges in integration of Resonant Interband Tunnel Devices with CMOS

Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488), 2003

The fabrication of SiGe Resonant Interband Tunnel Devices (RITD) using CMOS compatible processes ... more The fabrication of SiGe Resonant Interband Tunnel Devices (RITD) using CMOS compatible processes requires ability to form RITD structures selectively on source/drain regions. Various approaches were investigated and RITDs have been realized in lithographically defined openings in oxide on Si wafers. Patterned growth RITD on p+ Si exhibited a peak-tovalley current ratio (PVCR) of 3.0 and peak current density (J p) of 188 A/cm 2 whereas RITD of p+ implanted regions resulted in a PVCR of 2.5 with J p of 278 A/cm 2. Blanked growth RITD on p+ implanted substrate yielded a superior PCVR of 3.3 and J p of 332 A/cm 2. The observed effects of patterned growth and implanted substrate on the RITD device performance are critical challenges addressed in this study for RITD-CMOS integration.

Research paper thumbnail of 25 Years of Microelectronic Engineering Education

2006 16th Biennial University/Government/Industry Microelectronics Symposium, 2006

Abstract-Rochester Institute of Technology started the nation's first Bachelor o... more Abstract-Rochester Institute of Technology started the nation's first Bachelor of Science program in Microelectronic Engineering in 1982. The program has kept pace with the rapid advancements in semiconductor technology, sharing 25 of the 40 years characterized by Moore's Law. ...

Research paper thumbnail of Microelectronics Manufacturing Education

Proceedings. IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop

ABSTRACT

Research paper thumbnail of K-12 teachers forum on microelectronics and nanotechnology

2007 International Semiconductor Device Research Symposium, 2007

ABSTRACT

Research paper thumbnail of Modeling the thermal behavior of chalcogenide based phase change memory cell

2007 International Semiconductor Device Research Symposium, 2007

The presented work, reports a 2D thermal model for a PCM cell employing stacked Ge-chalcogenide (... more The presented work, reports a 2D thermal model for a PCM cell employing stacked Ge-chalcogenide (Ge2Se3) and Sn-chalcogenide (SnSe) layers as phase change materials. The thermal behavior exhibited by the PCM cell upon melting of the Ge2Se3 layer is explored at the 130nm, 65nm and 45nm technology nodes. The suitability of doped polysilicon, TiN and TaSiNx as potential heater materials

Research paper thumbnail of Summer innovation experience for undergraduates in semiconductor technology

... Santosh Kurinec, Sean Rommel, Dale Ewbank and Karl Hirschman Rochester Institute of Technolog... more ... Santosh Kurinec, Sean Rommel, Dale Ewbank and Karl Hirschman Rochester Institute of Technology skkemc@rit.edu;slremc@rit.edu ... Based on the authors' experience with the NSF “Research Experience for Undergraduates (REU)” program, this pilot program “Summer ...

Research paper thumbnail of Modeling, simulation and verification of void transfer process for patterning nm scale features

2009 International Semiconductor Device Research Symposium, 2009

ABSTRACT

Research paper thumbnail of Blue cathodoluminescence from tantalum zinc oxide

Proceedings of the UGIM Symposium, Microelectronics Education for the Future. Twelfth Biennial University/Government/Industry Microelectronics Symposium (Cat. No.97CH36030), 1997

We have observed cathodoluminescence (CL) at low voltages (-60 V) with a peak at-410

Research paper thumbnail of Care and feeding of a university cleanroom facility

Proceedings., Eighth University/Government/Industry Microelectronics Symposium

The authors describe the systems that have been established for the operation of the microelectro... more The authors describe the systems that have been established for the operation of the microelectronics facility at the Rochester Institute of Technology. Attention is given to the organizational structure; support facilities; cleanroom maintenance; lab equipment; equipment operation; lab supplies, inventory, and control; lab safety; and the hazardous waste program

Research paper thumbnail of Residual Stress Analysis of Stacked SnTe/Ge2Se3 Phase Change Memory Films using Vantec 2000 Area Detector

... ψ 2 sin Acknowledgement The authors wish to thank Dr. Kris Campbell and her team for providin... more ... ψ 2 sin Acknowledgement The authors wish to thank Dr. Kris Campbell and her team for providing the as-deposited film stacks and Dr. Vinnie Gupta for his help in editing the paper and offering very important and insightful suggestions. ... 349-355, 2004. [7] S. Lai, “Current status ...

Research paper thumbnail of Teaching solar cell I-V characteristics using SPICE

American Journal of Physics, 2011

The basic equivalent circuit of a p-n junction solar cell is most commonly represented as consist... more The basic equivalent circuit of a p-n junction solar cell is most commonly represented as consisting of a current source in parallel with two diodes and two parasitic resistances. The output of a solar cell is measured by obtaining the current-voltage (I–V) characteristics for different illumination intensities, and various parameters are extracted from these characteristics. Because the nature of the information derived from these characteristics is not obvious to the beginning students in photovoltaics, a simulation using SPICE was utilized to explain three solar cell I–V characteristics—dark I–V, illuminated I–V, and open circuit voltage versus the short circuit current (illumination intensity). Students can construct a solar cell and study the effect of the diode and parasitic parameters on the three output I–V characteristics. Series and parallel combinations of solar cells for arrays and modules using bypass diodes are demonstrated using SPICE as educational tools for understa...

Research paper thumbnail of Monitoring a photovoltaic system during the partial solar eclipse of August 2017

EPJ Photovoltaics, 2018

The power output of a 4.85 kW residential photovoltaic (PV) system located in Rochester, NY is mo... more The power output of a 4.85 kW residential photovoltaic (PV) system located in Rochester, NY is monitored during the partial solar eclipse of August 21, 2017. The data is compared with the data on a day before and on the same day, a year ago. The area of exposed solar disk is measured using astrophotography every 16 s of the eclipse. Global solar irradiance is estimated using the eclipse shading, time of the day, location coordinates, atmospheric conditions and panel orientation. A sharp decline, as expected in the energy produced is observed at the time of the peak of the eclipse. The observed data of the PV energy produced is related with the model calculations taking into account solar eclipse coverage and cloudiness conditions. The paper provides a cohesive approach of irradiance calculations and obtaining anticipated PV performance.

Research paper thumbnail of A Comparative Study of n- and p- Channel FeFETs with Ferroelectric HZO Gate Dielectric

This study investigates the electrical characteristics observed in n- channel and p-channel ferro... more This study investigates the electrical characteristics observed in n- channel and p-channel ferroelectric field effect transistor (FeFET) devices fabricated through a similar process flow with 10 nm of ferroelectric hafnium zirconium oxide (HZO) as the gate dielectric. The n-FeFETs demonstrate a faster complete polarization switching compared to the p-channel counterparts. Detailed and systematic investigations using TCAD simulations reveal the role of fixed charges and interface traps at the HZO-interfacial layer (HZO/IL) interface in modulating the subthreshold characteristics of the devices. A characteristic crossover point observed in the transfer characteristics of n-channel devices is attributed with the temporary switching between ferroelectric-based operation to charge-based operation, caused by the pinning effect due to the presence of different traps. This experimental study helps understand the role of charge trapping effects in switching characteristics of n- and p-chann...

Research paper thumbnail of Trap Capture and Emission Dynamics in Ferroelectric Field-Effect Transistors and their Impact on Device Operation and Reliability

2021 IEEE International Electron Devices Meeting (IEDM), 2021

We track carrier capture and emission dynamics during write operations in n-type ferroelectric-fi... more We track carrier capture and emission dynamics during write operations in n-type ferroelectric-field-effect transistors (FEFETs) by directly and separately measuring the trap related hole and electron currents through the body terminal and shorted source-drain, respectively. Both electron and hole currents are simultaneously observed during polarization switching, irrespective of whether the channel is in hole accumulation or electron inversion. This allows us to discover the exact mechanism of emission and capture of carriers, which leads to partial neutralization of the traps charged in the previous write cycle. With fatigue cycling, the neutralization of trapped charges progressively decreases, and the density of trap states increases leading to IGI_{G}IG, SS and peak gmg_{m}gm degradation. An increase in the effective time constant of trap states is also evident with cycling as a fatigued FEFET requires longer time to reach a given memory window after a write operation. We conclude that the memory window in FEFETs is facilitated by neutralization of traps, previously charged by carriers captured during FE switching (i. e., write operation) that screen the ferroelectric polarization. These emission and capture dynamics place the trap levels close to EcE_{c}Ec and EvE_{v}Ev and inside the SiO2 and at the SiO2/HZO interface, and currently hinders high-speed read-after-write in front-end FEFETs. The universality of the suggested mechanisms is confirmed in FEFETs fabricated in different facilities.

Research paper thumbnail of Unraveling the Dynamics of Charge Trapping and De-Trapping in Ferroelectric FETs

IEEE Transactions on Electron Devices, 2022

In this work, a comprehensive study of charge trapping and de-trapping dynamics is performed on n... more In this work, a comprehensive study of charge trapping and de-trapping dynamics is performed on n-channel ferroelectric field-effect transistors (nFeFETs) and pFeFETs. It is discovered that: 1) the degree of charge trapping depends on the substrate that nFeFETs exhibit significant electron trapping but negligible hole trapping during memory write while pFeFETs exhibit much less electron trapping but significant hole trapping when heavily stressed; 2) due to enhanced electric field in the interlayer and semiconductor, the like initial polarization states (i.e., initialized by a pulse of the same polarity as the write pulse) could exacerbate charge trapping induced by the write pulse; 3) electron trapping is fully recoverable while hole trapping shows a semi-permanent component which involves interface trap generation; and 4) less significant charge trapping in pFeFETs allows immediate read-after-write at normal operating conditions.

Research paper thumbnail of FeFET-Based Neuromorphic Architecture with On-Device Feedback Alignment Training

2020 21st International Symposium on Quality Electronic Design (ISQED), 2020

With the onset of on-device learning in neuromorphic systems, there are a requisition for compute... more With the onset of on-device learning in neuromorphic systems, there are a requisition for compute-lite learning rules and novel emerging devices that address the memory bottleneck. In this research, we propose a neuromorphic architecture with FeFET synapse arrays and study the efficacy of write schemes for feedback alignment backpropagation algorithm. The proposed architecture is benchmarked for two write programming schemes, sawtooth pulse and incremental pulse. The sawtooth write programming scheme is further simplified for resource efficient training, by sharing the pulse generator with local control circuitry across multiple neurons. When the overall architecture is benchmarked for on-device learning, we observed that both writing schemes result in comparable performance, but the sawtooth is more efficient in terms of power consumption and area.

Research paper thumbnail of Utilization of electroluminescence from avalanche p-n junctions for optical testing of silicon integrated circuits

Proceedings., Eighth University/Government/Industry Microelectronics Symposium

ABSTRACT

Research paper thumbnail of Development and characterization of 10 nm, N/sub 2/-implanted nitrided oxides for gate dielectrics

Proceedings of the Thirteenth Biennial University/Government/Industry Microelectronics Symposium (Cat. No.99CH36301)

ABSTRACT

Research paper thumbnail of AVT-RIT-NSF partnership for the development of low voltage thin film phosphor for field emission display devices

Proceedings of the Thirteenth Biennial University/Government/Industry Microelectronics Symposium (Cat. No.99CH36301)

... 6, No. 3, p. 181. 1998. [2] Philip D. Rack, Michael D. Potter, Andrew Woodard and Santosh Kur... more ... 6, No. 3, p. 181. 1998. [2] Philip D. Rack, Michael D. Potter, Andrew Woodard and Santosh Kurinec, “Negative Ion Re-sputtering in Ta2Zn308 Thin Films,” Materials Research Society National Spring Meeting, April 1999, E4.4. [3] G. Blasse, Structure and Bonding. ...

Research paper thumbnail of A new program at RIT: master of engineering in microelectronics manufacturing engineering

Proceedings., Eighth University/Government/Industry Microelectronics Symposium

Rochester Institute of Technology, College of Engineering, has established a new master of engine... more Rochester Institute of Technology, College of Engineering, has established a new master of engineering degree program in microelectronics manufacturing engineering. The program is one year (four quarters) in duration and is designed for BS graduates in engineering or science. The core courses are Microelectronics I, II, III, Microlithography I, II, and Manufacturing Science I, II. Concentration courses may be selected from a list of courses including computer integrated manufacturing, statistical design of experiments, facilities design, safety, and others. The core courses are discussed, and the facilities are described

Research paper thumbnail of Challenges in integration of Resonant Interband Tunnel Devices with CMOS

Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488), 2003

The fabrication of SiGe Resonant Interband Tunnel Devices (RITD) using CMOS compatible processes ... more The fabrication of SiGe Resonant Interband Tunnel Devices (RITD) using CMOS compatible processes requires ability to form RITD structures selectively on source/drain regions. Various approaches were investigated and RITDs have been realized in lithographically defined openings in oxide on Si wafers. Patterned growth RITD on p+ Si exhibited a peak-tovalley current ratio (PVCR) of 3.0 and peak current density (J p) of 188 A/cm 2 whereas RITD of p+ implanted regions resulted in a PVCR of 2.5 with J p of 278 A/cm 2. Blanked growth RITD on p+ implanted substrate yielded a superior PCVR of 3.3 and J p of 332 A/cm 2. The observed effects of patterned growth and implanted substrate on the RITD device performance are critical challenges addressed in this study for RITD-CMOS integration.

Research paper thumbnail of 25 Years of Microelectronic Engineering Education

2006 16th Biennial University/Government/Industry Microelectronics Symposium, 2006

Abstract-Rochester Institute of Technology started the nation's first Bachelor o... more Abstract-Rochester Institute of Technology started the nation's first Bachelor of Science program in Microelectronic Engineering in 1982. The program has kept pace with the rapid advancements in semiconductor technology, sharing 25 of the 40 years characterized by Moore's Law. ...

Research paper thumbnail of Microelectronics Manufacturing Education

Proceedings. IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop

ABSTRACT

Research paper thumbnail of K-12 teachers forum on microelectronics and nanotechnology

2007 International Semiconductor Device Research Symposium, 2007

ABSTRACT

Research paper thumbnail of Modeling the thermal behavior of chalcogenide based phase change memory cell

2007 International Semiconductor Device Research Symposium, 2007

The presented work, reports a 2D thermal model for a PCM cell employing stacked Ge-chalcogenide (... more The presented work, reports a 2D thermal model for a PCM cell employing stacked Ge-chalcogenide (Ge2Se3) and Sn-chalcogenide (SnSe) layers as phase change materials. The thermal behavior exhibited by the PCM cell upon melting of the Ge2Se3 layer is explored at the 130nm, 65nm and 45nm technology nodes. The suitability of doped polysilicon, TiN and TaSiNx as potential heater materials

Research paper thumbnail of Summer innovation experience for undergraduates in semiconductor technology

... Santosh Kurinec, Sean Rommel, Dale Ewbank and Karl Hirschman Rochester Institute of Technolog... more ... Santosh Kurinec, Sean Rommel, Dale Ewbank and Karl Hirschman Rochester Institute of Technology skkemc@rit.edu;slremc@rit.edu ... Based on the authors' experience with the NSF “Research Experience for Undergraduates (REU)” program, this pilot program “Summer ...

Research paper thumbnail of Modeling, simulation and verification of void transfer process for patterning nm scale features

2009 International Semiconductor Device Research Symposium, 2009

ABSTRACT

Research paper thumbnail of Blue cathodoluminescence from tantalum zinc oxide

Proceedings of the UGIM Symposium, Microelectronics Education for the Future. Twelfth Biennial University/Government/Industry Microelectronics Symposium (Cat. No.97CH36030), 1997

We have observed cathodoluminescence (CL) at low voltages (-60 V) with a peak at-410

Research paper thumbnail of Care and feeding of a university cleanroom facility

Proceedings., Eighth University/Government/Industry Microelectronics Symposium

The authors describe the systems that have been established for the operation of the microelectro... more The authors describe the systems that have been established for the operation of the microelectronics facility at the Rochester Institute of Technology. Attention is given to the organizational structure; support facilities; cleanroom maintenance; lab equipment; equipment operation; lab supplies, inventory, and control; lab safety; and the hazardous waste program

Research paper thumbnail of Residual Stress Analysis of Stacked SnTe/Ge2Se3 Phase Change Memory Films using Vantec 2000 Area Detector

... ψ 2 sin Acknowledgement The authors wish to thank Dr. Kris Campbell and her team for providin... more ... ψ 2 sin Acknowledgement The authors wish to thank Dr. Kris Campbell and her team for providing the as-deposited film stacks and Dr. Vinnie Gupta for his help in editing the paper and offering very important and insightful suggestions. ... 349-355, 2004. [7] S. Lai, “Current status ...

Research paper thumbnail of Teaching solar cell I-V characteristics using SPICE

American Journal of Physics, 2011

The basic equivalent circuit of a p-n junction solar cell is most commonly represented as consist... more The basic equivalent circuit of a p-n junction solar cell is most commonly represented as consisting of a current source in parallel with two diodes and two parasitic resistances. The output of a solar cell is measured by obtaining the current-voltage (I–V) characteristics for different illumination intensities, and various parameters are extracted from these characteristics. Because the nature of the information derived from these characteristics is not obvious to the beginning students in photovoltaics, a simulation using SPICE was utilized to explain three solar cell I–V characteristics—dark I–V, illuminated I–V, and open circuit voltage versus the short circuit current (illumination intensity). Students can construct a solar cell and study the effect of the diode and parasitic parameters on the three output I–V characteristics. Series and parallel combinations of solar cells for arrays and modules using bypass diodes are demonstrated using SPICE as educational tools for understa...

Research paper thumbnail of Monitoring a photovoltaic system during the partial solar eclipse of August 2017

EPJ Photovoltaics, 2018

The power output of a 4.85 kW residential photovoltaic (PV) system located in Rochester, NY is mo... more The power output of a 4.85 kW residential photovoltaic (PV) system located in Rochester, NY is monitored during the partial solar eclipse of August 21, 2017. The data is compared with the data on a day before and on the same day, a year ago. The area of exposed solar disk is measured using astrophotography every 16 s of the eclipse. Global solar irradiance is estimated using the eclipse shading, time of the day, location coordinates, atmospheric conditions and panel orientation. A sharp decline, as expected in the energy produced is observed at the time of the peak of the eclipse. The observed data of the PV energy produced is related with the model calculations taking into account solar eclipse coverage and cloudiness conditions. The paper provides a cohesive approach of irradiance calculations and obtaining anticipated PV performance.