Omid Kavehei | RMIT University (original) (raw)

Papers by Omid Kavehei

Research paper thumbnail of Epileptic Seizure Forecasting with Generative Adversarial Networks

IEEE Access, 2019

Many outstanding studies have reported promising results in seizure forecasting, one of the most ... more Many outstanding studies have reported promising results in seizure forecasting, one of the most challenging predictive data analysis problems. This is mainly because electroencephalogram (EEG) bio-signal intensity is very small, in µV range, and there are significant sensing difficulties given physiological and non-physiological artifacts. Today the process of accurate epileptic seizure identification and data labeling is done by neurologists. The current unpredictability of epileptic seizure activities together with the lack of reliable treatment for patients living with drug resistant forms of epilepsy creates an urgency for research into accurate, sensitive and patient-specific seizure forecasting. Most seizure forecasting algorithms use only labeled data for training purposes. As the seizure data is labeled manually by neurologists, preparing the labeled data is expensive and time consuming, making the best use of the data critical. In this article, we propose an approach that can make use of not only labeled EEG signals but also the unlabeled ones which are more accessible. We use the short-time Fourier transform on 28-s EEG windows as a pre-processing step. A generative adversarial network (GAN) is trained in an unsupervised manner where information of seizure onset is disregarded. The trained Discriminator of the GAN is then used as a feature extractor. Features generated by the feature extractor are classified by two fully-connected layers (can be replaced by any classifier) for the labeled EEG signals. This semi-supervised patient-specific seizure forecasting method achieves an out-of-sample testing area under the operating characteristic curve (AUC) of 77.68%, 75.47% and 65.05% for the CHB-MIT scalp EEG dataset, the Freiburg Hospital intracranial EEG dataset and the EPILEPSIAE dataset, respectively. Unsupervised training without the need for labeling is important because not only it can be performed in real-time during EEG signal recording, but also it does not require feature engineering effort for each patient. To the best of our knowledge, this is the first application of GAN to seizure forecasting.

Research paper thumbnail of Donor-Induced Performance Tuning of Amorphous SrTiO 3 Memristive Nanodevices: Multistate Resistive Switching and Mechanical Tunability

Advanced Functional Materials, 2015

ABSTRACT Metal–oxide valence-change memristive devices are the key contenders for the development... more ABSTRACT Metal–oxide valence-change memristive devices are the key contenders for the development of multilevel nonvolatile analog memories and neuromorphic computing architectures. Reliable low energy performance and tunability of nonlinear resistive switching dynamics are essential to streamline the high-density circuit level integration of these devices. Here, manipulation of room temperature-synthesized defect chemistry is employed to enhance and tune the switching characteristics of high-performance amorphous SrTiO3 (a-STO) memristors. Substitutional donor (Nb) doping with low concentrations in the a-STO oxide structure allows extensive improvements in energy requirements, stability, and controllability of the memristive performance, as well as field-dependent multistate resistive switching. Evidence is presented that room temperature donor doping results in a modified insulator oxide where dislocation sites act as charge carrier modulators for low energy and multilevel operation. Finally, the performance of donor-doped a-STO-based memristive nanodevices is showcased, with the possibility of mechanical modulation of the nonlinear memristive characteristics of these devices demonstrated. These results highlight the potential of donor-doped a-STO nanodevices for high-density integration as analog memories and multifunctional alternative logic elements.

Research paper thumbnail of Donor-Induced Performance Tuning of Amorphous SrTiO 3 Memristive Nanodevices: Multistate Resistive Switching and Mechanical Tunability

Advanced Functional Materials, 2015

ABSTRACT Metal–oxide valence-change memristive devices are the key contenders for the development... more ABSTRACT Metal–oxide valence-change memristive devices are the key contenders for the development of multilevel nonvolatile analog memories and neuromorphic computing architectures. Reliable low energy performance and tunability of nonlinear resistive switching dynamics are essential to streamline the high-density circuit level integration of these devices. Here, manipulation of room temperature-synthesized defect chemistry is employed to enhance and tune the switching characteristics of high-performance amorphous SrTiO3 (a-STO) memristors. Substitutional donor (Nb) doping with low concentrations in the a-STO oxide structure allows extensive improvements in energy requirements, stability, and controllability of the memristive performance, as well as field-dependent multistate resistive switching. Evidence is presented that room temperature donor doping results in a modified insulator oxide where dislocation sites act as charge carrier modulators for low energy and multilevel operation. Finally, the performance of donor-doped a-STO-based memristive nanodevices is showcased, with the possibility of mechanical modulation of the nonlinear memristive characteristics of these devices demonstrated. These results highlight the potential of donor-doped a-STO nanodevices for high-density integration as analog memories and multifunctional alternative logic elements.

Research paper thumbnail of Fabrication and modeling of Ag/TiO< inf> 2 /ITO memristor

Research paper thumbnail of High density and non-volatile CRS-based CAM

Research paper thumbnail of Memristive crypto primitive for building highly secure physical unclonable functions

Research paper thumbnail of Live demonstration: High fill factor CIS based on single inverter architecture

2012 IEEE International Symposium on Circuits and Systems, 2012

ABSTRACT This live demonstration presents a high fill factor 6 transistor per pixel CMOS image se... more ABSTRACT This live demonstration presents a high fill factor 6 transistor per pixel CMOS image sensor (CIS) based on a single inverter that modulates light illumination to pulse width supporting ultra low supply voltage requirements. It has a compact readout circuitry for pulse-based signal processing without A/D converter at the output. A 64 × 64 pixel array was fabricated using 130 nm CMOS technology. The chip operated under a +VDD as low as 500 mV with power consumption of only 27 nW per pixel. The fill factor is 58%, which is significantly larger than those conventional CMOS imagers.

Research paper thumbnail of Guest Editorial Solid-state Memristive Devices and Systems

IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2015

ABSTRACT The articles in this special section present some of the latest developments in the fiel... more ABSTRACT The articles in this special section present some of the latest developments in the field of solid-state memristive devices and systems. The papers cover different aspects of practical memristive devices and systems, including solid-state nanodevices, physical switching mechanisms, circuits and emerging applications.

Research paper thumbnail of A charge-balanced 4-wire interface for the interconnections of biomedical implants

2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2013

Research paper thumbnail of Pattern matching and classification based on an associative memory architecture using CRS

2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, 2012

Research paper thumbnail of Fabrication and modeling of Ag/TiO<inf>2</inf>/ITO memristor

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011

Research paper thumbnail of Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation

2009 IEEE Computer Society Annual Symposium on VLSI, 2009

Redundant Number Systems have been widely used in fast arithmetic circuits design. Signed-Digit (... more Redundant Number Systems have been widely used in fast arithmetic circuits design. Signed-Digit (SD) or generally High-Radix SD (HRSD) number system is one of the most important redundant number systems. HRSD additions are used in many arithmetic functions as ...

Research paper thumbnail of A Complete and Highly Flexible 256-Electrode Retinal Prosthesis Chip

Research paper thumbnail of Highly Scalable Neuromorphic Hardware with 1-bit Stochastic nano-Synapses

Research paper thumbnail of Novel VLSI implementation for triplet-based spike-timing dependent plasticity

Research paper thumbnail of Nanosession: Logic Devices and Circuit Design

A Collection of Extended Abstracts of the Nature Conference Frontiers in Electronic Materials, June 17 th to 20 th 2012, Aachen, Germany, 2012

Research paper thumbnail of Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design

2008 IEEE Computer Society Annual Symposium on VLSI, 2008

Research paper thumbnail of <title>High-performance bridge-style full adder structure</title>

Smart Structures, Devices, and Systems IV, 2008

Research paper thumbnail of Multiprotocol-induced plasticity in artificial synapses

Research paper thumbnail of Live demonstration: An associative capacitive network based on nanoscale complementary resistive switches

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014

ABSTRACT Integration density is a major drawback of today&#39;s associative memories required... more ABSTRACT Integration density is a major drawback of today&#39;s associative memories required for intelligent data processing for such as pattern recognition or classification. Ultra dense complementary resistive switch-based architectures are thought to overcome this issue, offering a footprint of 4F2. Here we demonstrate the feasibility of an 8 by 16 associative capacitive network.

Research paper thumbnail of Epileptic Seizure Forecasting with Generative Adversarial Networks

IEEE Access, 2019

Many outstanding studies have reported promising results in seizure forecasting, one of the most ... more Many outstanding studies have reported promising results in seizure forecasting, one of the most challenging predictive data analysis problems. This is mainly because electroencephalogram (EEG) bio-signal intensity is very small, in µV range, and there are significant sensing difficulties given physiological and non-physiological artifacts. Today the process of accurate epileptic seizure identification and data labeling is done by neurologists. The current unpredictability of epileptic seizure activities together with the lack of reliable treatment for patients living with drug resistant forms of epilepsy creates an urgency for research into accurate, sensitive and patient-specific seizure forecasting. Most seizure forecasting algorithms use only labeled data for training purposes. As the seizure data is labeled manually by neurologists, preparing the labeled data is expensive and time consuming, making the best use of the data critical. In this article, we propose an approach that can make use of not only labeled EEG signals but also the unlabeled ones which are more accessible. We use the short-time Fourier transform on 28-s EEG windows as a pre-processing step. A generative adversarial network (GAN) is trained in an unsupervised manner where information of seizure onset is disregarded. The trained Discriminator of the GAN is then used as a feature extractor. Features generated by the feature extractor are classified by two fully-connected layers (can be replaced by any classifier) for the labeled EEG signals. This semi-supervised patient-specific seizure forecasting method achieves an out-of-sample testing area under the operating characteristic curve (AUC) of 77.68%, 75.47% and 65.05% for the CHB-MIT scalp EEG dataset, the Freiburg Hospital intracranial EEG dataset and the EPILEPSIAE dataset, respectively. Unsupervised training without the need for labeling is important because not only it can be performed in real-time during EEG signal recording, but also it does not require feature engineering effort for each patient. To the best of our knowledge, this is the first application of GAN to seizure forecasting.

Research paper thumbnail of Donor-Induced Performance Tuning of Amorphous SrTiO 3 Memristive Nanodevices: Multistate Resistive Switching and Mechanical Tunability

Advanced Functional Materials, 2015

ABSTRACT Metal–oxide valence-change memristive devices are the key contenders for the development... more ABSTRACT Metal–oxide valence-change memristive devices are the key contenders for the development of multilevel nonvolatile analog memories and neuromorphic computing architectures. Reliable low energy performance and tunability of nonlinear resistive switching dynamics are essential to streamline the high-density circuit level integration of these devices. Here, manipulation of room temperature-synthesized defect chemistry is employed to enhance and tune the switching characteristics of high-performance amorphous SrTiO3 (a-STO) memristors. Substitutional donor (Nb) doping with low concentrations in the a-STO oxide structure allows extensive improvements in energy requirements, stability, and controllability of the memristive performance, as well as field-dependent multistate resistive switching. Evidence is presented that room temperature donor doping results in a modified insulator oxide where dislocation sites act as charge carrier modulators for low energy and multilevel operation. Finally, the performance of donor-doped a-STO-based memristive nanodevices is showcased, with the possibility of mechanical modulation of the nonlinear memristive characteristics of these devices demonstrated. These results highlight the potential of donor-doped a-STO nanodevices for high-density integration as analog memories and multifunctional alternative logic elements.

Research paper thumbnail of Donor-Induced Performance Tuning of Amorphous SrTiO 3 Memristive Nanodevices: Multistate Resistive Switching and Mechanical Tunability

Advanced Functional Materials, 2015

ABSTRACT Metal–oxide valence-change memristive devices are the key contenders for the development... more ABSTRACT Metal–oxide valence-change memristive devices are the key contenders for the development of multilevel nonvolatile analog memories and neuromorphic computing architectures. Reliable low energy performance and tunability of nonlinear resistive switching dynamics are essential to streamline the high-density circuit level integration of these devices. Here, manipulation of room temperature-synthesized defect chemistry is employed to enhance and tune the switching characteristics of high-performance amorphous SrTiO3 (a-STO) memristors. Substitutional donor (Nb) doping with low concentrations in the a-STO oxide structure allows extensive improvements in energy requirements, stability, and controllability of the memristive performance, as well as field-dependent multistate resistive switching. Evidence is presented that room temperature donor doping results in a modified insulator oxide where dislocation sites act as charge carrier modulators for low energy and multilevel operation. Finally, the performance of donor-doped a-STO-based memristive nanodevices is showcased, with the possibility of mechanical modulation of the nonlinear memristive characteristics of these devices demonstrated. These results highlight the potential of donor-doped a-STO nanodevices for high-density integration as analog memories and multifunctional alternative logic elements.

Research paper thumbnail of Fabrication and modeling of Ag/TiO< inf> 2 /ITO memristor

Research paper thumbnail of High density and non-volatile CRS-based CAM

Research paper thumbnail of Memristive crypto primitive for building highly secure physical unclonable functions

Research paper thumbnail of Live demonstration: High fill factor CIS based on single inverter architecture

2012 IEEE International Symposium on Circuits and Systems, 2012

ABSTRACT This live demonstration presents a high fill factor 6 transistor per pixel CMOS image se... more ABSTRACT This live demonstration presents a high fill factor 6 transistor per pixel CMOS image sensor (CIS) based on a single inverter that modulates light illumination to pulse width supporting ultra low supply voltage requirements. It has a compact readout circuitry for pulse-based signal processing without A/D converter at the output. A 64 × 64 pixel array was fabricated using 130 nm CMOS technology. The chip operated under a +VDD as low as 500 mV with power consumption of only 27 nW per pixel. The fill factor is 58%, which is significantly larger than those conventional CMOS imagers.

Research paper thumbnail of Guest Editorial Solid-state Memristive Devices and Systems

IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2015

ABSTRACT The articles in this special section present some of the latest developments in the fiel... more ABSTRACT The articles in this special section present some of the latest developments in the field of solid-state memristive devices and systems. The papers cover different aspects of practical memristive devices and systems, including solid-state nanodevices, physical switching mechanisms, circuits and emerging applications.

Research paper thumbnail of A charge-balanced 4-wire interface for the interconnections of biomedical implants

2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2013

Research paper thumbnail of Pattern matching and classification based on an associative memory architecture using CRS

2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, 2012

Research paper thumbnail of Fabrication and modeling of Ag/TiO<inf>2</inf>/ITO memristor

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011

Research paper thumbnail of Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation

2009 IEEE Computer Society Annual Symposium on VLSI, 2009

Redundant Number Systems have been widely used in fast arithmetic circuits design. Signed-Digit (... more Redundant Number Systems have been widely used in fast arithmetic circuits design. Signed-Digit (SD) or generally High-Radix SD (HRSD) number system is one of the most important redundant number systems. HRSD additions are used in many arithmetic functions as ...

Research paper thumbnail of A Complete and Highly Flexible 256-Electrode Retinal Prosthesis Chip

Research paper thumbnail of Highly Scalable Neuromorphic Hardware with 1-bit Stochastic nano-Synapses

Research paper thumbnail of Novel VLSI implementation for triplet-based spike-timing dependent plasticity

Research paper thumbnail of Nanosession: Logic Devices and Circuit Design

A Collection of Extended Abstracts of the Nature Conference Frontiers in Electronic Materials, June 17 th to 20 th 2012, Aachen, Germany, 2012

Research paper thumbnail of Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design

2008 IEEE Computer Society Annual Symposium on VLSI, 2008

Research paper thumbnail of <title>High-performance bridge-style full adder structure</title>

Smart Structures, Devices, and Systems IV, 2008

Research paper thumbnail of Multiprotocol-induced plasticity in artificial synapses

Research paper thumbnail of Live demonstration: An associative capacitive network based on nanoscale complementary resistive switches

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014

ABSTRACT Integration density is a major drawback of today&#39;s associative memories required... more ABSTRACT Integration density is a major drawback of today&#39;s associative memories required for intelligent data processing for such as pattern recognition or classification. Ultra dense complementary resistive switch-based architectures are thought to overcome this issue, offering a footprint of 4F2. Here we demonstrate the feasibility of an 8 by 16 associative capacitive network.

Research paper thumbnail of A Physical Unclonable Function with Redox-based Nanoionic Resistive Memory

A unique set of characteristics are packed in emerging nonvolatile reduction-oxidation (redox)-ba... more A unique set of characteristics are packed in emerging nonvolatile reduction-oxidation (redox)-based resistive switching memories (ReRAMs) such as their underlying stochastic switching processes alongside their intrinsic highly nonlinear current-voltage characteristic, which in addition to known nanofabrication process variation make them a promising candidate for the next generation of low-cost, low-power, tiny and secure Physically Unclonable Functions (PUFs). This paper takes advantage of this otherwise disadvantageous ReRAM feature using a combination of novel architectural and peripheral circuitry. We present a physical one-way function, nonlinear resistive Physical Unclonable Function (nrPUF), potentially applicable in variety of cyber-physical security applications given its performance characteristics. We experimentally verified performance of Valency Change Mechanism (VCM)-based ReRAM in nano-fabricated crossbar arrays across multiple dies and runs. In addition to a massive pool of Challenge-Response Pairs (CRPs), using a combination of experimental and simulation, our proposed PUF shows a reliability of 98.67%, a uniqueness of 49.85%, a diffuseness of 49.86%, a uniformity of 47.28%, and a bit-aliasing of 47.48%. Index Terms—Physical unclonable function, resistive random access memory, emerging nonvolatile memory.