Omid Kavehei - Profile on Academia.edu (original) (raw)

Papers by Omid Kavehei

IEEE Access, 2019

Many outstanding studies have reported promising results in seizure forecasting, one of the most ... more Many outstanding studies have reported promising results in seizure forecasting, one of the most challenging predictive data analysis problems. This is mainly because electroencephalogram (EEG) bio-signal intensity is very small, in µV range, and there are significant sensing difficulties given physiological and non-physiological artifacts. Today the process of accurate epileptic seizure identification and data labeling is done by neurologists. The current unpredictability of epileptic seizure activities together with the lack of reliable treatment for patients living with drug resistant forms of epilepsy creates an urgency for research into accurate, sensitive and patient-specific seizure forecasting. Most seizure forecasting algorithms use only labeled data for training purposes. As the seizure data is labeled manually by neurologists, preparing the labeled data is expensive and time consuming, making the best use of the data critical. In this article, we propose an approach that can make use of not only labeled EEG signals but also the unlabeled ones which are more accessible. We use the short-time Fourier transform on 28-s EEG windows as a pre-processing step. A generative adversarial network (GAN) is trained in an unsupervised manner where information of seizure onset is disregarded. The trained Discriminator of the GAN is then used as a feature extractor. Features generated by the feature extractor are classified by two fully-connected layers (can be replaced by any classifier) for the labeled EEG signals. This semi-supervised patient-specific seizure forecasting method achieves an out-of-sample testing area under the operating characteristic curve (AUC) of 77.68%, 75.47% and 65.05% for the CHB-MIT scalp EEG dataset, the Freiburg Hospital intracranial EEG dataset and the EPILEPSIAE dataset, respectively. Unsupervised training without the need for labeling is important because not only it can be performed in real-time during EEG signal recording, but also it does not require feature engineering effort for each patient. To the best of our knowledge, this is the first application of GAN to seizure forecasting.

Donor-Induced Performance Tuning of Amorphous SrTiO 3 Memristive Nanodevices: Multistate Resistive Switching and Mechanical Tunability

Advanced Functional Materials, 2015

ABSTRACT Metal–oxide valence-change memristive devices are the key contenders for the development... more ABSTRACT Metal–oxide valence-change memristive devices are the key contenders for the development of multilevel nonvolatile analog memories and neuromorphic computing architectures. Reliable low energy performance and tunability of nonlinear resistive switching dynamics are essential to streamline the high-density circuit level integration of these devices. Here, manipulation of room temperature-synthesized defect chemistry is employed to enhance and tune the switching characteristics of high-performance amorphous SrTiO3 (a-STO) memristors. Substitutional donor (Nb) doping with low concentrations in the a-STO oxide structure allows extensive improvements in energy requirements, stability, and controllability of the memristive performance, as well as field-dependent multistate resistive switching. Evidence is presented that room temperature donor doping results in a modified insulator oxide where dislocation sites act as charge carrier modulators for low energy and multilevel operation. Finally, the performance of donor-doped a-STO-based memristive nanodevices is showcased, with the possibility of mechanical modulation of the nonlinear memristive characteristics of these devices demonstrated. These results highlight the potential of donor-doped a-STO nanodevices for high-density integration as analog memories and multifunctional alternative logic elements.

Donor-Induced Performance Tuning of Amorphous SrTiO 3 Memristive Nanodevices: Multistate Resistive Switching and Mechanical Tunability

Advanced Functional Materials, 2015

ABSTRACT Metal–oxide valence-change memristive devices are the key contenders for the development... more ABSTRACT Metal–oxide valence-change memristive devices are the key contenders for the development of multilevel nonvolatile analog memories and neuromorphic computing architectures. Reliable low energy performance and tunability of nonlinear resistive switching dynamics are essential to streamline the high-density circuit level integration of these devices. Here, manipulation of room temperature-synthesized defect chemistry is employed to enhance and tune the switching characteristics of high-performance amorphous SrTiO3 (a-STO) memristors. Substitutional donor (Nb) doping with low concentrations in the a-STO oxide structure allows extensive improvements in energy requirements, stability, and controllability of the memristive performance, as well as field-dependent multistate resistive switching. Evidence is presented that room temperature donor doping results in a modified insulator oxide where dislocation sites act as charge carrier modulators for low energy and multilevel operation. Finally, the performance of donor-doped a-STO-based memristive nanodevices is showcased, with the possibility of mechanical modulation of the nonlinear memristive characteristics of these devices demonstrated. These results highlight the potential of donor-doped a-STO nanodevices for high-density integration as analog memories and multifunctional alternative logic elements.

The nanometer scale feature of memristor created a broad range of opportunities for innovative ar... more The nanometer scale feature of memristor created a broad range of opportunities for innovative architectures. The nature of the boundary conditions, the complexity of the ionic transport and tunneling mechanism, and the nanoscale feature of the memristor introduces new challenges in model ing, characterization, and measurements for Memristor-MOS (M 2 ) circuits. These new challenges can be addressed by a joint insight from the circuit designer and device engineers, which will dictate the needed modeling and layout rules to attain an accurate estimation of M 2 circuit performance. In this paper, memristive behavior of titanium dioxide (Ti0 2 ) is studied using a novel combination of electrodes, silver (Ag) and indium thin oxide (ITO). Fabrication method and a modeling approach are also explained. The ITO electrode provide (a) an excellent transparency in visible light, (b) improved functional reproducibility, and (c) non-volatile characteristics as well as a promising unique application of the M 2 circuits in sensory applications. Furthermore, proposed modeling approach shows a good agreement between measurements and simulations of analog memory characteristics and reproducibility as well as long-term retention.

This paper presents a novel resistive-only Binary and Ternary Content Addressable Memory (B/TCAM)... more This paper presents a novel resistive-only Binary and Ternary Content Addressable Memory (B/TCAM) cell that consists of two Complementary Resistive Switches (CRSs). The operation of such a cell relies on a logic→ON state transition that enables this novel CRS application.

Scientific Reports, 2015

Physical unclonable functions (PUFs) exploit the intrinsic complexity and irreproducibility of ph... more Physical unclonable functions (PUFs) exploit the intrinsic complexity and irreproducibility of physical systems to generate secret information. The advantage is that PUFs have the potential to provide fundamentally higher security than traditional cryptographic methods by preventing the cloning of devices and the extraction of secret keys. Most PUF designs focus on exploiting process variations in Complementary Metal Oxide Semiconductor (CMOS) technology. In recent years, progress in nanoelectronic devices such as memristors has demonstrated the prevalence of process variations in scaling electronics down to the nano region. In this paper, we exploit the extremely large information density available in nanocrossbar architectures and the significant resistance variations of memristors to develop an on-chip memristive device based strong PUF (mrSPUF). Our novel architecture demonstrates desirable characteristics of PUFs, including uniqueness, reliability, and large number of challenge-response pairs (CRPs) and desirable characteristics of strong PUFs. More significantly, in contrast to most existing PUFs, our PUF can act as a reconfigurable PUF (rPUF) without additional hardware and is of benefit to applications needing revocation or update of secure key information.

Live demonstration: High fill factor CIS based on single inverter architecture

2012 IEEE International Symposium on Circuits and Systems, 2012

ABSTRACT This live demonstration presents a high fill factor 6 transistor per pixel CMOS image se... more ABSTRACT This live demonstration presents a high fill factor 6 transistor per pixel CMOS image sensor (CIS) based on a single inverter that modulates light illumination to pulse width supporting ultra low supply voltage requirements. It has a compact readout circuitry for pulse-based signal processing without A/D converter at the output. A 64 × 64 pixel array was fabricated using 130 nm CMOS technology. The chip operated under a +VDD as low as 500 mV with power consumption of only 27 nW per pixel. The fill factor is 58%, which is significantly larger than those conventional CMOS imagers.

Guest Editorial Solid-state Memristive Devices and Systems

IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2015

ABSTRACT The articles in this special section present some of the latest developments in the fiel... more ABSTRACT The articles in this special section present some of the latest developments in the field of solid-state memristive devices and systems. The papers cover different aspects of practical memristive devices and systems, including solid-state nanodevices, physical switching mechanisms, circuits and emerging applications.

A charge-balanced 4-wire interface for the interconnections of biomedical implants

2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2013

2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, 2012

Emergence of new materials and in particular the recent progress in Memristor and related memory ... more Emergence of new materials and in particular the recent progress in Memristor and related memory technologies encouraged the research community for a renewed approach towards formulation of architectures such as those that depend upon associate memory constructs to take the advantages being offered within this new design domain. In this paper we address a key issue in pattern matching and classification process and hence suggest an alternative approach for image vector matching combining Complementary Resistive Switch (CRS) array and bump circuits. We emulated an experimental pattern matching with two approaches which are based on Hamming distance and threshold level of the image: the former finds an exact image with a bump circuit and the later finds similar patterns from the stored images combining comparators. The proposed hardware oriented architecture is high speed and smaller size that is easier to implement on conventional CMOS technology.

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011

The nanometer scale feature of memristor created a broad range of opportunities for innovative ar... more The nanometer scale feature of memristor created a broad range of opportunities for innovative architectures. The nature of the boundary conditions, the complexity of the ionic transport and tunneling mechanism, and the nanoscale feature of the memristor introduces new challenges in model ing, characterization, and measurements for Memristor-MOS (M 2 ) circuits. These new challenges can be addressed by a joint insight from the circuit designer and device engineers, which will dictate the needed modeling and layout rules to attain an accurate estimation of M 2 circuit performance. In this paper, memristive behavior of titanium dioxide (Ti0 2 ) is studied using a novel combination of electrodes, silver (Ag) and indium thin oxide (ITO). Fabrication method and a modeling approach are also explained. The ITO electrode provide (a) an excellent transparency in visible light, (b) improved functional reproducibility, and (c) non-volatile characteristics as well as a promising unique application of the M 2 circuits in sensory applications. Furthermore, proposed modeling approach shows a good agreement between measurements and simulations of analog memory characteristics and reproducibility as well as long-term retention.

Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation

2009 IEEE Computer Society Annual Symposium on VLSI, 2009

Redundant Number Systems have been widely used in fast arithmetic circuits design. Signed-Digit (... more Redundant Number Systems have been widely used in fast arithmetic circuits design. Signed-Digit (SD) or generally High-Radix SD (HRSD) number system is one of the most important redundant number systems. HRSD additions are used in many arithmetic functions as ...

A Complete and Highly Flexible 256-Electrode Retinal Prosthesis Chip

Thermodynamic-driven filament formation in redox-based resistive memory and the impact of thermal... more Thermodynamic-driven filament formation in redox-based resistive memory and the impact of thermal fluctuations on switching probability of emerging magnetic switches are probabilistic phenomena in nature, and thus, processes of binary switching in these nonvolatile memories are stochastic and vary from switching cycle-to-switching cycle, in the same device, and from device-to-device, hence, they provide a rich in-situ spatiotemporal stochastic characteristic. This work presents a highly scalable neuromorphic hardware based on crossbar array of 1-bit resistive crosspoints as distributed stochastic synapses. The network shows a robust performance in emulating selectivity of synaptic potentials in neurons of primary visual cortex to the orientation of a visual image. The proposed model could be configured to accept a wide range of nanodevices.

Spike Timing-Dependent Plasticity (STDP) is one of several plasticity rules that is believed to p... more Spike Timing-Dependent Plasticity (STDP) is one of several plasticity rules that is believed to play an important role in learning and memory in the brain. In conventional pairbased STDP learning, synaptic weights are altered by utilizing the temporal difference between pairs of pre-and post-synaptic spikes. This learning rule, however, fails to reproduce reported experimental measurements when using stimuli either by patterns consisting of triplet or quadruplet of spikes or increasing the repetition frequency of pairs of spikes. Significantly, a previously described spike triplet-based STDP rule succeeds in reproducing all of these experimental observations. In this paper, we present a new spike triplet-based VLSI implementation, that is based on a previous pair-based STDP circuit [1]. This implementation can reproduce similar results to those observed in various physiological STDP experiments, in contrast to traditional pairbased VLSI implementation. Simulation results using standard 0.35 µm CMOS process of the new circuit are presented and compared to published experimental data .

Nanosession: Logic Devices and Circuit Design

A Collection of Extended Abstracts of the Nature Conference Frontiers in Electronic Materials, June 17 th to 20 th 2012, Aachen, Germany, 2012

2008 IEEE Computer Society Annual Symposium on VLSI, 2008

Full-adders are the core element of the complex arithmetic circuits like addition, multiplication... more Full-adders are the core element of the complex arithmetic circuits like addition, multiplication, division and exponentiation. Regarding to this importance, new idea and investigations for constructing full-adders are required. As far as related literature is concerned, generality and ease of use, as well as voltage and transistor scaling are considerable advantages of CMOS logic design versus other design style such as CPL specially when cell-based design are targeted. This paper proposes a novel, symmetric and efficient design for a CMOS 1-bit full-adder. Besides, another fully symmetric full-adder has been presented. Results and simulations demonstrate that the proposed design leads to an efficient full-adder in terms of power consumption, delay and area in comparison to a well-known conventional full-adder design. The postlayout simulations have been done by HSPICE with nanometer scale transistors considering all parasitic capacitors and resistors.

Smart Structures, Devices, and Systems IV, 2008

Adders are the core element in arithmetic circuits like subtracters, multipliers, and dividers. O... more Adders are the core element in arithmetic circuits like subtracters, multipliers, and dividers. Optimization of adders can be achieved at device, circuit, architectural, and algorithmic levels. In this paper we present a new optimize full adder circuit structure that provides an improved performance compared to standard and mirror types adder structures. The performance of this adder in terms of power, delay, energy, and yield are investigated. This paper also proposes a novel simulation setup for full adder cells that is suitable for analyzing full adder cells at the high frequency. The simulation results of this structure will take into account the process variations for a 90 nm CMOS process and present results based on post-layout simulation using Cadence and Synopsys tools.

Nanoscale, 2014

We suggest a 'universal' electrical circuit for the realization of an artificial synapse that exh... more We suggest a 'universal' electrical circuit for the realization of an artificial synapse that exhibits longterm plasticity induced by different protocols. The long-term plasticity of the artificial synapse is basically attributed to the nonvolatile resistance change of the bipolar resistive switch in the circuit. The synaptic behaviour realized by the circuit is termed 'universal' inasmuch as (i) the shape of the action potential is not required to vary so as to implement different plasticity-induction behaviours, activity-dependent plasticity (ADP) and spike-timing-dependent plasticity (STDP), (ii) the behaviours satisfy several essential features of a biological chemical synapse including firing-rate and spike-timing encoding and unidirectional synaptic transmission, and (iii) both excitatory and inhibitory synapses can be realized using the same circuit but different diode polarity in the circuit. The feasibility of the suggested circuit as an artificial synapse is demonstrated by conducting circuit calculations and the calculation results are introduced in comparison with biological chemical synapses. † Electronic supplementary information (ESI) available. See

Live demonstration: An associative capacitive network based on nanoscale complementary resistive switches

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014

ABSTRACT Integration density is a major drawback of today's associative memories required... more ABSTRACT Integration density is a major drawback of today's associative memories required for intelligent data processing for such as pattern recognition or classification. Ultra dense complementary resistive switch-based architectures are thought to overcome this issue, offering a footprint of 4F2. Here we demonstrate the feasibility of an 8 by 16 associative capacitive network.

IEEE Access, 2019

Many outstanding studies have reported promising results in seizure forecasting, one of the most ... more Many outstanding studies have reported promising results in seizure forecasting, one of the most challenging predictive data analysis problems. This is mainly because electroencephalogram (EEG) bio-signal intensity is very small, in µV range, and there are significant sensing difficulties given physiological and non-physiological artifacts. Today the process of accurate epileptic seizure identification and data labeling is done by neurologists. The current unpredictability of epileptic seizure activities together with the lack of reliable treatment for patients living with drug resistant forms of epilepsy creates an urgency for research into accurate, sensitive and patient-specific seizure forecasting. Most seizure forecasting algorithms use only labeled data for training purposes. As the seizure data is labeled manually by neurologists, preparing the labeled data is expensive and time consuming, making the best use of the data critical. In this article, we propose an approach that can make use of not only labeled EEG signals but also the unlabeled ones which are more accessible. We use the short-time Fourier transform on 28-s EEG windows as a pre-processing step. A generative adversarial network (GAN) is trained in an unsupervised manner where information of seizure onset is disregarded. The trained Discriminator of the GAN is then used as a feature extractor. Features generated by the feature extractor are classified by two fully-connected layers (can be replaced by any classifier) for the labeled EEG signals. This semi-supervised patient-specific seizure forecasting method achieves an out-of-sample testing area under the operating characteristic curve (AUC) of 77.68%, 75.47% and 65.05% for the CHB-MIT scalp EEG dataset, the Freiburg Hospital intracranial EEG dataset and the EPILEPSIAE dataset, respectively. Unsupervised training without the need for labeling is important because not only it can be performed in real-time during EEG signal recording, but also it does not require feature engineering effort for each patient. To the best of our knowledge, this is the first application of GAN to seizure forecasting.

Donor-Induced Performance Tuning of Amorphous SrTiO 3 Memristive Nanodevices: Multistate Resistive Switching and Mechanical Tunability

Advanced Functional Materials, 2015

ABSTRACT Metal–oxide valence-change memristive devices are the key contenders for the development... more ABSTRACT Metal–oxide valence-change memristive devices are the key contenders for the development of multilevel nonvolatile analog memories and neuromorphic computing architectures. Reliable low energy performance and tunability of nonlinear resistive switching dynamics are essential to streamline the high-density circuit level integration of these devices. Here, manipulation of room temperature-synthesized defect chemistry is employed to enhance and tune the switching characteristics of high-performance amorphous SrTiO3 (a-STO) memristors. Substitutional donor (Nb) doping with low concentrations in the a-STO oxide structure allows extensive improvements in energy requirements, stability, and controllability of the memristive performance, as well as field-dependent multistate resistive switching. Evidence is presented that room temperature donor doping results in a modified insulator oxide where dislocation sites act as charge carrier modulators for low energy and multilevel operation. Finally, the performance of donor-doped a-STO-based memristive nanodevices is showcased, with the possibility of mechanical modulation of the nonlinear memristive characteristics of these devices demonstrated. These results highlight the potential of donor-doped a-STO nanodevices for high-density integration as analog memories and multifunctional alternative logic elements.

Donor-Induced Performance Tuning of Amorphous SrTiO 3 Memristive Nanodevices: Multistate Resistive Switching and Mechanical Tunability

Advanced Functional Materials, 2015

ABSTRACT Metal–oxide valence-change memristive devices are the key contenders for the development... more ABSTRACT Metal–oxide valence-change memristive devices are the key contenders for the development of multilevel nonvolatile analog memories and neuromorphic computing architectures. Reliable low energy performance and tunability of nonlinear resistive switching dynamics are essential to streamline the high-density circuit level integration of these devices. Here, manipulation of room temperature-synthesized defect chemistry is employed to enhance and tune the switching characteristics of high-performance amorphous SrTiO3 (a-STO) memristors. Substitutional donor (Nb) doping with low concentrations in the a-STO oxide structure allows extensive improvements in energy requirements, stability, and controllability of the memristive performance, as well as field-dependent multistate resistive switching. Evidence is presented that room temperature donor doping results in a modified insulator oxide where dislocation sites act as charge carrier modulators for low energy and multilevel operation. Finally, the performance of donor-doped a-STO-based memristive nanodevices is showcased, with the possibility of mechanical modulation of the nonlinear memristive characteristics of these devices demonstrated. These results highlight the potential of donor-doped a-STO nanodevices for high-density integration as analog memories and multifunctional alternative logic elements.

The nanometer scale feature of memristor created a broad range of opportunities for innovative ar... more The nanometer scale feature of memristor created a broad range of opportunities for innovative architectures. The nature of the boundary conditions, the complexity of the ionic transport and tunneling mechanism, and the nanoscale feature of the memristor introduces new challenges in model ing, characterization, and measurements for Memristor-MOS (M 2 ) circuits. These new challenges can be addressed by a joint insight from the circuit designer and device engineers, which will dictate the needed modeling and layout rules to attain an accurate estimation of M 2 circuit performance. In this paper, memristive behavior of titanium dioxide (Ti0 2 ) is studied using a novel combination of electrodes, silver (Ag) and indium thin oxide (ITO). Fabrication method and a modeling approach are also explained. The ITO electrode provide (a) an excellent transparency in visible light, (b) improved functional reproducibility, and (c) non-volatile characteristics as well as a promising unique application of the M 2 circuits in sensory applications. Furthermore, proposed modeling approach shows a good agreement between measurements and simulations of analog memory characteristics and reproducibility as well as long-term retention.

This paper presents a novel resistive-only Binary and Ternary Content Addressable Memory (B/TCAM)... more This paper presents a novel resistive-only Binary and Ternary Content Addressable Memory (B/TCAM) cell that consists of two Complementary Resistive Switches (CRSs). The operation of such a cell relies on a logic→ON state transition that enables this novel CRS application.

Scientific Reports, 2015

Physical unclonable functions (PUFs) exploit the intrinsic complexity and irreproducibility of ph... more Physical unclonable functions (PUFs) exploit the intrinsic complexity and irreproducibility of physical systems to generate secret information. The advantage is that PUFs have the potential to provide fundamentally higher security than traditional cryptographic methods by preventing the cloning of devices and the extraction of secret keys. Most PUF designs focus on exploiting process variations in Complementary Metal Oxide Semiconductor (CMOS) technology. In recent years, progress in nanoelectronic devices such as memristors has demonstrated the prevalence of process variations in scaling electronics down to the nano region. In this paper, we exploit the extremely large information density available in nanocrossbar architectures and the significant resistance variations of memristors to develop an on-chip memristive device based strong PUF (mrSPUF). Our novel architecture demonstrates desirable characteristics of PUFs, including uniqueness, reliability, and large number of challenge-response pairs (CRPs) and desirable characteristics of strong PUFs. More significantly, in contrast to most existing PUFs, our PUF can act as a reconfigurable PUF (rPUF) without additional hardware and is of benefit to applications needing revocation or update of secure key information.

Live demonstration: High fill factor CIS based on single inverter architecture

2012 IEEE International Symposium on Circuits and Systems, 2012

ABSTRACT This live demonstration presents a high fill factor 6 transistor per pixel CMOS image se... more ABSTRACT This live demonstration presents a high fill factor 6 transistor per pixel CMOS image sensor (CIS) based on a single inverter that modulates light illumination to pulse width supporting ultra low supply voltage requirements. It has a compact readout circuitry for pulse-based signal processing without A/D converter at the output. A 64 × 64 pixel array was fabricated using 130 nm CMOS technology. The chip operated under a +VDD as low as 500 mV with power consumption of only 27 nW per pixel. The fill factor is 58%, which is significantly larger than those conventional CMOS imagers.

Guest Editorial Solid-state Memristive Devices and Systems

IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2015

ABSTRACT The articles in this special section present some of the latest developments in the fiel... more ABSTRACT The articles in this special section present some of the latest developments in the field of solid-state memristive devices and systems. The papers cover different aspects of practical memristive devices and systems, including solid-state nanodevices, physical switching mechanisms, circuits and emerging applications.

A charge-balanced 4-wire interface for the interconnections of biomedical implants

2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2013

2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, 2012

Emergence of new materials and in particular the recent progress in Memristor and related memory ... more Emergence of new materials and in particular the recent progress in Memristor and related memory technologies encouraged the research community for a renewed approach towards formulation of architectures such as those that depend upon associate memory constructs to take the advantages being offered within this new design domain. In this paper we address a key issue in pattern matching and classification process and hence suggest an alternative approach for image vector matching combining Complementary Resistive Switch (CRS) array and bump circuits. We emulated an experimental pattern matching with two approaches which are based on Hamming distance and threshold level of the image: the former finds an exact image with a bump circuit and the later finds similar patterns from the stored images combining comparators. The proposed hardware oriented architecture is high speed and smaller size that is easier to implement on conventional CMOS technology.

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011

The nanometer scale feature of memristor created a broad range of opportunities for innovative ar... more The nanometer scale feature of memristor created a broad range of opportunities for innovative architectures. The nature of the boundary conditions, the complexity of the ionic transport and tunneling mechanism, and the nanoscale feature of the memristor introduces new challenges in model ing, characterization, and measurements for Memristor-MOS (M 2 ) circuits. These new challenges can be addressed by a joint insight from the circuit designer and device engineers, which will dictate the needed modeling and layout rules to attain an accurate estimation of M 2 circuit performance. In this paper, memristive behavior of titanium dioxide (Ti0 2 ) is studied using a novel combination of electrodes, silver (Ag) and indium thin oxide (ITO). Fabrication method and a modeling approach are also explained. The ITO electrode provide (a) an excellent transparency in visible light, (b) improved functional reproducibility, and (c) non-volatile characteristics as well as a promising unique application of the M 2 circuits in sensory applications. Furthermore, proposed modeling approach shows a good agreement between measurements and simulations of analog memory characteristics and reproducibility as well as long-term retention.

Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation

2009 IEEE Computer Society Annual Symposium on VLSI, 2009

Redundant Number Systems have been widely used in fast arithmetic circuits design. Signed-Digit (... more Redundant Number Systems have been widely used in fast arithmetic circuits design. Signed-Digit (SD) or generally High-Radix SD (HRSD) number system is one of the most important redundant number systems. HRSD additions are used in many arithmetic functions as ...

A Complete and Highly Flexible 256-Electrode Retinal Prosthesis Chip

Thermodynamic-driven filament formation in redox-based resistive memory and the impact of thermal... more Thermodynamic-driven filament formation in redox-based resistive memory and the impact of thermal fluctuations on switching probability of emerging magnetic switches are probabilistic phenomena in nature, and thus, processes of binary switching in these nonvolatile memories are stochastic and vary from switching cycle-to-switching cycle, in the same device, and from device-to-device, hence, they provide a rich in-situ spatiotemporal stochastic characteristic. This work presents a highly scalable neuromorphic hardware based on crossbar array of 1-bit resistive crosspoints as distributed stochastic synapses. The network shows a robust performance in emulating selectivity of synaptic potentials in neurons of primary visual cortex to the orientation of a visual image. The proposed model could be configured to accept a wide range of nanodevices.

Spike Timing-Dependent Plasticity (STDP) is one of several plasticity rules that is believed to p... more Spike Timing-Dependent Plasticity (STDP) is one of several plasticity rules that is believed to play an important role in learning and memory in the brain. In conventional pairbased STDP learning, synaptic weights are altered by utilizing the temporal difference between pairs of pre-and post-synaptic spikes. This learning rule, however, fails to reproduce reported experimental measurements when using stimuli either by patterns consisting of triplet or quadruplet of spikes or increasing the repetition frequency of pairs of spikes. Significantly, a previously described spike triplet-based STDP rule succeeds in reproducing all of these experimental observations. In this paper, we present a new spike triplet-based VLSI implementation, that is based on a previous pair-based STDP circuit [1]. This implementation can reproduce similar results to those observed in various physiological STDP experiments, in contrast to traditional pairbased VLSI implementation. Simulation results using standard 0.35 µm CMOS process of the new circuit are presented and compared to published experimental data .

Nanosession: Logic Devices and Circuit Design

A Collection of Extended Abstracts of the Nature Conference Frontiers in Electronic Materials, June 17 th to 20 th 2012, Aachen, Germany, 2012

2008 IEEE Computer Society Annual Symposium on VLSI, 2008

Full-adders are the core element of the complex arithmetic circuits like addition, multiplication... more Full-adders are the core element of the complex arithmetic circuits like addition, multiplication, division and exponentiation. Regarding to this importance, new idea and investigations for constructing full-adders are required. As far as related literature is concerned, generality and ease of use, as well as voltage and transistor scaling are considerable advantages of CMOS logic design versus other design style such as CPL specially when cell-based design are targeted. This paper proposes a novel, symmetric and efficient design for a CMOS 1-bit full-adder. Besides, another fully symmetric full-adder has been presented. Results and simulations demonstrate that the proposed design leads to an efficient full-adder in terms of power consumption, delay and area in comparison to a well-known conventional full-adder design. The postlayout simulations have been done by HSPICE with nanometer scale transistors considering all parasitic capacitors and resistors.

Smart Structures, Devices, and Systems IV, 2008

Adders are the core element in arithmetic circuits like subtracters, multipliers, and dividers. O... more Adders are the core element in arithmetic circuits like subtracters, multipliers, and dividers. Optimization of adders can be achieved at device, circuit, architectural, and algorithmic levels. In this paper we present a new optimize full adder circuit structure that provides an improved performance compared to standard and mirror types adder structures. The performance of this adder in terms of power, delay, energy, and yield are investigated. This paper also proposes a novel simulation setup for full adder cells that is suitable for analyzing full adder cells at the high frequency. The simulation results of this structure will take into account the process variations for a 90 nm CMOS process and present results based on post-layout simulation using Cadence and Synopsys tools.

Nanoscale, 2014

We suggest a 'universal' electrical circuit for the realization of an artificial synapse that exh... more We suggest a 'universal' electrical circuit for the realization of an artificial synapse that exhibits longterm plasticity induced by different protocols. The long-term plasticity of the artificial synapse is basically attributed to the nonvolatile resistance change of the bipolar resistive switch in the circuit. The synaptic behaviour realized by the circuit is termed 'universal' inasmuch as (i) the shape of the action potential is not required to vary so as to implement different plasticity-induction behaviours, activity-dependent plasticity (ADP) and spike-timing-dependent plasticity (STDP), (ii) the behaviours satisfy several essential features of a biological chemical synapse including firing-rate and spike-timing encoding and unidirectional synaptic transmission, and (iii) both excitatory and inhibitory synapses can be realized using the same circuit but different diode polarity in the circuit. The feasibility of the suggested circuit as an artificial synapse is demonstrated by conducting circuit calculations and the calculation results are introduced in comparison with biological chemical synapses. † Electronic supplementary information (ESI) available. See

Live demonstration: An associative capacitive network based on nanoscale complementary resistive switches

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014

ABSTRACT Integration density is a major drawback of today's associative memories required... more ABSTRACT Integration density is a major drawback of today's associative memories required for intelligent data processing for such as pattern recognition or classification. Ultra dense complementary resistive switch-based architectures are thought to overcome this issue, offering a footprint of 4F2. Here we demonstrate the feasibility of an 8 by 16 associative capacitive network.

A unique set of characteristics are packed in emerging nonvolatile reduction-oxidation (redox)-ba... more A unique set of characteristics are packed in emerging nonvolatile reduction-oxidation (redox)-based resistive switching memories (ReRAMs) such as their underlying stochastic switching processes alongside their intrinsic highly nonlinear current-voltage characteristic, which in addition to known nanofabrication process variation make them a promising candidate for the next generation of low-cost, low-power, tiny and secure Physically Unclonable Functions (PUFs). This paper takes advantage of this otherwise disadvantageous ReRAM feature using a combination of novel architectural and peripheral circuitry. We present a physical one-way function, nonlinear resistive Physical Unclonable Function (nrPUF), potentially applicable in variety of cyber-physical security applications given its performance characteristics. We experimentally verified performance of Valency Change Mechanism (VCM)-based ReRAM in nano-fabricated crossbar arrays across multiple dies and runs. In addition to a massive pool of Challenge-Response Pairs (CRPs), using a combination of experimental and simulation, our proposed PUF shows a reliability of 98.67%, a uniqueness of 49.85%, a diffuseness of 49.86%, a uniformity of 47.28%, and a bit-aliasing of 47.48%. Index Terms—Physical unclonable function, resistive random access memory, emerging nonvolatile memory.