Smitha Kaje | Birla Institute of Technology and Sciences, Pilani (original) (raw)

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Papers by Smitha Kaje

Research paper thumbnail of Towards a Talking Tiny Cognitive Architecture for the Study of Spoken Language Evolution

Research paper thumbnail of Fast Image Convolution and Pattern Recognition using Vedic Mathematics on Field Programmable Gate Arrays (FPGAs)

2022 OITS International Conference on Information Technology (OCIT)

Research paper thumbnail of Design and FPGA Implementation of an Efficient 8×8 Multiplier Using the Principle of Vedic Mathematics

This paper is regarding the design and analysis of an efficient 8×8 Vedic multiplier by the princ... more This paper is regarding the design and analysis of an efficient 8×8 Vedic multiplier by the principle of Vedic mathematics [1]. Here, a unique Vedic multiplier architecture is adapted, which is not based on the regular method of multiplication (addition, shifting). The design is as per the "Urdhwa-Tiryakbhyam Sutra" of Vedic mathematics. Two numbers (binary of 8-bit each) are multiplied using the methodology of this principle/sutra. "Urdhwa-Tiryakbhyam" means "vertically and crosswise", wherein the partial products are computed at once, thus lessening the delay and hence making the multiplication faster. This 8 by 8 bit multiplier is coded in Verilog HDL and tested on a DE10-lite FPGA kit.

Research paper thumbnail of Towards a Talking Tiny Cognitive Architecture for the Study of Spoken Language Evolution

Research paper thumbnail of Fast Image Convolution and Pattern Recognition using Vedic Mathematics on Field Programmable Gate Arrays (FPGAs)

2022 OITS International Conference on Information Technology (OCIT)

Research paper thumbnail of Design and FPGA Implementation of an Efficient 8×8 Multiplier Using the Principle of Vedic Mathematics

This paper is regarding the design and analysis of an efficient 8×8 Vedic multiplier by the princ... more This paper is regarding the design and analysis of an efficient 8×8 Vedic multiplier by the principle of Vedic mathematics [1]. Here, a unique Vedic multiplier architecture is adapted, which is not based on the regular method of multiplication (addition, shifting). The design is as per the "Urdhwa-Tiryakbhyam Sutra" of Vedic mathematics. Two numbers (binary of 8-bit each) are multiplied using the methodology of this principle/sutra. "Urdhwa-Tiryakbhyam" means "vertically and crosswise", wherein the partial products are computed at once, thus lessening the delay and hence making the multiplication faster. This 8 by 8 bit multiplier is coded in Verilog HDL and tested on a DE10-lite FPGA kit.

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