Georgi Gaydadjiev | University of Groningen (original) (raw)

Papers by Georgi Gaydadjiev

Research paper thumbnail of Novel design methods and a tool flow for unleashing dynamic reconfiguration

Research paper thumbnail of D4. 3: Configuration Scheduler Requirements and Basic Functionality

Research paper thumbnail of 64-bit floating-point FPGA matrix multiplication

Research paper thumbnail of The molen polymorphic processor

Research paper thumbnail of 47 Vector Processor Customization For Fft

Research paper thumbnail of 1353 Separable 2d Convolution With Polymorphic Register Files

Research paper thumbnail of 6 Sequence Alignment Application Model For Multi And Manycore A

Research paper thumbnail of 51 Scaling Hmmer Performance On Multicore Architectures

Research paper thumbnail of 1319 Improving Dram Performance And Energy Efficiency

Research paper thumbnail of 17 Hmmer Performance Model For Multicore Architectures

Research paper thumbnail of 1292 Addressing Gpu Onchip Shared Memory Bank Conflicts Using E

Research paper thumbnail of 1343 A Novel Productivitydriven Logic Element For Fieldprogram

Research paper thumbnail of 1320 Implementation Study Of Fft On Multilane Vector Processors

Research paper thumbnail of 1290 Scalability Study Of Polymorphic Register Files

Research paper thumbnail of 1293 On Implementability Of Polymorphic Register Files

Research paper thumbnail of 1325 On Improved Manet Network Utilization

Research paper thumbnail of Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints

Research paper thumbnail of Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints

Research paper thumbnail of An analysis of (linked) address decoder faults

The complexity of memory tests arises when linked faults are taken into consideration. Usually on... more The complexity of memory tests arises when linked faults are taken into consideration. Usually only the class of linked faults in the memory cell array have been taken into consideration, while the class of linked faults involving address decoder faults has been ignored. This paper gives an overview of the most important and commonly used fault models including the disturb fault model. It derives a set of conditions march tests have to satisfy in order to detect address decoder faults (AFs) when they are not linked; these conditions are shown to be dependent on the memory technology (SRAM and DRAM). Next, a set of conditions for march tests are derived to detect linked AFs (linked with other AFs or linked with faults in the memory cell array). The paper concludes with the analysis of a set of well-known march tests for the fault coverage of unlinked and linked AFs. Many of the widely used tests are shown not to be able to detect all (linked) AFs

Research paper thumbnail of An analysis of and the detectabilities of (linked) memory cell and address decoder faults

Research paper thumbnail of Novel design methods and a tool flow for unleashing dynamic reconfiguration

Research paper thumbnail of D4. 3: Configuration Scheduler Requirements and Basic Functionality

Research paper thumbnail of 64-bit floating-point FPGA matrix multiplication

Research paper thumbnail of The molen polymorphic processor

Research paper thumbnail of 47 Vector Processor Customization For Fft

Research paper thumbnail of 1353 Separable 2d Convolution With Polymorphic Register Files

Research paper thumbnail of 6 Sequence Alignment Application Model For Multi And Manycore A

Research paper thumbnail of 51 Scaling Hmmer Performance On Multicore Architectures

Research paper thumbnail of 1319 Improving Dram Performance And Energy Efficiency

Research paper thumbnail of 17 Hmmer Performance Model For Multicore Architectures

Research paper thumbnail of 1292 Addressing Gpu Onchip Shared Memory Bank Conflicts Using E

Research paper thumbnail of 1343 A Novel Productivitydriven Logic Element For Fieldprogram

Research paper thumbnail of 1320 Implementation Study Of Fft On Multilane Vector Processors

Research paper thumbnail of 1290 Scalability Study Of Polymorphic Register Files

Research paper thumbnail of 1293 On Implementability Of Polymorphic Register Files

Research paper thumbnail of 1325 On Improved Manet Network Utilization

Research paper thumbnail of Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints

Research paper thumbnail of Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints

Research paper thumbnail of An analysis of (linked) address decoder faults

The complexity of memory tests arises when linked faults are taken into consideration. Usually on... more The complexity of memory tests arises when linked faults are taken into consideration. Usually only the class of linked faults in the memory cell array have been taken into consideration, while the class of linked faults involving address decoder faults has been ignored. This paper gives an overview of the most important and commonly used fault models including the disturb fault model. It derives a set of conditions march tests have to satisfy in order to detect address decoder faults (AFs) when they are not linked; these conditions are shown to be dependent on the memory technology (SRAM and DRAM). Next, a set of conditions for march tests are derived to detect linked AFs (linked with other AFs or linked with faults in the memory cell array). The paper concludes with the analysis of a set of well-known march tests for the fault coverage of unlinked and linked AFs. Many of the widely used tests are shown not to be able to detect all (linked) AFs

Research paper thumbnail of An analysis of and the detectabilities of (linked) memory cell and address decoder faults