Khaled Sharaf | Ain Shams University (original) (raw)

Papers by Khaled Sharaf

High-Performance Digital VLSI Circuit Design, 1996

High-performance integrated circuits, which can operate at frequencies in the GHz range, are requ... more High-performance integrated circuits, which can operate at frequencies in the GHz range, are required for applications such as wireless digital communications and fiber-optic data transmission. Parallel computers, high resolution graphics, and network backbones are among the many applications that could immediately benefit from inexpensive, compact, and easy-to-use giga-bit rate fiber-optic data links. Mobile communications have been also growing rapidly in this decade.

High-Performance Digital VLSI Circuit Design, 1996

An analytical model for calculating the propagation delay time of two-level series-gated CML and ... more An analytical model for calculating the propagation delay time of two-level series-gated CML and ECL high-speed bipolar circuits is presented. The analytical delay model accounts for different transistor sizes at the two levels. Moreover, high-current effects are also considered in the developed model. Exploiting these two features, the model has been successfully applied in optimizing the design of a variety of two-level series-gated CML and ECL circuits. A comparison with the results obtained by SPICE is presented to verify the applicability of the proposed model.

High-Performance Digital VLSI Circuit Design, 1996

High-Performance Digital VLSI Circuit Design, 1996

In this chapter the performance of the different two-level series-gated CML BiCMOS schemes will b... more In this chapter the performance of the different two-level series-gated CML BiCMOS schemes will be studied and compared. Simulation results, based on a 0.6-um BiCMOS technology, show an improvement of 64% in the maximum frequency of operation of the BJT-MOS static frequency divider over the BJT scheme operating in the low power regime (< 1 mW). Moreover, the BJT-MOS frequency divider configuration a high input sensitivity throughout the frequency range of operation. In addition, a proposed BiCMOS latched-comparator shows favorable input voltage sensitivity over conventional bipolar design under low-power operation. Secondly, a brief overview of high-performance ECL circuit techniques is covered along with a rough comparison and evaluation of such techniques. A new BiCMOS Active-Pull-Down (APD) ECL circuit is also presented which can achieve 32% improvement in the load driving capability and 43% improvement in the propagation delay over conventional ECL circuit.

High-Performance Digital VLSI Circuit Design, 1996

The dual purposes of this chapter are to review the design of recent high-performance CMOS circui... more The dual purposes of this chapter are to review the design of recent high-performance CMOS circuits and to introduce and analyze novel all-N-logic single-phase high-speed pipelined dynamic CMOS circuits.

High-Performance Digital VLSI Circuit Design, 1996

A new analytical delay model for high-speed CML circuits is presented. It is applicable to high-s... more A new analytical delay model for high-speed CML circuits is presented. It is applicable to high-speed/low-voltage-swing silicon and HBT CML circuits operating at medium or high current densities. The model is based on the bipolar SPICE parameters file, and can be used to estimate the propagation delay time of CML circuits under different operating conditions. The detailed transient analysis accounts for delay components due to each element in the complete SPICE bipolar transistor model. The comparison with SPICE circuit simulation results shows excellent agreement for a wide range of state-of-the-art technologies and circuit parameters. The new model predicts the delay time with less than 5% error in most cases. The influence of the finite slopes (slewing rate) of the input signal and the device dimensions is also investigated. The delay model determines the optimum current io(or load resistorR L ) for a transistor of a certain emitter area when driven by a source of a voltage swing (ΔV) and slew time(t r ).At a specified power dissipation, the delay model is used to optimally size the transistor emitter area for maximum switching speed. The model provides circuit and device guidelines to minimize the propagation in delay time and improve the performance of high-speed CML circuits.

Proceedings of the 2019 2nd International Conference on Sensors, Signal and Image Processing - SSIP 2019, 2019

... 6 shows VHDL simulation results for fclk = 6.25 MHz. For the purpose of clarity the figure is... more ... 6 shows VHDL simulation results for fclk = 6.25 MHz. For the purpose of clarity the figure is drawn for an over-sampling ratio of 4 instead of 16 and only 4-bit delay word. ... More optimization can be done to reduce the utilization. ... 6. VHDL timing simulation for FCW (PINC) = 0xB. ...

High-Performance Digital VLSI Circuit Design, 1996

This chapter presents high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits ... more This chapter presents high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier for static memory. Optimal use of the bipolar and MOS transistors pushes BiCMOS circuits to operate toward the limits of standard BiCMOS technologies. The chapter shows readers that the bipolar transistors in BiCMOS circuits not only serve as conventional output drivers, but also play an important role in circuit design such as for voltage clamps, current amplification, and current differential amplification. A generic 0.8µm complementary BiCMOS technology has been used in the circuit design. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuits, and the BiCMOS sense amplifier are improved by 20%, 250%, and 60% respectively. An analytical circuit delay model for DRV-CMOS/ECL interface circuits, which fits HSPICE simulation results, is addressed. The error between the model and the circuit simulator is within 4%. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V.

Quantum Electronics, IEEE Journal of, 2002

Page 1. IEEE JOURNAL OF QUANTUM ELECTRONICS. VOL. 26. NO. 8. AUGUST IYYO 1347 The Effect of Elect... more Page 1. IEEE JOURNAL OF QUANTUM ELECTRONICS. VOL. 26. NO. 8. AUGUST IYYO 1347 The Effect of Electronic Feedback on Semiconductor Lasers KHALED SHARAF AND MAGDY M. IBRAHIM Abstract-Negative electronic ...

High-Performance Digital VLSI Circuit Design, 1996

This is a very good, practical text for all who wish to increase their knowledge and expertise in... more This is a very good, practical text for all who wish to increase their knowledge and expertise in this subject area, with extensive circuit exampies and design and performance equations being given. A basic knowledge of electronic design is assumed, which is then built upon to provide a working and reference text rather than a research text in this area.

IEEE International Symposium on Circuits and Systems …, 2007

Abstract—This frequency synthesizer presents a fully inte-grated solution by using a newly develo... more Abstract—This frequency synthesizer presents a fully inte-grated solution by using a newly developed low noise, wide bandwidth ring-based VCO which depends on inductive peaking. The new VCO is characterized by its low phase noise and power consumption compared to ordinary ...

2003 46th Midwest Symposium on Circuits and Systems, 2003

A dual phase s itched capacitor common mode feedbac (SC CMFB) circuit is proposed hich is suitabl... more A dual phase s itched capacitor common mode feedbac (SC CMFB) circuit is proposed hich is suitable for double sampling circuits. A 4n order SC bandpass sigma delta modulator designed in 0. jgm CMOS is used as a testbench to compare the proposed circuit to ...

Fiber Lasers XIV: Technology and Systems, 2017

2008 9th International Conference on Solid State and Integrated Circuit Technology, 2008

A 1.2 V Bluetooth receiver was implemented in a 0.13 ¿m CMOS process. The receiver supports both ... more A 1.2 V Bluetooth receiver was implemented in a 0.13 ¿m CMOS process. The receiver supports both the basic data rate at 1 Mb/s and the enhanced date rate (EDR) at 2 Mb/s and 3 Mb/s Bluetooth modes. The presented receiver is highly integrated with only 13 mA current consumption at 1.2 V supply. At this low power consumption, the

2016 33rd National Radio Science Conference (NRSC), 2016

In this work, we present an optical gyroscope based on hybrid semiconductor-fiber ring laser. The... more In this work, we present an optical gyroscope based on hybrid semiconductor-fiber ring laser. The proposed optical gyroscope is a Ring Laser Gyroscope (RLG), in which the laser cavity is a fiber ring of standard single mode fiber where a semiconductor optical amplifier is used as the gain medium for the ring laser. Taking advantage of the bidirectional nature of the ring laser cavity, two counter-propagating waves are supported in the ring cavity. The two waves are identical in terms of their optical resonance frequency due to the reciprocity of the loop in the static position. A frequency shift is introduced between the two counter-propagating waves when the loop is subjected to an angular rotation, known as the Sagnac effect, and the magnitude of the shift is proportional to the rotation rate. Due to the multi-longitudinal mode nature of the constructed ring laser, the rotation sensor optical system parameters are optimized in a trade-off between the sensitivity and the dynamic range. Special signal processing algorithms are developed to enhance the RLG sensitivity. The performance of the RLG is evaluated using a rate table and the Allan variance of the sensor is extracted. The demonstrated RLG has an excellent linear scale factor with a dynamic range up to 40°/sec and a sensitivity down to 0.2°/sec. The RLG noise specifications as extracted from the Allan variance are a bias instability of 3°/h and an angular random walk of 0.5°/√h.

Analog Integrated Circuits and Signal Processing, May 1, 2010

Abstract This paper presents the design of a dual-band L1/L2 GPS receiver, that can be easily int... more Abstract This paper presents the design of a dual-band L1/L2 GPS receiver, that can be easily integrated in por-table devices (mainly GSM mobile phones). For the ease of integration with GSM wireless systems the receiver can tolerate most of the common GSM crystals, ...

Proceedings of 2010 Ieee International Symposium on Circuits and Systems, 2010

... Khaled Sharaf Ain Shams University, Cairo, Egypt Email: kmsharaf@ieee.org ... ACKNOWLEDGMENT ... more ... Khaled Sharaf Ain Shams University, Cairo, Egypt Email: kmsharaf@ieee.org ... ACKNOWLEDGMENT The authors would like to thank Shohdy Abd El-Kader from Mentor Graphics Egypt for his continuous support and fruitful discussions. ...

High-Performance Digital VLSI Circuit Design, 1996

High-performance integrated circuits, which can operate at frequencies in the GHz range, are requ... more High-performance integrated circuits, which can operate at frequencies in the GHz range, are required for applications such as wireless digital communications and fiber-optic data transmission. Parallel computers, high resolution graphics, and network backbones are among the many applications that could immediately benefit from inexpensive, compact, and easy-to-use giga-bit rate fiber-optic data links. Mobile communications have been also growing rapidly in this decade.

High-Performance Digital VLSI Circuit Design, 1996

An analytical model for calculating the propagation delay time of two-level series-gated CML and ... more An analytical model for calculating the propagation delay time of two-level series-gated CML and ECL high-speed bipolar circuits is presented. The analytical delay model accounts for different transistor sizes at the two levels. Moreover, high-current effects are also considered in the developed model. Exploiting these two features, the model has been successfully applied in optimizing the design of a variety of two-level series-gated CML and ECL circuits. A comparison with the results obtained by SPICE is presented to verify the applicability of the proposed model.

High-Performance Digital VLSI Circuit Design, 1996

High-Performance Digital VLSI Circuit Design, 1996

In this chapter the performance of the different two-level series-gated CML BiCMOS schemes will b... more In this chapter the performance of the different two-level series-gated CML BiCMOS schemes will be studied and compared. Simulation results, based on a 0.6-um BiCMOS technology, show an improvement of 64% in the maximum frequency of operation of the BJT-MOS static frequency divider over the BJT scheme operating in the low power regime (< 1 mW). Moreover, the BJT-MOS frequency divider configuration a high input sensitivity throughout the frequency range of operation. In addition, a proposed BiCMOS latched-comparator shows favorable input voltage sensitivity over conventional bipolar design under low-power operation. Secondly, a brief overview of high-performance ECL circuit techniques is covered along with a rough comparison and evaluation of such techniques. A new BiCMOS Active-Pull-Down (APD) ECL circuit is also presented which can achieve 32% improvement in the load driving capability and 43% improvement in the propagation delay over conventional ECL circuit.

High-Performance Digital VLSI Circuit Design, 1996

The dual purposes of this chapter are to review the design of recent high-performance CMOS circui... more The dual purposes of this chapter are to review the design of recent high-performance CMOS circuits and to introduce and analyze novel all-N-logic single-phase high-speed pipelined dynamic CMOS circuits.

High-Performance Digital VLSI Circuit Design, 1996

A new analytical delay model for high-speed CML circuits is presented. It is applicable to high-s... more A new analytical delay model for high-speed CML circuits is presented. It is applicable to high-speed/low-voltage-swing silicon and HBT CML circuits operating at medium or high current densities. The model is based on the bipolar SPICE parameters file, and can be used to estimate the propagation delay time of CML circuits under different operating conditions. The detailed transient analysis accounts for delay components due to each element in the complete SPICE bipolar transistor model. The comparison with SPICE circuit simulation results shows excellent agreement for a wide range of state-of-the-art technologies and circuit parameters. The new model predicts the delay time with less than 5% error in most cases. The influence of the finite slopes (slewing rate) of the input signal and the device dimensions is also investigated. The delay model determines the optimum current io(or load resistorR L ) for a transistor of a certain emitter area when driven by a source of a voltage swing (ΔV) and slew time(t r ).At a specified power dissipation, the delay model is used to optimally size the transistor emitter area for maximum switching speed. The model provides circuit and device guidelines to minimize the propagation in delay time and improve the performance of high-speed CML circuits.

Proceedings of the 2019 2nd International Conference on Sensors, Signal and Image Processing - SSIP 2019, 2019

... 6 shows VHDL simulation results for fclk = 6.25 MHz. For the purpose of clarity the figure is... more ... 6 shows VHDL simulation results for fclk = 6.25 MHz. For the purpose of clarity the figure is drawn for an over-sampling ratio of 4 instead of 16 and only 4-bit delay word. ... More optimization can be done to reduce the utilization. ... 6. VHDL timing simulation for FCW (PINC) = 0xB. ...

High-Performance Digital VLSI Circuit Design, 1996

This chapter presents high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits ... more This chapter presents high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier for static memory. Optimal use of the bipolar and MOS transistors pushes BiCMOS circuits to operate toward the limits of standard BiCMOS technologies. The chapter shows readers that the bipolar transistors in BiCMOS circuits not only serve as conventional output drivers, but also play an important role in circuit design such as for voltage clamps, current amplification, and current differential amplification. A generic 0.8µm complementary BiCMOS technology has been used in the circuit design. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuits, and the BiCMOS sense amplifier are improved by 20%, 250%, and 60% respectively. An analytical circuit delay model for DRV-CMOS/ECL interface circuits, which fits HSPICE simulation results, is addressed. The error between the model and the circuit simulator is within 4%. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V.

Quantum Electronics, IEEE Journal of, 2002

Page 1. IEEE JOURNAL OF QUANTUM ELECTRONICS. VOL. 26. NO. 8. AUGUST IYYO 1347 The Effect of Elect... more Page 1. IEEE JOURNAL OF QUANTUM ELECTRONICS. VOL. 26. NO. 8. AUGUST IYYO 1347 The Effect of Electronic Feedback on Semiconductor Lasers KHALED SHARAF AND MAGDY M. IBRAHIM Abstract-Negative electronic ...

High-Performance Digital VLSI Circuit Design, 1996

This is a very good, practical text for all who wish to increase their knowledge and expertise in... more This is a very good, practical text for all who wish to increase their knowledge and expertise in this subject area, with extensive circuit exampies and design and performance equations being given. A basic knowledge of electronic design is assumed, which is then built upon to provide a working and reference text rather than a research text in this area.

IEEE International Symposium on Circuits and Systems …, 2007

Abstract—This frequency synthesizer presents a fully inte-grated solution by using a newly develo... more Abstract—This frequency synthesizer presents a fully inte-grated solution by using a newly developed low noise, wide bandwidth ring-based VCO which depends on inductive peaking. The new VCO is characterized by its low phase noise and power consumption compared to ordinary ...

2003 46th Midwest Symposium on Circuits and Systems, 2003

A dual phase s itched capacitor common mode feedbac (SC CMFB) circuit is proposed hich is suitabl... more A dual phase s itched capacitor common mode feedbac (SC CMFB) circuit is proposed hich is suitable for double sampling circuits. A 4n order SC bandpass sigma delta modulator designed in 0. jgm CMOS is used as a testbench to compare the proposed circuit to ...

Fiber Lasers XIV: Technology and Systems, 2017

2008 9th International Conference on Solid State and Integrated Circuit Technology, 2008

A 1.2 V Bluetooth receiver was implemented in a 0.13 ¿m CMOS process. The receiver supports both ... more A 1.2 V Bluetooth receiver was implemented in a 0.13 ¿m CMOS process. The receiver supports both the basic data rate at 1 Mb/s and the enhanced date rate (EDR) at 2 Mb/s and 3 Mb/s Bluetooth modes. The presented receiver is highly integrated with only 13 mA current consumption at 1.2 V supply. At this low power consumption, the

2016 33rd National Radio Science Conference (NRSC), 2016

In this work, we present an optical gyroscope based on hybrid semiconductor-fiber ring laser. The... more In this work, we present an optical gyroscope based on hybrid semiconductor-fiber ring laser. The proposed optical gyroscope is a Ring Laser Gyroscope (RLG), in which the laser cavity is a fiber ring of standard single mode fiber where a semiconductor optical amplifier is used as the gain medium for the ring laser. Taking advantage of the bidirectional nature of the ring laser cavity, two counter-propagating waves are supported in the ring cavity. The two waves are identical in terms of their optical resonance frequency due to the reciprocity of the loop in the static position. A frequency shift is introduced between the two counter-propagating waves when the loop is subjected to an angular rotation, known as the Sagnac effect, and the magnitude of the shift is proportional to the rotation rate. Due to the multi-longitudinal mode nature of the constructed ring laser, the rotation sensor optical system parameters are optimized in a trade-off between the sensitivity and the dynamic range. Special signal processing algorithms are developed to enhance the RLG sensitivity. The performance of the RLG is evaluated using a rate table and the Allan variance of the sensor is extracted. The demonstrated RLG has an excellent linear scale factor with a dynamic range up to 40°/sec and a sensitivity down to 0.2°/sec. The RLG noise specifications as extracted from the Allan variance are a bias instability of 3°/h and an angular random walk of 0.5°/√h.

Analog Integrated Circuits and Signal Processing, May 1, 2010

Abstract This paper presents the design of a dual-band L1/L2 GPS receiver, that can be easily int... more Abstract This paper presents the design of a dual-band L1/L2 GPS receiver, that can be easily integrated in por-table devices (mainly GSM mobile phones). For the ease of integration with GSM wireless systems the receiver can tolerate most of the common GSM crystals, ...

Proceedings of 2010 Ieee International Symposium on Circuits and Systems, 2010

... Khaled Sharaf Ain Shams University, Cairo, Egypt Email: kmsharaf@ieee.org ... ACKNOWLEDGMENT ... more ... Khaled Sharaf Ain Shams University, Cairo, Egypt Email: kmsharaf@ieee.org ... ACKNOWLEDGMENT The authors would like to thank Shohdy Abd El-Kader from Mentor Graphics Egypt for his continuous support and fruitful discussions. ...