Dipu Pramanik | Stanford University (original) (raw)

Papers by Dipu Pramanik

Research paper thumbnail of Assessing technology tradeoffs for 65nm logic circuits

The 2001 ITRS roadmap identified the need for tight coupling of design technology with manufactur... more The 2001 ITRS roadmap identified the need for tight coupling of design technology with manufacturing technology in order to ensure the successful production of circuits fabricated at the 65nm technology node. The design creation process for 65nm needs to efficiently explore the interaction between device, cell design and manufacturability. Using fast simulation tools for device and lithography simulation and an automated tool for standard cell generation, various process and cell architectural options were investigated. The average and standard deviation of line width had to be matched to the type of application because of the direct relationship between leakage current and performance. Best process latitude for poly line widths is achieved with Full Phase technology. It is shown that by matching design rules to the Full Phase capabilities and using automated layout tools, manufacturability could be optimized without hurting density or performance.

Research paper thumbnail of SOFTWARE-Analyzing strained-silicon options for stress-engineering transistors-Careful stress engineering can enhance device performance by more than 50%. but there are tradeoffs in processing

Research paper thumbnail of Megaelectronvolt implantations in silicon very-large-scale integration

Materials Science and Engineering B-advanced Functional Solid-state Materials, 1989

Research paper thumbnail of When IC yield missed the target, who is at fault

Silicon yield once was dominated by contaminants and particulates, making yield a process issue. ... more Silicon yield once was dominated by contaminants and particulates, making yield a process issue. But with today's electronics supply chain, multiple suspects may be indicted on manufacturability issues. Who is responsible for preventative actions in manufacturability and yield? The AUTHORs, representing a foundry, a fabless company, an IP provider, two EDA vendors, and an IC design team, will discuss the

Research paper thumbnail of When IC yield missed the target, who is at fault

Silicon yield once was dominated by contaminants and particulates, making yield a process issue. ... more Silicon yield once was dominated by contaminants and particulates, making yield a process issue. But with today's electronics supply chain, multiple suspects may be indicted on manufacturability issues. Who is responsible for preventative actions in manufacturability and yield? The panelists, representing a foundry, a fabless company, an IP provider, two EDA vendors, and an IC design team, will discuss the problems and the solutions for achieving manufacturability and yield goals.

Research paper thumbnail of TCAD Analysis for VLSI-Application-Oriented Process Optimization

A new process optimization procedure is hereby presented, based on the quantitative impact of the... more A new process optimization procedure is hereby presented, based on the quantitative impact of the variations of process variables on VLSI design performance. Process tuning is obtained through reverse modeling on transistor characteristics, process variations are then addressed by means of consistent TCAD simulations. Optimum process variables for minimum dynamic and static dissipation have been investigated in a low-power prototype chip, integrated in a 0.25 mum technology

Research paper thumbnail of A Full 3D TCAD Simulation Study of Line-Width Roughness Effects in 65 nm Technology

For the 65 nm technology node and beyond, new manufacturability problems are arising that strongl... more For the 65 nm technology node and beyond, new manufacturability problems are arising that strongly impact device and circuit behavior. Among these problems, line-edge and line-width roughness (LER and LWR) are of particular interest as dominant issues affecting parametric yield. In this paper, we investigate LWR effects by applying latest generation, full 3D TCAD technology including lithography simulation. In addition, our results answer open questions concerning the applicability of 2D slicing approximations vis a vis a 3D modeling effort. While LWR has been investigated by TCAD before, our methodology includes a full 3D process simulation (including lithography) without simplifications to generate the final transistor structures

Research paper thumbnail of A manufacturable shallow trench isolation process for 0.18 μm and beyond-optimization, stress reduction and electrical performance

An integrated shallow trench isolation process utilizing HDP (high density plasma) oxide and a hi... more An integrated shallow trench isolation process utilizing HDP (high density plasma) oxide and a highly manufacturable corner oxidation is described. The choice of trench corner oxidation temperature is shown to be critical in reducing silicon stress, and hence junction leakage, to the levels required by multi-million gate designs. This STI process is shown to be extremely robust and manufacturable. Optimal design of the trench depth and well profiles is shown to provide well-edge isolation adequate for sub-0.18 μm technologies

Research paper thumbnail of Bringing Manufacturing into Design via Process-Dependent SPICE Models

This paper describes methodology for constructing compact SPICE models as a function of process p... more This paper describes methodology for constructing compact SPICE models as a function of process parameter variations. The methodology involves global extraction of process-dependant SPICE model parameters from silicon calibrated TCAD simulations. The model is validated by comparing device characteristics from the extracted SPICE parameters with those from TCAD simulations. The analysis demonstrates an excellent goodness of fit over the full

Research paper thumbnail of Exploring the limits of stress-enhanced hole mobility

IEEE Electron Device Letters, 2005

Hole mobility is found to more than double in fabricated p-MOSFETs with SiGe source/drain due to ... more Hole mobility is found to more than double in fabricated p-MOSFETs with SiGe source/drain due to longitudinal compressive stress in the channel exceeding 1 GPa. The maximum observed low-field mobility enhancement is 140% at a simulated stress level of 1.45 GPa. The mobility enhancement is approximately linear with stress at moderate levels but becomes super-linear above 1 GPa. An important consequence of this behavior is that for moderate stress levels, an average channel stress can be used to estimate the performance of transistors with a nonuniform stress distribution across the channel width. Two alternative approaches to model stress-enhanced hole mobility are suggested. Analysis of the physical effects behind the experimental observations reveals the relative roles of band repopulation and mass modulation. In addition, previously published wafer bending experiments with compressive stress levels below 400 MPa are used to implicitly verify the accuracy of the stress simulations.

Research paper thumbnail of A systematic study of trade-offs in engineering a locally strained pMOSFET

We present the results of a study on the impact of process parameters on the performance of strai... more We present the results of a study on the impact of process parameters on the performance of strain enhanced pMOSFETs with recessed SiGe S/D. Recess depth, channel length, layout sensitivity, and their subsequent impact on strain and hole mobility are explored. Micro-Raman spectroscopy (μRS), process simulations, device simulations, and electrical results are presented. A 30% improvement in drive current is demonstrated.

Research paper thumbnail of The Impact of Layout on Stress-Enhanced Transistor Performance

This paper studies the sensitivity of stress-enhanced transistor performance to layout variations... more This paper studies the sensitivity of stress-enhanced transistor performance to layout variations. Stress simulations and mobility models are calibrated and verified for test structures with SiGe source/drain as a stressor. The role of STI on the stress transfer is explored. The numerical results show that variations of 15% in drive currents and of 44% in hole mobility due to layout induced stress variations can occur in the cases studied. These deviations need to be taken into account in circuit design or to be compensated via layout modification.

Research paper thumbnail of Trends, demands and challenges in TCAD

Materials Science and Engineering B-advanced Functional Solid-state Materials, 2005

Currently, TCAD is most heavily used in the device research and process integration phases of a t... more Currently, TCAD is most heavily used in the device research and process integration phases of a technology life cycle. However, a major trend visible in the industry is the demand to apply TCAD tools far beyond the integration phase into manufacturing and yield optimization. Short IC product lifetimes make fast yield ramp-up critical for being profitable and TCAD tools build a bridge between IC design and manufacturing. Another major trend is to use TCAD to evaluate layout dependent stress variations and account for these variations in the design flow of standard cells, libraries and custom ICs. This article gives an overview of those trends and addresses resulting challenges for TCAD models and tools.

Research paper thumbnail of Stress-Aware Design Methodology

Sub-90 nm CMOS circuits contain a significant amount of mechanical stress in active silicon. This... more Sub-90 nm CMOS circuits contain a significant amount of mechanical stress in active silicon. This stress is generated by a variety of intentional and unintentional stress sources. Shallow trench isolation is an example of an unintentional stress source, whereas embedded SiGe in the source and drain is an example of an intentional stress source. The amount of stress in each transistor in the circuit depends on the shape of its diffusion area as well as the density of the adjacent layout. The resulting non-uniform stress distribution alters individual transistor performance and, ultimately, the behavior of the circuit. In this paper, several examples are used to illustrate this effect based on design rules for the 45 nm technology node. A number of alternative approaches are suggested for partially suppressing or completely eliminating the stress-induced performance variations.

Research paper thumbnail of Optimizing boron junctions through point defect and stress engineering using carbon and germanium co-implants

Applied Physics Letters, 2005

Optimizing boron junctions through point defect and stress engineering using carbon and germanium... more Optimizing boron junctions through point defect and stress engineering using carbon and germanium co-implants. [Applied Physics Letters 87, 051908 (2005)]. Victor Moroz, Yong-Seog Oh, Dipu Pramanik, Houda Graoui, Majeed A. Foad. Abstract. ...

Research paper thumbnail of Assessing technology tradeoffs for 65nm logic circuits

The 2001 ITRS roadmap identified the need for tight coupling of design technology with manufactur... more The 2001 ITRS roadmap identified the need for tight coupling of design technology with manufacturing technology in order to ensure the successful production of circuits fabricated at the 65nm technology node. The design creation process for 65nm needs to efficiently explore the interaction between device, cell design and manufacturability. Using fast simulation tools for device and lithography simulation and an automated tool for standard cell generation, various process and cell architectural options were investigated. The average and standard deviation of line width had to be matched to the type of application because of the direct relationship between leakage current and performance. Best process latitude for poly line widths is achieved with Full Phase technology. It is shown that by matching design rules to the Full Phase capabilities and using automated layout tools, manufacturability could be optimized without hurting density or performance.

Research paper thumbnail of SOFTWARE-Analyzing strained-silicon options for stress-engineering transistors-Careful stress engineering can enhance device performance by more than 50%. but there are tradeoffs in processing

Research paper thumbnail of Megaelectronvolt implantations in silicon very-large-scale integration

Materials Science and Engineering B-advanced Functional Solid-state Materials, 1989

Research paper thumbnail of When IC yield missed the target, who is at fault

Silicon yield once was dominated by contaminants and particulates, making yield a process issue. ... more Silicon yield once was dominated by contaminants and particulates, making yield a process issue. But with today's electronics supply chain, multiple suspects may be indicted on manufacturability issues. Who is responsible for preventative actions in manufacturability and yield? The AUTHORs, representing a foundry, a fabless company, an IP provider, two EDA vendors, and an IC design team, will discuss the

Research paper thumbnail of When IC yield missed the target, who is at fault

Silicon yield once was dominated by contaminants and particulates, making yield a process issue. ... more Silicon yield once was dominated by contaminants and particulates, making yield a process issue. But with today's electronics supply chain, multiple suspects may be indicted on manufacturability issues. Who is responsible for preventative actions in manufacturability and yield? The panelists, representing a foundry, a fabless company, an IP provider, two EDA vendors, and an IC design team, will discuss the problems and the solutions for achieving manufacturability and yield goals.

Research paper thumbnail of TCAD Analysis for VLSI-Application-Oriented Process Optimization

A new process optimization procedure is hereby presented, based on the quantitative impact of the... more A new process optimization procedure is hereby presented, based on the quantitative impact of the variations of process variables on VLSI design performance. Process tuning is obtained through reverse modeling on transistor characteristics, process variations are then addressed by means of consistent TCAD simulations. Optimum process variables for minimum dynamic and static dissipation have been investigated in a low-power prototype chip, integrated in a 0.25 mum technology

Research paper thumbnail of A Full 3D TCAD Simulation Study of Line-Width Roughness Effects in 65 nm Technology

For the 65 nm technology node and beyond, new manufacturability problems are arising that strongl... more For the 65 nm technology node and beyond, new manufacturability problems are arising that strongly impact device and circuit behavior. Among these problems, line-edge and line-width roughness (LER and LWR) are of particular interest as dominant issues affecting parametric yield. In this paper, we investigate LWR effects by applying latest generation, full 3D TCAD technology including lithography simulation. In addition, our results answer open questions concerning the applicability of 2D slicing approximations vis a vis a 3D modeling effort. While LWR has been investigated by TCAD before, our methodology includes a full 3D process simulation (including lithography) without simplifications to generate the final transistor structures

Research paper thumbnail of A manufacturable shallow trench isolation process for 0.18 μm and beyond-optimization, stress reduction and electrical performance

An integrated shallow trench isolation process utilizing HDP (high density plasma) oxide and a hi... more An integrated shallow trench isolation process utilizing HDP (high density plasma) oxide and a highly manufacturable corner oxidation is described. The choice of trench corner oxidation temperature is shown to be critical in reducing silicon stress, and hence junction leakage, to the levels required by multi-million gate designs. This STI process is shown to be extremely robust and manufacturable. Optimal design of the trench depth and well profiles is shown to provide well-edge isolation adequate for sub-0.18 μm technologies

Research paper thumbnail of Bringing Manufacturing into Design via Process-Dependent SPICE Models

This paper describes methodology for constructing compact SPICE models as a function of process p... more This paper describes methodology for constructing compact SPICE models as a function of process parameter variations. The methodology involves global extraction of process-dependant SPICE model parameters from silicon calibrated TCAD simulations. The model is validated by comparing device characteristics from the extracted SPICE parameters with those from TCAD simulations. The analysis demonstrates an excellent goodness of fit over the full

Research paper thumbnail of Exploring the limits of stress-enhanced hole mobility

IEEE Electron Device Letters, 2005

Hole mobility is found to more than double in fabricated p-MOSFETs with SiGe source/drain due to ... more Hole mobility is found to more than double in fabricated p-MOSFETs with SiGe source/drain due to longitudinal compressive stress in the channel exceeding 1 GPa. The maximum observed low-field mobility enhancement is 140% at a simulated stress level of 1.45 GPa. The mobility enhancement is approximately linear with stress at moderate levels but becomes super-linear above 1 GPa. An important consequence of this behavior is that for moderate stress levels, an average channel stress can be used to estimate the performance of transistors with a nonuniform stress distribution across the channel width. Two alternative approaches to model stress-enhanced hole mobility are suggested. Analysis of the physical effects behind the experimental observations reveals the relative roles of band repopulation and mass modulation. In addition, previously published wafer bending experiments with compressive stress levels below 400 MPa are used to implicitly verify the accuracy of the stress simulations.

Research paper thumbnail of A systematic study of trade-offs in engineering a locally strained pMOSFET

We present the results of a study on the impact of process parameters on the performance of strai... more We present the results of a study on the impact of process parameters on the performance of strain enhanced pMOSFETs with recessed SiGe S/D. Recess depth, channel length, layout sensitivity, and their subsequent impact on strain and hole mobility are explored. Micro-Raman spectroscopy (μRS), process simulations, device simulations, and electrical results are presented. A 30% improvement in drive current is demonstrated.

Research paper thumbnail of The Impact of Layout on Stress-Enhanced Transistor Performance

This paper studies the sensitivity of stress-enhanced transistor performance to layout variations... more This paper studies the sensitivity of stress-enhanced transistor performance to layout variations. Stress simulations and mobility models are calibrated and verified for test structures with SiGe source/drain as a stressor. The role of STI on the stress transfer is explored. The numerical results show that variations of 15% in drive currents and of 44% in hole mobility due to layout induced stress variations can occur in the cases studied. These deviations need to be taken into account in circuit design or to be compensated via layout modification.

Research paper thumbnail of Trends, demands and challenges in TCAD

Materials Science and Engineering B-advanced Functional Solid-state Materials, 2005

Currently, TCAD is most heavily used in the device research and process integration phases of a t... more Currently, TCAD is most heavily used in the device research and process integration phases of a technology life cycle. However, a major trend visible in the industry is the demand to apply TCAD tools far beyond the integration phase into manufacturing and yield optimization. Short IC product lifetimes make fast yield ramp-up critical for being profitable and TCAD tools build a bridge between IC design and manufacturing. Another major trend is to use TCAD to evaluate layout dependent stress variations and account for these variations in the design flow of standard cells, libraries and custom ICs. This article gives an overview of those trends and addresses resulting challenges for TCAD models and tools.

Research paper thumbnail of Stress-Aware Design Methodology

Sub-90 nm CMOS circuits contain a significant amount of mechanical stress in active silicon. This... more Sub-90 nm CMOS circuits contain a significant amount of mechanical stress in active silicon. This stress is generated by a variety of intentional and unintentional stress sources. Shallow trench isolation is an example of an unintentional stress source, whereas embedded SiGe in the source and drain is an example of an intentional stress source. The amount of stress in each transistor in the circuit depends on the shape of its diffusion area as well as the density of the adjacent layout. The resulting non-uniform stress distribution alters individual transistor performance and, ultimately, the behavior of the circuit. In this paper, several examples are used to illustrate this effect based on design rules for the 45 nm technology node. A number of alternative approaches are suggested for partially suppressing or completely eliminating the stress-induced performance variations.

Research paper thumbnail of Optimizing boron junctions through point defect and stress engineering using carbon and germanium co-implants

Applied Physics Letters, 2005

Optimizing boron junctions through point defect and stress engineering using carbon and germanium... more Optimizing boron junctions through point defect and stress engineering using carbon and germanium co-implants. [Applied Physics Letters 87, 051908 (2005)]. Victor Moroz, Yong-Seog Oh, Dipu Pramanik, Houda Graoui, Majeed A. Foad. Abstract. ...