Ehsan Rohani | Texas A&M University (original) (raw)

Papers by Ehsan Rohani

In this paper we introduce the algorithm and the fixed point hardware to calculate the normalized... more In this paper we introduce the algorithm and the fixed point hardware to calculate the normalized singular value decomposition of a non-symmetric matrices using Givens fast (approximate) rotations. This algorithm only uses the basic combinational logic modules such as adders, multiplexers, encoders, Barrel shifters (B-shifters), and comparators and does not use any lookup table. This method in fact combines the iterative properties of singular value decomposition method and CORDIC method in one single iteration. The introduced architecture is a systolic architecture that uses two different types of processors, diagonal and non-diagonal processors. The diagonal processor calculates, transmits and applies the horizontal and vertical rotations, while the non-diagonal processor uses a fully combinational architecture to receive, and apply the rotations. The diagonal processor uses priority encoders, Barrel shifters, and comparators to calculate the rotation angles. Both processors use a...

In this paper, we report an issue first observed when using block-floating-point calculations in ... more In this paper, we report an issue first observed when using block-floating-point calculations in a time equalizer of an ADSL modem. We believe this important phenomenon have been out of the sight of researchers till now; and show that neglecting this issue may increase the round-off error significantly and reduce the SNR of a system. The simulation results suggest that ignoring this issue may increase RMS of errors by a factor of 2 in an equalizer. Then, we present two different methods for correcting this error. We use a FIR filter with 16 taps whose coefficients are set with Chow algorithm for equalizing an ADSL channel, using block-floating-point structure. We observed that for 3.3% of the inputs, the error of rounding is greater than error of truncation. By curing this issue, truncation error remains always above rounding error, as expected. As well, the RMS of the overall error is reduced by 17%.

2020 Intermountain Engineering, Technology and Computing (IETC), 2020

A DNA computer requires DNA processor. A fundamental component of the processor is an arithmetic ... more A DNA computer requires DNA processor. A fundamental component of the processor is an arithmetic logic unit (ALU). The ALU performs all arithmetic operations in binary format, and the most critical operation is two's complement addition, which can involve addition, subtraction, multiplication, and division. Two's complement adders can be synthesized using multiple full adders. In this paper, a noise-resistant DNA computing full adder circuit is presented. The proposed adder circuit, unlike other circuits, takes strands as inputs and produces the results in the form of DNA strands. This is an important characteristic, since it enables multiple-level design. In addition, since all possible hybridization in this circuit is desired, it can control an abundance of unwanted strands. As a result, the synthesized adder is noise-resistant. While other multi-level designs might be possible (e.g., Nor-Nor design), the proposed design implements the full adder circuit as an integrated g...

This paper is an analytical literature review on the dilemma of error-tolerance (ET) in IC manufa... more This paper is an analytical literature review on the dilemma of error-tolerance (ET) in IC manufacturing industry. The ET has a vast definition in research but, we mainly fuscous on the result acceptability of the the chips that generate erroneous outputs to increase the yield. The source of these errors is fabrication process (process variation or defects). The idea lies behind this question, what if a device is occasionally generating erroneous results but the results are in an acceptable range. Although the idea is simple but there are challenges to overcome (what is the acceptable range, how do we measure the range of error, and how to redesign a system to reduce sensitivity to the faults). But, the most challenging concern is to convince the IC designers that not all the output results need to be perfect and addressing the advertising and marketing issues that this new dilemma arises.

International Journal of Computer and Communication Engineering, 2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014

Applied Mechanics and Materials, 2014

Manufacturing and operation of wireless systems require a practical solution for achieving low-po... more Manufacturing and operation of wireless systems require a practical solution for achieving low-power and high-performance when using advance communication apparatus such as that using multiple-input and multiple-output (MIMO). Often algorithm solutions achieve very high performance but over only in a narrow range of operating parameters. This paper presents a hardware design of MIMO detection that allows real-time switching between various algorithms and detection effort to achieve high performance over the wide-range of signal to noise ratio (SNR) found in realistic operating conditions. We illustrate a design with over 80% reduction in detection power that satisfies the required quality of service (QoS) in SNRs (Eb/No) as low as 8.7 dB.

Analog Integrated Circuits and Signal Processing, 2015

This paper presents a novel asynchronous design approach for multiple input multiple output (MIMO... more This paper presents a novel asynchronous design approach for multiple input multiple output (MIMO) satellite communication (SatCom) systems. One of the main challenges for MIMO SatCom systems is that these are prone to transient faults that typically are attributable to radiation hazards. Hence, instead of using conventional synchronous circuits, we conceive our design using asynchronous circuits since it inherently has a high tolerance to transient fault. Additionally, we adopt accelerated dual paths (ADP) design into our system. By carefully arranging the data flow between the two paths, the ADP design approach can help to further accelerate the asynchronous system and increase the reliability of the system by circumventing transient faults induced delay, as well as tolerating latch-ups and other permanent faults. The numerical results show that this design approach provides promising results. For example, the proposed design can decrease the delay overhead of the entire system from 43.5 to 19.8 % at the fault rate of 400/clock cycle.

2014 48th Asilomar Conference on Signals, Systems and Computers, 2014

This paper presents a low-density parity-check (LDPC) decoder design that uses scalable-precision... more This paper presents a low-density parity-check (LDPC) decoder design that uses scalable-precision calculation (SPC) and asynchronous circuit techniques to reduce power consumption. The decoder configures the computation precision to minimize circuit-level switching necessary for given target biterror rate (FER). The asynchronous circuit approach guarantees the completion of each compute-and-forward phase at necessary voltage levels. The voltage level is scheduled to ensure completion of minimum necessary decoding iterations. The proposed scheme is studied for the specific application of IEEE 802.16e to reduce the power consumption at a given target FER. The proposed design is evaluated on Nangate 45nm library. The results show that the proposed asynchronous design results in 51% reduction in terms of power consumption compared with full-precision decoding mode.

2014 48th Asilomar Conference on Signals, Systems and Computers, 2014

This paper presents an iterative soft decision based adaptive K-best multiple-input-multiple-outp... more This paper presents an iterative soft decision based adaptive K-best multiple-input-multiple-output (MIMO) decoding algorithm. It has the flexibility of changing the list size, K with respect to the channel condition, although the accurate measurement of signal to noise ratio (SNR) is not required. Moreover, the concept of iterative soft decision based lattice reduction (LR)aided minimum mean square error (MMSE) extended K-best decoder is applied instead of conventional hard decision based K-best algorithm to reduce computational complexity to a great extent. It is found that the ratio of the minimum path metric to the second minimum can provide reliable estimation of channel condition. Hence, in the proposed algorithm, K is changed adaptively with respect to the ratio. Using this method with less number of K, we can obtain similar performance compared to the conventional LR-aided K-best algorithm operating with maximum list size of 64. Comparing to the fourth iteration of iterative soft decision based least sphere decoding (LSD), the proposed method with less K achieves 1.6 dB improvement at the bit error rate (BER) of 10-6 • Therefore, similar performance can be obtained by the proposed adaptive K-best algorithm with less computational complexity of the tree search decoder.

2015 International Conference on Computing, Networking and Communications (ICNC), 2015

This paper presents a performance analysis of soft decision based Lattice Reduction (LR) aided Sc... more This paper presents a performance analysis of soft decision based Lattice Reduction (LR) aided Schnorr-Euchner (SE) multiple-input-multiple-output (MIMO) detection algorithm with that of a hard one. We develop an advanced soft decoding scheme, for 4×4 MIMO with different modulation schemes and it provides 1.3 to 1.5 dB improvement compared to the LR-aided hard decision based detection method. The optimum parameters for K and saturation limit are further derived using extensive simulation. In the conventional K-best algorithm limiting the LLR values is not beneficiary in reducing the optimum size of candidate list, whereas applying the saturation limit on the LLR values in LR-aided algorithm will result in more than 8x reduction in list size as well as in the complexity of detector and LLR calculation unit.

Asphalt Pavements, 2014

With the increasing emphasis on renewable resources and green technologies, energy harvesting fro... more With the increasing emphasis on renewable resources and green technologies, energy harvesting from asphalt pavement has gained momentous attention in the recent years. Thermoelectric energy harvesting is one of the promising methods for collecting and transmitting solar energy into electrical power using temperature gradient along the pavement depth. However, the low energy conversion efficiency must be mitigated in order for this method to be viable for various practical applications. Henceforth, the objectives of this study are to investigate the key factors affecting the energy conversion efficiency and to derive optimal mechanical and circuit configurations. The goal is to compose a thermoelectric energy harvesting system tailored for the pavement application. The design under study is typical and it consists of a thermoelectric generator and thermally conductive rods for transferring heat. The effects of the generator type, circuit design, the shape of the conductive rod, and its insulation are investigated. The results indicate that the controlling of the heat transfer from the pavement to the thermoelectric generator is central to effective thermoelectric energy harvesting. Among the tested thermoelectric systems, the best device configuration yielded 42 mW; about 26 times higher power than the default case in this study.

This paper presents a very-large-scale integration (VLSI) design to reconstruct compressively sen... more This paper presents a very-large-scale integration (VLSI) design to reconstruct compressively sensed data. The proposed digital design recovers signal compressed by specific analog-to-digital converter (ADC). Our design is based on a modified iterative hard threshold (IHT) reconstruction algorithm to adapt unknown and varying degree of sparsity of the signal. The algorithm is composed empirically and implemented in a hardware-friendly fashion. The reconstruction fidelity using fixedpoint hardware model is analyzed. The design is synthesized using Synopsys Design Compiler with TSMC 45nm standard cell library. The post-synthesis implementation consumes 165 mW and is able to reconstruct data with information sparsity of 4%, at equivalent sampling rate of 1 gigasample-per-second (GSPS).

In this paper, we report an issue first observed when using block-floating-point calculations in ... more In this paper, we report an issue first observed when using block-floating-point calculations in a time equalizer of an ADSL modem. We believe this important phenomenon have been out of the sight of researchers till now; and show that neglecting this issue may increase the round-off error significantly and reduce the SNR 1 of a system. The simulation results suggest that ignoring this issue may increase RMS 2 of errors by a factor of 2 in an equalizer. Then, we present two different methods for correcting this error. We use a FIR filter with 16 taps whose coefficients are set with Chow algorithm for equalizing an ADSL channel, using block-floating-point structure. We observed that for 3.3% of the inputs, the error of rounding is greater than error of truncation. By curing this issue, truncation error remains always above rounding error, as expected. As well, the RMS of the overall error is reduced by 17%.

Drowsiness presents major safety concerns for tasks that require long periods of focus and alertn... more Drowsiness presents major safety concerns for tasks that require long periods of focus and alertness. While there is a body of work on drowsiness detection using EEG signals in neuroscience and engineering, there exist unanswered questions pertaining to the best mechanisms to use for detecting drowsiness. Targeting a range of practical safety-awareness applications, this study adopts a machine learning based approach to build support vector machine (SVM) classifiers to distinguish between awake and drowsy states. While broadband alpha, beta, delta, and theta waves are often used as features in the existing work, lack of widely agreed precise definitions of such broadband signals and difficulty in accounting for interpersonal variability has led to poor classification performance as demonstrated in this study. Furthermore, the transition from wakefulness to drowsiness and deeper sleep stages is a complex multifaceted process. The richness of this process calls for inclusion of sub-band features for more accurate drowsiness detection. To shed light on the effectiveness of sub-banding, we quantitatively compare the performances of a large set of SVM classifiers trained upon a varying number of 1Hz subband features. More importantly, we identify a compact set of neuroscientifcally motivated EEG features and demonstrate that the resulting classifier not only outperforms traditional broadband based classifiers but also is on a par with or superior than the best sub-band classifiers found by thorough search in a large space of 1Hz subband features.

2020 Intermountain Engineering, Technology and Computing (IETC), 2020

International Journal of Computer and Communication Engineering, 2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014

Applied Mechanics and Materials, 2014

Analog Integrated Circuits and Signal Processing, 2015

2014 48th Asilomar Conference on Signals, Systems and Computers, 2014

2015 International Conference on Computing, Networking and Communications (ICNC), 2015

Asphalt Pavements, 2014

In this paper, we report an issue first observed when using block-floating-point calculations in ... more In this paper, we report an issue first observed when using block-floating-point calculations in a time equalizer of an ADSL modem. We believe this important phenomenon have been out of the sight of researchers till now; and show that neglecting this issue may increase the round-off error significantly and reduce the SNR 1 of a system. The simulation results suggest that ignoring this issue may increase RMS 2 of errors by a factor of 2 in an equalizer. Then, we present two different methods for correcting this error. We use a FIR filter with 16 taps whose coefficients are set with Chow algorithm for equalizing an ADSL channel, using block-floating-point structure. We observed that for 3.3% of the inputs, the error of rounding is greater than error of truncation. By curing this issue, truncation error remains always above rounding error, as expected. As well, the RMS of the overall error is reduced by 17%.