Michael Dossis | TEI of Western Macedonia (original) (raw)

Books by Michael Dossis

Programming can be easy (as in Title) if instructed and taught properly. This book avoids unecess... more Programming can be easy (as in Title) if instructed and taught properly. This book avoids unecessary literature text and focuses on the main issues and problems encountered in computer programming.

Papers by Michael Dossis

2022 7th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM)

2022 7th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM)

Information, Apr 20, 2022

2020 5th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM)

High-level synthesis (HLS) has been an important tool in digital circuit design for more than two... more High-level synthesis (HLS) has been an important tool in digital circuit design for more than two decades, especially for processor components like accelerators or coprocessors. However, many high-level language characteristics have not been ported in such tools, under the false assumption that HLS programmers have a good understanding of hardware and of how actual circuits operate. This work is concentrated on the use of global and static variables in HLS. Such variables are often not allowed in HLS tools, since their storage class makes their support difficult. We will present an intelligent global and static variable placement methodology, which attempts to nullify the negative effects of supporting such variables, by carefully selecting variables to be placed globally, within an appropriate memory module. Addressing of such a module is direct, which allows the use of static pointers in the input high-level language code. We have implemented our methodology in the CCC HLS tool, and tested it with various benchmarks of varying complexity. We have also tested the same benchmarks with other popular HLS tools, and we show that under a fair comparison, CCC produces equal, or in some cases superior output to other tools with regard to global and static variable support.

2019 4th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM), 2019

In this work we consider a popular machine learning method, classification and regression trees. ... more In this work we consider a popular machine learning method, classification and regression trees. We discuss the algorithm and proceed in development from scratch, with hardware implementation in mind. We give our algorithm details, verify its correct functionality in GNU Ada and proceed with high level synthesis, via our CCC framework tool. Results validate our motivation for accelerated performance and device portability.

2019 4th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM), 2019

Traditional timing analysis techniques for microprocessor design are based on the static analysis... more Traditional timing analysis techniques for microprocessor design are based on the static analysis approach, in which clock frequency is set in accord with the worst-case delay in the processor circuit operation, regardless of the possible circuit inputs. Dynamic analysis approaches are calculating delays using varying circuit inputs, but are in general very slow. Recent approaches to static timing analysis are based on better-than-worst-case algorithms, which attempt to trade-off the pessimism of standard static analysis with the optimism of dynamic analysis.The work presented in this paper is concentrated on an enhanced implementation of static timing analysis for processor design, applying dynamic analysis through specific variations of circuit inputs. In particular, given that the circuit inputs are mostly instructions of the processor instruction set, we have chosen to vary the instruction opcode of that input. Thus, we have designed and implemented a timing analysis algorithm, which produces timing information for each instruction of the processor, allowing the designer to focus on improving the architecture of particular instructions rather than redesigning circuit parts.We have tested our algorithm on an OpenRISC processor design and collected timing information through an innovative use of the Synopsis PrimeTime tool. A comparison against timing information obtained through pure static timing analysis makes clear that our algorithm succeeds to give better-than-worst-case timing for the most common instructions, thus allowing the designer to deliver a better product.

25th Pan-Hellenic Conference on Informatics, 2021

Compilers apply transformations to the code they compile in order to make it run faster without c... more Compilers apply transformations to the code they compile in order to make it run faster without changing its behavior. This process is called code optimization. Modern compilers apply many different passes of code optimization to ensure maximum runtime performance and efficiency, at the rather negligible expense of larger compilation times. This study focuses on a particular optimization, called branchless optimization, which eliminates code branches by utilizing different data transformation techniques that have the same effect. Such techniques are explored on their implementation on the LLVM IR and MIPS and partly ARM assembly, and ranked based on their runtime efficiency. Moreover, the stages of implementing the optimization transformation are explored, as well as different instruction set features that some CPU architectures provide that can be used to increase the efficiency of the optimization.

24th Pan-Hellenic Conference on Informatics, 2020

Advances in silicon integration technology have allowed the emergence of extremely complex System... more Advances in silicon integration technology have allowed the emergence of extremely complex Systems-on-Chip and Application-Specific Integrated Circuits. This complexity impacted severely the verification time and effort of delayed products, that due to this they often miss the market window. Engineering teams have experienced exponential verification time increase with the linear complexity increase and the largest proportion of effort is due to segmented, long, tedious, bug-prone and repetitive low level verification. This work presents a High-level Synthesis – driven formal verification method, aimed in quickly verifying high-level software or hardware code which rapidly converges results from different abstraction levels in a formal design flow. First the benefits of formal techniques are explained and the proposed methodology is outlined. Then 4 converging aspects of our formal methodology, and namely high-level program code verification, cycle-accurate verification, RTL verific...

2020 5th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM), 2020

In a typical integrated circuit (IC) design flow, each step is executed sequentially, and valuabl... more In a typical integrated circuit (IC) design flow, each step is executed sequentially, and valuable feedback is provided that can be utilized if we are forced to backtrack as a means to resolve problems or satisfy design constraints and restrictions. Following a similar logic, the objective of our algorithm is to plan the I/O pad positions, based on back-annotated data gathered from a formerly placed similar design, concerning the cell connectivity and positioning, in order to minimize the total wirelength, a critical metric defining the routability, and thus the manufacturability of a design. Our approach results in the embetterment of the wirelength at an acceptable runtime.

Journal of Robotics and Mechanical Engineering Research, 2015

IEE Colloquium on Hardware-Software Cosynthesis for Reconfigurable Systems, 1996

The Handel hardware compilation language, is designed and used for hardware specification and syn... more The Handel hardware compilation language, is designed and used for hardware specification and synthesis in the Computing Laboratory of Oxford University. It is very similar to a subset of occam and a meta-language environment is utilized to map abstract program syntax trees of Handel into functionally equivalent hardware netlists. The Handel compilation represents itself a syntax-directed strategy for mapping sequential and parallel operations into a maximally parallel hardware datapath, via robust transformations of programs into their equivalent normal form program. The sequential and parallel sets include RTL occam-like assignments. These features allow the circuit designers/programmers to exercise absolute control on the intended architectures, via rescheduling and/or modification of their Handel code so as to meet the various size/performance targets. (16 pages)

IFIP Advances in Information and Communication Technology, 1999

Programming can be easy (as in Title) if instructed and taught properly. This book avoids unecess... more Programming can be easy (as in Title) if instructed and taught properly. This book avoids unecessary literature text and focuses on the main issues and problems encountered in computer programming.

2022 7th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM)

2022 7th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM)

Information, Apr 20, 2022

2020 5th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM)

High-level synthesis (HLS) has been an important tool in digital circuit design for more than two... more High-level synthesis (HLS) has been an important tool in digital circuit design for more than two decades, especially for processor components like accelerators or coprocessors. However, many high-level language characteristics have not been ported in such tools, under the false assumption that HLS programmers have a good understanding of hardware and of how actual circuits operate. This work is concentrated on the use of global and static variables in HLS. Such variables are often not allowed in HLS tools, since their storage class makes their support difficult. We will present an intelligent global and static variable placement methodology, which attempts to nullify the negative effects of supporting such variables, by carefully selecting variables to be placed globally, within an appropriate memory module. Addressing of such a module is direct, which allows the use of static pointers in the input high-level language code. We have implemented our methodology in the CCC HLS tool, and tested it with various benchmarks of varying complexity. We have also tested the same benchmarks with other popular HLS tools, and we show that under a fair comparison, CCC produces equal, or in some cases superior output to other tools with regard to global and static variable support.

2019 4th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM), 2019

In this work we consider a popular machine learning method, classification and regression trees. ... more In this work we consider a popular machine learning method, classification and regression trees. We discuss the algorithm and proceed in development from scratch, with hardware implementation in mind. We give our algorithm details, verify its correct functionality in GNU Ada and proceed with high level synthesis, via our CCC framework tool. Results validate our motivation for accelerated performance and device portability.

2019 4th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM), 2019

Traditional timing analysis techniques for microprocessor design are based on the static analysis... more Traditional timing analysis techniques for microprocessor design are based on the static analysis approach, in which clock frequency is set in accord with the worst-case delay in the processor circuit operation, regardless of the possible circuit inputs. Dynamic analysis approaches are calculating delays using varying circuit inputs, but are in general very slow. Recent approaches to static timing analysis are based on better-than-worst-case algorithms, which attempt to trade-off the pessimism of standard static analysis with the optimism of dynamic analysis.The work presented in this paper is concentrated on an enhanced implementation of static timing analysis for processor design, applying dynamic analysis through specific variations of circuit inputs. In particular, given that the circuit inputs are mostly instructions of the processor instruction set, we have chosen to vary the instruction opcode of that input. Thus, we have designed and implemented a timing analysis algorithm, which produces timing information for each instruction of the processor, allowing the designer to focus on improving the architecture of particular instructions rather than redesigning circuit parts.We have tested our algorithm on an OpenRISC processor design and collected timing information through an innovative use of the Synopsis PrimeTime tool. A comparison against timing information obtained through pure static timing analysis makes clear that our algorithm succeeds to give better-than-worst-case timing for the most common instructions, thus allowing the designer to deliver a better product.

25th Pan-Hellenic Conference on Informatics, 2021

Compilers apply transformations to the code they compile in order to make it run faster without c... more Compilers apply transformations to the code they compile in order to make it run faster without changing its behavior. This process is called code optimization. Modern compilers apply many different passes of code optimization to ensure maximum runtime performance and efficiency, at the rather negligible expense of larger compilation times. This study focuses on a particular optimization, called branchless optimization, which eliminates code branches by utilizing different data transformation techniques that have the same effect. Such techniques are explored on their implementation on the LLVM IR and MIPS and partly ARM assembly, and ranked based on their runtime efficiency. Moreover, the stages of implementing the optimization transformation are explored, as well as different instruction set features that some CPU architectures provide that can be used to increase the efficiency of the optimization.

24th Pan-Hellenic Conference on Informatics, 2020

Advances in silicon integration technology have allowed the emergence of extremely complex System... more Advances in silicon integration technology have allowed the emergence of extremely complex Systems-on-Chip and Application-Specific Integrated Circuits. This complexity impacted severely the verification time and effort of delayed products, that due to this they often miss the market window. Engineering teams have experienced exponential verification time increase with the linear complexity increase and the largest proportion of effort is due to segmented, long, tedious, bug-prone and repetitive low level verification. This work presents a High-level Synthesis – driven formal verification method, aimed in quickly verifying high-level software or hardware code which rapidly converges results from different abstraction levels in a formal design flow. First the benefits of formal techniques are explained and the proposed methodology is outlined. Then 4 converging aspects of our formal methodology, and namely high-level program code verification, cycle-accurate verification, RTL verific...

2020 5th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM), 2020

In a typical integrated circuit (IC) design flow, each step is executed sequentially, and valuabl... more In a typical integrated circuit (IC) design flow, each step is executed sequentially, and valuable feedback is provided that can be utilized if we are forced to backtrack as a means to resolve problems or satisfy design constraints and restrictions. Following a similar logic, the objective of our algorithm is to plan the I/O pad positions, based on back-annotated data gathered from a formerly placed similar design, concerning the cell connectivity and positioning, in order to minimize the total wirelength, a critical metric defining the routability, and thus the manufacturability of a design. Our approach results in the embetterment of the wirelength at an acceptable runtime.

Journal of Robotics and Mechanical Engineering Research, 2015

IEE Colloquium on Hardware-Software Cosynthesis for Reconfigurable Systems, 1996

The Handel hardware compilation language, is designed and used for hardware specification and syn... more The Handel hardware compilation language, is designed and used for hardware specification and synthesis in the Computing Laboratory of Oxford University. It is very similar to a subset of occam and a meta-language environment is utilized to map abstract program syntax trees of Handel into functionally equivalent hardware netlists. The Handel compilation represents itself a syntax-directed strategy for mapping sequential and parallel operations into a maximally parallel hardware datapath, via robust transformations of programs into their equivalent normal form program. The sequential and parallel sets include RTL occam-like assignments. These features allow the circuit designers/programmers to exercise absolute control on the intended architectures, via rescheduling and/or modification of their Handel code so as to meet the various size/performance targets. (16 pages)

IFIP Advances in Information and Communication Technology, 1999

2009 Fourth International Workshop on Semantic Media Adaptation and Personalization, 2009

The design and implementation of today's complex embedded systems including custo... more The design and implementation of today's complex embedded systems including custom hardware and software is still to a large extent based on a collaboration of heterogeneous, semi-manual and often poorly inter-connected design methods and tools. This usually results in repetitive and longer development cycles. This paper describes an intelligent web service to automatically produce non-standard and custom hardware description code,

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

Page 1. 229 Synthesis Of Customised Hardware From ADA Michael F. Dossis James M. Noras Gary J. Po... more Page 1. 229 Synthesis Of Customised Hardware From ADA Michael F. Dossis James M. Noras Gary J. Porter Department of Electronic and Electrical Engineering The University BRADFORD BD7 1DP United Kingdom (+44) 274 384036 M. Dossis@bradford.ac.uk ABSTRACT ...

Applied Intelligence, 2022

2018 41st International Conference on Telecommunications and Signal Processing (TSP), 2018

Academic High-level Synthesis tools like CustomCoprocessorsCompiler have recently evolved in new ... more Academic High-level Synthesis tools like CustomCoprocessorsCompiler have recently evolved in new versions with expanded functionality and more aggressive optimization schemes in order to satisfy hardware implementation requirements. Meanwhile, commercial tools like Xilinx VivadoHLS or, more recently, Compiler-driven code optimizations, are a useful means to improve quality of automatically generated hardware implementations. Such optimizations include loop transformations. Some of the most important transformations are loop unrolling and loop pipelining, which when they are combined with careful instruction reordering, deliver highly optimized schedules. Amongst others, instruction dependencies are significant limitations in loop optimization. In this paper, we discuss possible resolutions of loop pipelining issues such as dealing with dependencies between loop body operations. This has a great impact on high-level synthesis. Results from experiments with several benchmarks on the C...