Panayiotis Alefragis | TECHNOLOGICAL INSTITUTE OF MESSOLOGHI (original) (raw)
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Papers by Panayiotis Alefragis
ReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings, 2012
Abstract The mapping process of high performance embedded applications to today's re... more Abstract The mapping process of high performance embedded applications to today's reconfigurable multiprocessor System-on-Chip devices suffers from a complex toolchain and programming process. Thus, the efficient programming of such architectures in terms of achievable performance and power consumption is limited to experts only. Enabling them to nonexperts requires a simplified programming process that hides the complexity of the underlying hardware—introduced by software parallelism of multiple cores and the ...
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Proceedings - 2012 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2012, 2012
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ABSTRACT A computer program can be represented by a Directed Acyclic Graph (DAG) in order to capt... more ABSTRACT A computer program can be represented by a Directed Acyclic Graph (DAG) in order to capture the dependencies between the individual tasks that should be executed each time the program runs. This paper proposes a mathematical model of Integer Programming that can be applied in order to schedule the tasks in the presence of multiple processors serving as the execution environment. The target is to minimize the overall execution time of the DAG known as schedule length or makespan. An approach called MATH using the full model is applied to small sized problems and then a more elaborate approach called MATHL is presented where the DAG is partitioned to levels. Levels are formed according to the hops needed for each node to be reached starting from the source node. Hence sub-problems have manageable size and can be solved in a timely manner. Consecutive optimal solutions for each level result in a high quality schedule for the overall problem even for cases consisting of several hundreds of nodes. Results show that this method constantly gives very good results and it is compared favorably with other approaches to the problem that can be found in the bibliography.
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2013 11th IEEE International Conference on Industrial Informatics (INDIN), 2013
ABSTRACT There is an increasing need for automatic tools and techniques for application paralleli... more ABSTRACT There is an increasing need for automatic tools and techniques for application parallelization. Within the ALMA toolset, programs written in Scilab are automatically parallelized for execution on embedded multicore platforms. In this paper, key parts of the coarse grain parallelism optimization are presented. The coarse grain parallelism optimization considers the hierarchical task graph of a program and produces an optimized parallel schedule.
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ABSTRACT As processors and systems-on-chip increasingly become multicore, parallel programming re... more ABSTRACT As processors and systems-on-chip increasingly become multicore, parallel programming remains a difficult, time-consuming and complicated task. End users who are not parallel programming experts have a need to exploit such processors and architectures, using state of the art fourth generation of high programming languages, like Scilab or MATLAB. The ALMA toolset addresses this problem by receiving Scilab code as input and produces parallel code for embedded multiprocessor systems on chip, using platform quasi-agnostic optimisations. In this paper, coarse grain parallelism extraction and optimization issues as well as parallel code generation for the ALMA toolset are discussed.
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ABSTRACT In this paper, the coarse grained parallelism optimization step of the ALMA EU FP7 proje... more ABSTRACT In this paper, the coarse grained parallelism optimization step of the ALMA EU FP7 project is discussed. The current results look promising, as the possibility to use Integer Programming and provide optimal results to the problem model seems feasible and efficient.
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Proceedings - 2012 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2012, 2012
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ReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings, 2012
Abstract The mapping process of high performance embedded applications to today's re... more Abstract The mapping process of high performance embedded applications to today's reconfigurable multiprocessor System-on-Chip devices suffers from a complex toolchain and programming process. Thus, the efficient programming of such architectures in terms of achievable performance and power consumption is limited to experts only. Enabling them to nonexperts requires a simplified programming process that hides the complexity of the underlying hardware—introduced by software parallelism of multiple cores and the ...
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Algorithms, 2014
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International E-Conference of Computer Science 2006~ autofilled~
Abstract: Wireless Sensor Networks (WSN) are a module that can be added to any existing informati... more Abstract: Wireless Sensor Networks (WSN) are a module that can be added to any existing information system in order to extend it's capabilities by capturing and transmitting a dense amount of raw data from the application field back to a central computing system. Depending on the nature of the application, a known and measured level of security must be accomplished. Taking into account the fact that today's security approaches aggravate existing power limitations that are implied by WSN design, the need to establish an ...
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Abstract Today's reconfigurable multicore architectu... more Abstract Today's reconfigurable multicore architectures become more and more complex. They consist of several processing units, not necessarily identical, different interconnecting modules, memories and possibly other components. Programming such kind of architectures requires deep knowledge of the underlying hardware and is thus very time consuming and error prone. On the other hand, automated tool chains that target multicore architectures are typically tailored to one specific architecture type and require a platform- ...
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Microprocessors and Microsystems, 2013
ABSTRACT The mapping process of high performance embedded applications to today's multipr... more ABSTRACT The mapping process of high performance embedded applications to today's multiprocessor system-on-chip devices su�ers from a complex toolchain and programming process. The problem is the expression of parallelism with a pure imperative programming language which is commonly C. This traditional approach limits the mapping, partitioning and the generation of optimized parallel code, and consequently the achievable performance and power consumption of applications from di�erent domains. The Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of a Scilab-based toolchain which enables the e�cient mapping of applications on multiprocessor platforms from a high level of abstraction. The holistic solution of the ALMA toolchain allows the complexity of both the application and the architecture to be hidden, which leads to better acceptance, reduced development cost, and shorter time-to-market. Driven by the technology restrictions in chip design, the end of exponential growth of clock speeds, and an unavoidable increasing request of computing performance, ALMA is a fundamental step forward in the necessary introduction of novel computing paradigms and methodologies.
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Lecture Notes in Computer Science, 2014
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ReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings, 2012
Abstract The mapping process of high performance embedded applications to today's re... more Abstract The mapping process of high performance embedded applications to today's reconfigurable multiprocessor System-on-Chip devices suffers from a complex toolchain and programming process. Thus, the efficient programming of such architectures in terms of achievable performance and power consumption is limited to experts only. Enabling them to nonexperts requires a simplified programming process that hides the complexity of the underlying hardware—introduced by software parallelism of multiple cores and the ...
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Proceedings - 2012 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2012, 2012
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Bookmarks Related papers MentionsView impact
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ABSTRACT A computer program can be represented by a Directed Acyclic Graph (DAG) in order to capt... more ABSTRACT A computer program can be represented by a Directed Acyclic Graph (DAG) in order to capture the dependencies between the individual tasks that should be executed each time the program runs. This paper proposes a mathematical model of Integer Programming that can be applied in order to schedule the tasks in the presence of multiple processors serving as the execution environment. The target is to minimize the overall execution time of the DAG known as schedule length or makespan. An approach called MATH using the full model is applied to small sized problems and then a more elaborate approach called MATHL is presented where the DAG is partitioned to levels. Levels are formed according to the hops needed for each node to be reached starting from the source node. Hence sub-problems have manageable size and can be solved in a timely manner. Consecutive optimal solutions for each level result in a high quality schedule for the overall problem even for cases consisting of several hundreds of nodes. Results show that this method constantly gives very good results and it is compared favorably with other approaches to the problem that can be found in the bibliography.
Bookmarks Related papers MentionsView impact
2013 11th IEEE International Conference on Industrial Informatics (INDIN), 2013
ABSTRACT There is an increasing need for automatic tools and techniques for application paralleli... more ABSTRACT There is an increasing need for automatic tools and techniques for application parallelization. Within the ALMA toolset, programs written in Scilab are automatically parallelized for execution on embedded multicore platforms. In this paper, key parts of the coarse grain parallelism optimization are presented. The coarse grain parallelism optimization considers the hierarchical task graph of a program and produces an optimized parallel schedule.
Bookmarks Related papers MentionsView impact
ABSTRACT As processors and systems-on-chip increasingly become multicore, parallel programming re... more ABSTRACT As processors and systems-on-chip increasingly become multicore, parallel programming remains a difficult, time-consuming and complicated task. End users who are not parallel programming experts have a need to exploit such processors and architectures, using state of the art fourth generation of high programming languages, like Scilab or MATLAB. The ALMA toolset addresses this problem by receiving Scilab code as input and produces parallel code for embedded multiprocessor systems on chip, using platform quasi-agnostic optimisations. In this paper, coarse grain parallelism extraction and optimization issues as well as parallel code generation for the ALMA toolset are discussed.
Bookmarks Related papers MentionsView impact
ABSTRACT In this paper, the coarse grained parallelism optimization step of the ALMA EU FP7 proje... more ABSTRACT In this paper, the coarse grained parallelism optimization step of the ALMA EU FP7 project is discussed. The current results look promising, as the possibility to use Integer Programming and provide optimal results to the problem model seems feasible and efficient.
Bookmarks Related papers MentionsView impact
Proceedings - 2012 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2012, 2012
Bookmarks Related papers MentionsView impact
ReCoSoC 2012 - 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, Proceedings, 2012
Abstract The mapping process of high performance embedded applications to today's re... more Abstract The mapping process of high performance embedded applications to today's reconfigurable multiprocessor System-on-Chip devices suffers from a complex toolchain and programming process. Thus, the efficient programming of such architectures in terms of achievable performance and power consumption is limited to experts only. Enabling them to nonexperts requires a simplified programming process that hides the complexity of the underlying hardware—introduced by software parallelism of multiple cores and the ...
Bookmarks Related papers MentionsView impact
Algorithms, 2014
Bookmarks Related papers MentionsView impact
International E-Conference of Computer Science 2006~ autofilled~
Abstract: Wireless Sensor Networks (WSN) are a module that can be added to any existing informati... more Abstract: Wireless Sensor Networks (WSN) are a module that can be added to any existing information system in order to extend it's capabilities by capturing and transmitting a dense amount of raw data from the application field back to a central computing system. Depending on the nature of the application, a known and measured level of security must be accomplished. Taking into account the fact that today's security approaches aggravate existing power limitations that are implied by WSN design, the need to establish an ...
Bookmarks Related papers MentionsView impact
Bookmarks Related papers MentionsView impact
Abstract Today's reconfigurable multicore architectu... more Abstract Today's reconfigurable multicore architectures become more and more complex. They consist of several processing units, not necessarily identical, different interconnecting modules, memories and possibly other components. Programming such kind of architectures requires deep knowledge of the underlying hardware and is thus very time consuming and error prone. On the other hand, automated tool chains that target multicore architectures are typically tailored to one specific architecture type and require a platform- ...
Bookmarks Related papers MentionsView impact
Microprocessors and Microsystems, 2013
ABSTRACT The mapping process of high performance embedded applications to today's multipr... more ABSTRACT The mapping process of high performance embedded applications to today's multiprocessor system-on-chip devices su�ers from a complex toolchain and programming process. The problem is the expression of parallelism with a pure imperative programming language which is commonly C. This traditional approach limits the mapping, partitioning and the generation of optimized parallel code, and consequently the achievable performance and power consumption of applications from di�erent domains. The Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of a Scilab-based toolchain which enables the e�cient mapping of applications on multiprocessor platforms from a high level of abstraction. The holistic solution of the ALMA toolchain allows the complexity of both the application and the architecture to be hidden, which leads to better acceptance, reduced development cost, and shorter time-to-market. Driven by the technology restrictions in chip design, the end of exponential growth of clock speeds, and an unavoidable increasing request of computing performance, ALMA is a fundamental step forward in the necessary introduction of novel computing paradigms and methodologies.
Bookmarks Related papers MentionsView impact
Lecture Notes in Computer Science, 2014
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