Matthias Bucher | Technical University of Crete (original) (raw)

Papers by Matthias Bucher

2015 International Conference on Noise and Fluctuations (ICNF), 2015

f noise, submitted to ECCSC 2010 1 Abstract—Bias dependence and scaling of 1/f noise is an import... more f noise, submitted to ECCSC 2010 1 Abstract—Bias dependence and scaling of 1/f noise is an important subject for the design of analog/RF integrated circuits in scaled CMOS technology. In this paper, we report on the behavior of low frequency noise, including experimental characterization and compact modeling for NMOS and PMOS devices in 180nm CMOS technology. Aspects of bias dependence and scaling are examined. The compact model approach is based on the charge-based model, including carrier number fluctuation, mobility fluctuation and resistance fluctuation noise mechanisms. The low frequency noise model is related closely to the underlying charge-based model, and accounts for second-order effects such as mobility effects, velocity saturation and channel-length modulation effects. As a result, 1/f noise bias dependence and scaling is covered over a wide range of geometry and bias, ranging from long-to short-channel and weak to strong inversion conditions. Input referred noise shows ...

Solid-State Electronics, 1997

ABSTRACT This article presents a new model for the effect of the transverse non-uniform substrate... more ABSTRACT This article presents a new model for the effect of the transverse non-uniform substrate doping on the threshold voltage of MOS transistors. The new model is validated using 2D device simulations and measurements of a CMOS low-voltage process. A simple associated characterization method is also presented. The parameters related to the non-uniform doping are extracted from the pinch-off vs gate voltage characteristic, measured at constant current from a device biased in moderate inversion. (C) 1997 Elsevier Science Ltd.

... High-Frequency Model A general model for high-frequency small-signal operation [28, 31]is sho... more ... High-Frequency Model A general model for high-frequency small-signal operation [28, 31]is shown in Figure 6. The three voltage controlled current sources (VCCS) are defined as, Im = Ym · (V (gi) − V (bi)) Ims = Yms · (V (si) − V (bi)) (23) Imd = Ymd · (V (di) − V (bi)) ... gi si bi NQS ...

Solid-State Electronics, 2000

ABSTRACT Polysilicon gate depletion is an important effect that degrades the circuit performance ... more ABSTRACT Polysilicon gate depletion is an important effect that degrades the circuit performance of deep submicron standard CMOS technologies. A new approach to analytically modeling the polysilicon depletion effect on drain current and transconductances as well as node charges and transcapacitances is presented. The model is based on a clear physical analysis of the charges in the MOS transistor structure. Using the modeling framework and the fundamental variables of the EKV MOS transistor model formalism and that of the related charges models, a continuous model is achieved that is valid in all operating regions from weak inversion to strong inversion and from non-saturation to saturation. The asymptotic behavior of the transcapacitances is improved with respect to former model formulations. Only the doping concentration in the polygate is used in addition to the other physical device model parameters. The model shows excellent results in comparison with a surface potential based numerical model and 2D numerical device simulation. The model is efficient for circuit simulation and is further practical for analog circuit design.

physica status solidi (c), 2008

1 National Technical University of Athens, 15780 Athens, Greece 2 Technical University of Crete, ... more 1 National Technical University of Athens, 15780 Athens, Greece 2 Technical University of Crete, 73100 Chania, Greece 3 FPL, Semiconductor Physics Institute, 01108 Vilnius, Lithuania 4 Technical University of Dresden, 01069 Dresden, Germany 5 ECE Department, ...

International Journal of RF and Microwave Computer-Aided Engineering, 2008

ABSTRACT: This article presents a validation of the EKV3 MOSFET compact model dedicated to the de... more ABSTRACT: This article presents a validation of the EKV3 MOSFET compact model dedicated to the design of analogue/RF ICs using advanced CMOS technology. The EKV3 model is compared with DC, CV and RF measurements up to 20 GHz of a 110 nm CMOS technology. The ...

IEEE Transactions on Electron Devices, 2013

TechConnect Briefs, Jun 18, 2012

In this paper, analog/RF performance of new device architecture: graded channel dual material dou... more In this paper, analog/RF performance of new device architecture: graded channel dual material double gate (GCDMDG) is investigated using ATLAS device simulator. This configuration achieves higher drain current, peak transconductance and higher values of cutoff frequency at lower gate voltage along with better intrinsic gain for an amplifier. This unique configuration is favorable for gate length scaling.

arXiv (Cornell University), Jun 1, 2021

A MOSFET threshold voltage extraction method covering the entire range of drain-to-source voltage... more A MOSFET threshold voltage extraction method covering the entire range of drain-to-source voltage, from linear to saturation modes, is presented. Transconductance-to-current ratio is obtained from MOSFET transfer characteristics measured at low to high drain voltage. Based on the charge-based modeling approach, a near-constant value of threshold voltage is obtained over the whole range of drain voltage for ideal, long-channel MOSFETs. The method reveals a distinct increase of threshold voltage versus drain voltage for halo-implanted MOSFETs in the low drain voltage range. The method benefits from moderate inversion operation, where high-field effects, such as vertical field mobility reduction and series resistances, are minimal. The present method is applicable over the full range of drain voltage, is fully analytical, easy to be implemented, and provides more consistent results when compared to existing methods.

1. Introduction 2. Receiver architecture 3. Integrated mixers 4. Mixer simulation-results 5. Conc... more 1. Introduction 2. Receiver architecture 3. Integrated mixers 4. Mixer simulation-results 5. Conclusion-future work

EKV3 compact MOSFET model RF measurements in advanced RFCMOS 180nm RF CMOS

A method of interpreting MOSFET behavior is described which is more coherent for modern analog CM... more A method of interpreting MOSFET behavior is described which is more coherent for modern analog CMOS circuit design. This method supercedes the use of simple but antiquated equations in design, and replaces them with an approach based on the inversion coefficient of the individual transistors in the design. Measurements and modeling confirm that this method can be used directly to arbitrate among the various countervailing requirements of demanding analog designs.

The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial comm... more The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. The present paper provides a short review of foundations of the model and shows its capabilities via characterization and modeling based on a test chip in 180 nm CMOS fabricated via Europractice.

Analog/RF performance of nanoscale triple gate FinFETs and planar single gate and double gate SOI... more Analog/RF performance of nanoscale triple gate FinFETs and planar single gate and double gate SOI MOSFETs is examined via extensive 3D device simulations. Well-designed DG MOSFETs attain higher values of cutoff frequency for both lower and higher drain currents, whereas FinFETs offer higher intrinsic gain while compromising cutoff frequency. For longer channel lengths, SG MOSFETs show slightly higher cutoff frequency in comparison to multi-gate (MG) MOSFETs, whereas MG MOSFETs exhibit higher cutoff frequency for lower channel lengths. A unique figure of merit, gain transconductance frequency product (GTFP) for best trade-off among gain, transconductance, and speed is compared. DG MOSFETs exhibit higher GTFP over a wide range of device scaling, thus remain a good candidate for analog/RF applications. Furthermore, the RF linearity performance of these devices has been examined.

ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC), 2019

IEEE Journal of the Electron Devices Society, 2019

The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with... more The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of device fabrication but also its principle of operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Furthermore, co-integration of JFET with CMOS technology is attractive. Physicsbased compact models for JFETs are however scarce. In this paper, an analytical, charge-based model is established for the mobile charges, drain current, transconductances and transcapacitances of symmetric DG JFETs, covering all regions of device operation, continuously from subthreshold to linear and saturation operation. This charge-based JFET model (called CJM) constitutes the basis of a full compact model of the DG JFET for analog, RF, and digital circuit simulation.

IEEE Transactions on Electron Devices, 2018

We present a unified charge-based model for double-gate and cylindrical architectures of junction... more We present a unified charge-based model for double-gate and cylindrical architectures of junction fieldeffect transistors (JFETs). The central concept is to consider the JFET as a junctionless FET (JLFET) with an infinitely thin insulating layer, leading to analytical expressions between charge densities, current, and voltages without any fitting parameters. Assessment of the model with numerical technology computer-aided design simulations confirms that holding the JFET as a special case of the JLFET is justified in all the regions of operation, i.e., from deep depletion to flat-band and from linear to saturation. Index Terms-Cylindrical gate all around junction fieldeffect transistor (JFET), double-gate FETs, nanowire FETs, power semiconductor FETs, radiation-hard electronics, vertical JFET (V-JFET).

IEEE Transactions on Electron Devices, 2016

Variability of low frequency noise (LFN) in MOSFETs is bias-dependent. Moderate-to large-sized tr... more Variability of low frequency noise (LFN) in MOSFETs is bias-dependent. Moderate-to large-sized transistors commonly used in analog/RF applications show 1/f-like noise spectra, resulting from the superposition of random telegraph noise (RTN). Carrier number and mobility fluctuations are considered as the main causes of low frequency noise. While their effect on the bias-dependence of LFN has been well investigated, the way these noise mechanisms contribute to the bias-dependence of variability of LFN has been less well understood. LFN variability has been shown to be maximized in weak inversion (sub-threshold), while increased drain bias also increases LFN variability. However, no compact model has been proposed to explain this bias-dependence in detail. In combination with the charge-based formulation of LFN, the present paper proposes a new model for bias-dependence of LFN variability. Comparison with experimental data from moderately-sized NMOS and PMOS transistors at all bias conditions provides insight into how carrier number and mobility fluctuation mechanisms impact the bias-dependence of LFN variability.