Martin Rack | UCLouvain (University of Louvain) (original) (raw)

Papers by Martin Rack

2023 Symposium on Design, Test, Integration & Packaging of MEMS/MOEMS (DTIP)

Solid-state Electronics, Jun 1, 2020

In this paper, small-and large-signal performances of passive devices integrated on high-resistiv... more In this paper, small-and large-signal performances of passive devices integrated on high-resistivity, trap-rich and gold-doped silicon wafers are presented and compared through measurements and simulations. The gold-doped silicon substrate was produced starting from standard silicon having a nominal resistivity of 56 Ω.cm. We show that the gold-doped substrate presents high effective resistivity and low losses suitable for RF applications, this has been done by measuring coplanar waveguides, crosstalk, inductors and band pass filter where we saw a similar performances under small signal-measurements. Largesignal measurements of gold-doped substrates show 60 dBm lower harmonic distortion than high-resistivity substrates, and 10 dB lower than trap-rich substrate. A large DC bias dependence on the harmonic distortion induced by the gold-doped substrate is observed. This unexpected behavior is explained using the Fermi level localization in the silicon bandgap for the different DC bias conditions.

IEEE Electron Device Letters, Apr 1, 2023

IEEE Journal of the Electron Devices Society, 2022

This paper focuses on the comparison of various advanced substrates such as trap-rich (TR), porou... more This paper focuses on the comparison of various advanced substrates such as trap-rich (TR), porous silicon (PSi), gold-doped (Au-Si) and smart-implants PN-junction (DP) in terms of RF performances. Both small-and large-signal measurements were performed, including the study of the influence of temperature and DC bias voltage. The purpose of this paper is to provide an overview, and a more in-depth analysis of DP substrate, of the characteristics of these multiple substrates to facilitate design choices for RF-IC applications. INDEX TERMS Silicon-on-Insulator (SOI) technology, effective resistivity, trap-rich (TR) substrate, Parasitic Surface Conduction (PSC), RF characterization, RF substrate, harmonic distortion (HD), gold-doped silicon substrate (Au-Si), high temperature.

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IEEE Transactions on Electron Devices, 2023

IEEE Journal of the Electron Devices Society, 2023

Advances in CMOS technology have enabled MOSFET with cutoff and maximum oscillation frequencies (... more Advances in CMOS technology have enabled MOSFET with cutoff and maximum oscillation frequencies (ft and fmax) in the 400 GHz range, thus opening the path to CMOSbased applications at millimeter-wave (mm-wave) and sub-THz frequencies. Accurate compact models and therefore on-wafer MOSFET measurements at mm-wave frequencies and beyond become crucial for IC design at such high frequencies. However, accurate on-wafer measurement at these frequencies is a complex task requiring dedicating special care to calibration kit (calkit) design and characterization. This paper presents a complete and detailed parasitic correction procedure approach that demonstrates accurate corrected MOSFET measurements up to 110 GHz. It describes the custom calkit designed to perform 'in-situ' multiline Thru-Reflect-Line (mTRL) calibration. In this work, we compare different methods to evaluate the transmission line standards characteristic impedance and identify the best one by comparing the extracted series resistances of a MOSFET. The best method features frequency variations as low as <5% and <20% in source-drain and gate resistances, respectively, up to 110 GHz. Finally, by applying the most suited correction procedure to measurements of different RF probe technologies and comparing them to compact model simulations, we demonstrated high-accuracy FET measurements up to 110 GHz, thanks to an excellent agreement between the probe data and simulations, even in presence of probe-dependent residual errors.

Solid-state Electronics, Jul 1, 2023

2022 24th International Microwave and Radar Conference (MIKON), Sep 12, 2022

Solid-state Electronics, Aug 1, 2022

In this paper, the dependence of substrate effective resistivity on device dimensions is investig... more In this paper, the dependence of substrate effective resistivity on device dimensions is investigated through the measurements and simulations of CPW lines integrated on commercial flavors of high-resistivity (HR) and trap-rich (TR) wafers. It is shown that inhomogeneous resistivity profiles are responsible for the strong dependence of the effective resistivity parameter on device dimensions, up to a factor of 4 on TR substrates and up to a factor of 20 on HR substrates.

IEEE Transactions on Electron Devices

2023 21st IEEE Interregional NEWCAS Conference (NEWCAS)

Meeting abstracts, Jul 7, 2022

2022 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS)