Hussam Mousa | University of California, Santa Barbara (original) (raw)
Papers by Hussam Mousa
Understanding workload performance and resource utilization under full system virtualization is c... more Understanding workload performance and resource utilization under full system virtualization is challenging because of the additional Virtual Machine Monitor layer, the sharing of resources across the many virtual machine operating systems, and the alternative mechanism by ...
In an embodiment, a processor includes a plurality of counters each to provide a count of a perfo... more In an embodiment, a processor includes a plurality of counters each to provide a count of a performance metric of at least one core of the processor, a plurality of threshold registers each to store a threshold value with respect to a corresponding one of the plurality of counters, and an event logic to generate an event digest packet including a plurality of indicators each to indicate whether an event occurred based on a corresponding threshold value and a corresponding count value. Other embodiments are described and claimed.
Summary of recent Intel processor's cpuid values, model and family numbers linked to the architec... more Summary of recent Intel processor's cpuid values, model and family numbers linked to the architecture codename and processor codename as well as their brand names and model. Summary covers mainline IA x86 and x64 90nm, 65nm, 45nm, and 32nm processors.
Virtualization has become an essential strategy to control, manage, and share resources between m... more Virtualization has become an essential strategy to control, manage, and share resources between multiple executing services, bringing data centers remarkably close to extracting maximum efficiencies from their constituent platforms. Hardware assists to Virtualization have progressively increased the efficiency yields of virtualized platforms, but achieving scalable near native I/O performance remains a primary objective. The performance of I/O is a complex function of both the slowdown each access will incur from virtualization intermediaries and from the additional computing demands on the underlying hardware. By offloading a portion of the hypervisor's role in I/O processing to the hardware, hardware assist features like Intel®’s VT-d® can alleviate some of the I/O performance bottlenecks under virtualization. Given the growing role of virtualized servers in modern data center and cloud organizations, it is desirable to quantify the performance impact from such assists both at the level of unit I/O operations and at an application visible level.
Understanding workload performance and resource utilization under full system virtualization is c... more Understanding workload performance and resource utilization under full system virtualization is challenging because of the additional Virtual Machine Monitor layer, the sharing of resources across the many virtual machine operating systems, and the alternative mechanism by which several system facilities, such as I/O and interrupts, are handled. New pro ling, characterization, and modeling methodologies are required to shed light on the nature of system behavior under full system virtualization, including the behavior of hardware, system software, and guest software. We demonstrate that such methods are possible through synchronous and vertical data collection and analysis. The resulting pro ling data, characterizations and models enable a multitude of analyses which can better explain the complex transformations in hardware and software interaction brought about by the introduction of system virtualization. Such analyses aid the understanding of virtualized system performance and guide the future development of hardware and software virtualization solutions.
ACM Transactions on …, Jan 1, 2006
Parallel Architectures and Compilation …, Jan 1, 2005
Proceedings of the Workshop on …, Jan 1, 2007
Patents by Hussam Mousa
In an embodiment, a processor includes a plurality of counters each to provide a count of a perfo... more In an embodiment, a processor includes a plurality of counters each to provide a count of a performance metric of at least one core of the processor, a plurality of threshold registers each to store a threshold value with respect to a corresponding one of the plurality of counters, and an event logic to generate an event digest packet including a plurality of indicators each to indicate whether an event occurred based on a corresponding threshold value and a corresponding count value. Other embodiments are described and claimed.
Understanding workload performance and resource utilization under full system virtualization is c... more Understanding workload performance and resource utilization under full system virtualization is challenging because of the additional Virtual Machine Monitor layer, the sharing of resources across the many virtual machine operating systems, and the alternative mechanism by ...
In an embodiment, a processor includes a plurality of counters each to provide a count of a perfo... more In an embodiment, a processor includes a plurality of counters each to provide a count of a performance metric of at least one core of the processor, a plurality of threshold registers each to store a threshold value with respect to a corresponding one of the plurality of counters, and an event logic to generate an event digest packet including a plurality of indicators each to indicate whether an event occurred based on a corresponding threshold value and a corresponding count value. Other embodiments are described and claimed.
Summary of recent Intel processor's cpuid values, model and family numbers linked to the architec... more Summary of recent Intel processor's cpuid values, model and family numbers linked to the architecture codename and processor codename as well as their brand names and model. Summary covers mainline IA x86 and x64 90nm, 65nm, 45nm, and 32nm processors.
Virtualization has become an essential strategy to control, manage, and share resources between m... more Virtualization has become an essential strategy to control, manage, and share resources between multiple executing services, bringing data centers remarkably close to extracting maximum efficiencies from their constituent platforms. Hardware assists to Virtualization have progressively increased the efficiency yields of virtualized platforms, but achieving scalable near native I/O performance remains a primary objective. The performance of I/O is a complex function of both the slowdown each access will incur from virtualization intermediaries and from the additional computing demands on the underlying hardware. By offloading a portion of the hypervisor's role in I/O processing to the hardware, hardware assist features like Intel®’s VT-d® can alleviate some of the I/O performance bottlenecks under virtualization. Given the growing role of virtualized servers in modern data center and cloud organizations, it is desirable to quantify the performance impact from such assists both at the level of unit I/O operations and at an application visible level.
Understanding workload performance and resource utilization under full system virtualization is c... more Understanding workload performance and resource utilization under full system virtualization is challenging because of the additional Virtual Machine Monitor layer, the sharing of resources across the many virtual machine operating systems, and the alternative mechanism by which several system facilities, such as I/O and interrupts, are handled. New pro ling, characterization, and modeling methodologies are required to shed light on the nature of system behavior under full system virtualization, including the behavior of hardware, system software, and guest software. We demonstrate that such methods are possible through synchronous and vertical data collection and analysis. The resulting pro ling data, characterizations and models enable a multitude of analyses which can better explain the complex transformations in hardware and software interaction brought about by the introduction of system virtualization. Such analyses aid the understanding of virtualized system performance and guide the future development of hardware and software virtualization solutions.
ACM Transactions on …, Jan 1, 2006
Parallel Architectures and Compilation …, Jan 1, 2005
Proceedings of the Workshop on …, Jan 1, 2007
In an embodiment, a processor includes a plurality of counters each to provide a count of a perfo... more In an embodiment, a processor includes a plurality of counters each to provide a count of a performance metric of at least one core of the processor, a plurality of threshold registers each to store a threshold value with respect to a corresponding one of the plurality of counters, and an event logic to generate an event digest packet including a plurality of indicators each to indicate whether an event occurred based on a corresponding threshold value and a corresponding count value. Other embodiments are described and claimed.