John Eldon | University of California, San Diego (original) (raw)

Papers by John Eldon

Research paper thumbnail of <title>Two digital video encoder circuits</title>

Advanced Signal Processing Algorithms, Architectures, and Implementations III, 1992

Research paper thumbnail of <title>Video interface technology for wireless communications</title>

Advanced Signal Processing Algorithms, Architectures, and Implementations VI, 1996

Research paper thumbnail of Single-board digital signal processor

International Conference on Acoustics, Speech, and Signal Processing, 1981

Hardware and software needed to implement a 16-bit microprocessor-based, single-board digital sig... more Hardware and software needed to implement a 16-bit microprocessor-based, single-board digital signal processing system are outlined and discussed. As described, the system can perform high-speed dirital filtering and fast Fourier transforms in real time for signals of up to 35 kHz, and the basic architecture can be extended readily to handle higher frequency signals in real time.

Research paper thumbnail of Design of an improved air quality telemetry system

An engineering study of the feasibility of improving the air quality telemetry system is presente... more An engineering study of the feasibility of improving the air quality telemetry system is presented. The existing system is described along with some improvement ideas. Four alternative systems incorporating the improvements are described. The four designs were then analyzed to identify their relative advantages and drawbacks.

Research paper thumbnail of Analysis of the St. Louis RAMS (regional air monitoring system) ambient particulate data. Volume II: technical appendices

In this report, a variety of data analysis methods are used to study the 1976 particulate data fr... more In this report, a variety of data analysis methods are used to study the 1976 particulate data from the Regional Air Monitoring System (RAMS) in St. Louis. The aerosol data, collected at ten sites, include hi-vol measurements of total suspended particulate mass (TSP), as well as dichotomous sampler measurements of inhalable particulate mass (IP). IP is subdivided into fine particles

Research paper thumbnail of Two digital video encoder circuits

Central to `multimedia' image processing is the desire to encode computer graphics data into a st... more Central to `multimedia' image processing is the desire to encode computer graphics data into a standard television signal, complete with line, field, and color subcarrier synchronizing information. The numerous incompatibilities between television and computer display standards render this operation far less trivial than it sounds to anyone who hasn't worked with both types of signals. To simplify the task of encoding computer graphics signals into standard NTSC (North America and Japan) or PAL (most of Europe) television format for display, broadcast, or recording, TRW LSI Products Inc. has introduced the two newest members of it multimedia integrated circuit family, the TMC22090 and TMC22190 digital video encoders.

Research paper thumbnail of Video interface technology for wireless communications

Emerging technology finally permits wireless communication systems to carry video information eff... more Emerging technology finally permits wireless communication systems to carry video information efficiently. System challenges include low-noise preprocessing to maximize compressibility, efficient compression, decompression, and error-correction of the compressed signal, and clean reconstruction of the video waveform. This paper discusses algorithms and hardware for clean, efficient conversion of signals between universal analog television formats and compression-ready or decompressed digital video component formats. Problems of gunlock jitter, video decoding, cross- luminance, and video filtering are considered.

Research paper thumbnail of Legacy Television in an HDTV Environment

Research paper thumbnail of Integrated video interface technology

Asilomar Conference on Signals, Systems & Computers, 1996

Technology finally permits high-end consumer systems to accept, store, and display broadcast-qual... more Technology finally permits high-end consumer systems to accept, store, and display broadcast-quality signals cost-effectively. Mixed-signal design challenges include low-noise preprocessing and clean reconstruction of the video signal, plus real-time visual evaluation of image artifacts. This paper reviews the design, architecture and performance of a video input/output chipset which can digitize, decompose, mix, and synthesize NTSC and PAL television signals

Research paper thumbnail of Genlocked digital overlay on a video signal

IEEE International Symposium on Circuits and Systems, 1993

The synchronization problems involved in mixing computer graphics with a video signal are outline... more The synchronization problems involved in mixing computer graphics with a video signal are outlined, and it is shown how two components solve them. The components, a video encoder and a genlocking digitizer facilitate overlays of digital computer graphics and/or text data onto a standard analog NTSC (National Television System Committee) or PAL baseband television signal. The mapping of the clock

Research paper thumbnail of Applications Of A Bit-serial Floating-point Complex Multiplier-accumulator For High-speed Digital Signal Processing

Asilomar Conference on Signals, Systems & Computers, 1988

... John A. Eldon TRW LSI Products, Inc PO Box 2472 La Jolla, CA 92038 ... The tagged pipeline fo... more ... John A. Eldon TRW LSI Products, Inc PO Box 2472 La Jolla, CA 92038 ... The tagged pipeline for the stack and exponent adders has been de-signed and fabricated in the MOSIS 3 pm bulk CMOS technology for the purpose of functional testing. ...

Research paper thumbnail of VLSI Testing: A Decade of Experience

Computer Society International Conference, 1985

Research paper thumbnail of Using the TMC2301 image resampling sequencer

Microprocessors and Microsystems, 1990

Research paper thumbnail of Arithmetic for high speed FFT implementation

1985 IEEE 7th Symposium on Computer Arithmetic (ARITH), 1985

This paper describes recent progress in the implementation of high speed spectrum analysis system... more This paper describes recent progress in the implementation of high speed spectrum analysis systems with state-of-the-art commercial and semi-custom VLSI circuits. Initial efforts are producing Fast Fourier Transform (FFT) and inverse FFT processors that operate at data rates of up to 40 MHz (complex). The current implementation computes transforms of up to 16,384 points in length by means of the

Research paper thumbnail of <title>Image Transformation And Resampling</title>

Research paper thumbnail of Analysis of the St. Louis RAMS (regional air monitoring system) ambient particulate data. Volume I: Final report

In this report, a variety of data analysis methods are used to study the 1976 particulate data fr... more In this report, a variety of data analysis methods are used to study the 1976 particulate data from the Regional Air Monitoring System (RAMS) in St. Louis. The aerosol data, collected at ten sites, include hi-vol measurements of total suspended particulate mass (TSP), as well as dichotomous sampler measurements of inhalable particulate mass (IP). IP is subdivided into fine particles

Research paper thumbnail of Applications of the digital correlator

Microprocessors and Microsystems, 1988

Correlation can be a useful technique in a variety of digital systems applications. John Eldon sh... more Correlation can be a useful technique in a variety of digital systems applications. John Eldon shows how the TDC1023J digital correlator from TRW can be used in synchronization, A/D signal comparison and DSP-related tasks

Research paper thumbnail of Image processing address generator chip

International Conference on Acoustics, Speech, and Signal Processing, 1985

Accurate high speed rotation, warpage, translation, or rescaling of a two-dimensional image requi... more Accurate high speed rotation, warpage, translation, or rescaling of a two-dimensional image requires large RAMs, fast multiplier accumulators (MACs), and sophisticated address generators and controllers. TRW is designing a CM36 integrated circuit that generates the necessary control signals and data and coefficient addresses, economically replacing roughly 100 MSI and SSI components. The chip's target speed of 10 MHz is well matched to commercially available memories and MACs. With its versatile instruction set, the chip efficiently supports all first and second order image transforms, plus two dimensional filtering with a kernel size of up to 225 pixels.

Research paper thumbnail of A floating point format for signal processing

Journal of Substance Abuse Treatment, 1982

Until recently, most real time signal processing has been done in fixed point, due to size, cost,... more Until recently, most real time signal processing has been done in fixed point, due to size, cost, and speed limitations of available hardware. However, the increased dynamic range, consistent precision, and automatic normalization of floating point make it a desirable goal. The same increase in performance that was attained a few years ago when general purpose computing accepted floating point should now be attainable in hardware-based signal processing. For general purpose computation, 32 bit floating point has become the single precision standard. However, the 24 bit significand of this format provides more precision than is needed or justified for most signal processing, requires a large amount of hardware, and cannot yet be realized at 10MHz in a single integrated circuit. Therefore, a compromise format of 22 bits, using a 16 bit significand and a 6 bit exponent, has been developed. This format is compatible with 16 bit fixed point. To support this format, TRW is developing a single chip 10MHz adder/subtractor and a single chip 10MHz multiplier.

Research paper thumbnail of Video to VGA and back

Asilomar Conference on Signals, Systems & Computers, 1993

Converting a standard analog television signal into a digital component video or computer graphic... more Converting a standard analog television signal into a digital component video or computer graphics format entails: clock and sync acquisition, color reference acquisition, sampling and quantization, filtering, linear algebra, and quadrature demodulation. The paper traces a high performance video decoding algorithm and maps it to the architecture of a cost-effective new mixed-signal integrated circuit set from Raytheon Semiconductor

Research paper thumbnail of <title>Two digital video encoder circuits</title>

Advanced Signal Processing Algorithms, Architectures, and Implementations III, 1992

Research paper thumbnail of <title>Video interface technology for wireless communications</title>

Advanced Signal Processing Algorithms, Architectures, and Implementations VI, 1996

Research paper thumbnail of Single-board digital signal processor

International Conference on Acoustics, Speech, and Signal Processing, 1981

Hardware and software needed to implement a 16-bit microprocessor-based, single-board digital sig... more Hardware and software needed to implement a 16-bit microprocessor-based, single-board digital signal processing system are outlined and discussed. As described, the system can perform high-speed dirital filtering and fast Fourier transforms in real time for signals of up to 35 kHz, and the basic architecture can be extended readily to handle higher frequency signals in real time.

Research paper thumbnail of Design of an improved air quality telemetry system

An engineering study of the feasibility of improving the air quality telemetry system is presente... more An engineering study of the feasibility of improving the air quality telemetry system is presented. The existing system is described along with some improvement ideas. Four alternative systems incorporating the improvements are described. The four designs were then analyzed to identify their relative advantages and drawbacks.

Research paper thumbnail of Analysis of the St. Louis RAMS (regional air monitoring system) ambient particulate data. Volume II: technical appendices

In this report, a variety of data analysis methods are used to study the 1976 particulate data fr... more In this report, a variety of data analysis methods are used to study the 1976 particulate data from the Regional Air Monitoring System (RAMS) in St. Louis. The aerosol data, collected at ten sites, include hi-vol measurements of total suspended particulate mass (TSP), as well as dichotomous sampler measurements of inhalable particulate mass (IP). IP is subdivided into fine particles

Research paper thumbnail of Two digital video encoder circuits

Central to `multimedia' image processing is the desire to encode computer graphics data into a st... more Central to `multimedia' image processing is the desire to encode computer graphics data into a standard television signal, complete with line, field, and color subcarrier synchronizing information. The numerous incompatibilities between television and computer display standards render this operation far less trivial than it sounds to anyone who hasn't worked with both types of signals. To simplify the task of encoding computer graphics signals into standard NTSC (North America and Japan) or PAL (most of Europe) television format for display, broadcast, or recording, TRW LSI Products Inc. has introduced the two newest members of it multimedia integrated circuit family, the TMC22090 and TMC22190 digital video encoders.

Research paper thumbnail of Video interface technology for wireless communications

Emerging technology finally permits wireless communication systems to carry video information eff... more Emerging technology finally permits wireless communication systems to carry video information efficiently. System challenges include low-noise preprocessing to maximize compressibility, efficient compression, decompression, and error-correction of the compressed signal, and clean reconstruction of the video waveform. This paper discusses algorithms and hardware for clean, efficient conversion of signals between universal analog television formats and compression-ready or decompressed digital video component formats. Problems of gunlock jitter, video decoding, cross- luminance, and video filtering are considered.

Research paper thumbnail of Legacy Television in an HDTV Environment

Research paper thumbnail of Integrated video interface technology

Asilomar Conference on Signals, Systems & Computers, 1996

Technology finally permits high-end consumer systems to accept, store, and display broadcast-qual... more Technology finally permits high-end consumer systems to accept, store, and display broadcast-quality signals cost-effectively. Mixed-signal design challenges include low-noise preprocessing and clean reconstruction of the video signal, plus real-time visual evaluation of image artifacts. This paper reviews the design, architecture and performance of a video input/output chipset which can digitize, decompose, mix, and synthesize NTSC and PAL television signals

Research paper thumbnail of Genlocked digital overlay on a video signal

IEEE International Symposium on Circuits and Systems, 1993

The synchronization problems involved in mixing computer graphics with a video signal are outline... more The synchronization problems involved in mixing computer graphics with a video signal are outlined, and it is shown how two components solve them. The components, a video encoder and a genlocking digitizer facilitate overlays of digital computer graphics and/or text data onto a standard analog NTSC (National Television System Committee) or PAL baseband television signal. The mapping of the clock

Research paper thumbnail of Applications Of A Bit-serial Floating-point Complex Multiplier-accumulator For High-speed Digital Signal Processing

Asilomar Conference on Signals, Systems & Computers, 1988

... John A. Eldon TRW LSI Products, Inc PO Box 2472 La Jolla, CA 92038 ... The tagged pipeline fo... more ... John A. Eldon TRW LSI Products, Inc PO Box 2472 La Jolla, CA 92038 ... The tagged pipeline for the stack and exponent adders has been de-signed and fabricated in the MOSIS 3 pm bulk CMOS technology for the purpose of functional testing. ...

Research paper thumbnail of VLSI Testing: A Decade of Experience

Computer Society International Conference, 1985

Research paper thumbnail of Using the TMC2301 image resampling sequencer

Microprocessors and Microsystems, 1990

Research paper thumbnail of Arithmetic for high speed FFT implementation

1985 IEEE 7th Symposium on Computer Arithmetic (ARITH), 1985

This paper describes recent progress in the implementation of high speed spectrum analysis system... more This paper describes recent progress in the implementation of high speed spectrum analysis systems with state-of-the-art commercial and semi-custom VLSI circuits. Initial efforts are producing Fast Fourier Transform (FFT) and inverse FFT processors that operate at data rates of up to 40 MHz (complex). The current implementation computes transforms of up to 16,384 points in length by means of the

Research paper thumbnail of <title>Image Transformation And Resampling</title>

Research paper thumbnail of Analysis of the St. Louis RAMS (regional air monitoring system) ambient particulate data. Volume I: Final report

In this report, a variety of data analysis methods are used to study the 1976 particulate data fr... more In this report, a variety of data analysis methods are used to study the 1976 particulate data from the Regional Air Monitoring System (RAMS) in St. Louis. The aerosol data, collected at ten sites, include hi-vol measurements of total suspended particulate mass (TSP), as well as dichotomous sampler measurements of inhalable particulate mass (IP). IP is subdivided into fine particles

Research paper thumbnail of Applications of the digital correlator

Microprocessors and Microsystems, 1988

Correlation can be a useful technique in a variety of digital systems applications. John Eldon sh... more Correlation can be a useful technique in a variety of digital systems applications. John Eldon shows how the TDC1023J digital correlator from TRW can be used in synchronization, A/D signal comparison and DSP-related tasks

Research paper thumbnail of Image processing address generator chip

International Conference on Acoustics, Speech, and Signal Processing, 1985

Accurate high speed rotation, warpage, translation, or rescaling of a two-dimensional image requi... more Accurate high speed rotation, warpage, translation, or rescaling of a two-dimensional image requires large RAMs, fast multiplier accumulators (MACs), and sophisticated address generators and controllers. TRW is designing a CM36 integrated circuit that generates the necessary control signals and data and coefficient addresses, economically replacing roughly 100 MSI and SSI components. The chip's target speed of 10 MHz is well matched to commercially available memories and MACs. With its versatile instruction set, the chip efficiently supports all first and second order image transforms, plus two dimensional filtering with a kernel size of up to 225 pixels.

Research paper thumbnail of A floating point format for signal processing

Journal of Substance Abuse Treatment, 1982

Until recently, most real time signal processing has been done in fixed point, due to size, cost,... more Until recently, most real time signal processing has been done in fixed point, due to size, cost, and speed limitations of available hardware. However, the increased dynamic range, consistent precision, and automatic normalization of floating point make it a desirable goal. The same increase in performance that was attained a few years ago when general purpose computing accepted floating point should now be attainable in hardware-based signal processing. For general purpose computation, 32 bit floating point has become the single precision standard. However, the 24 bit significand of this format provides more precision than is needed or justified for most signal processing, requires a large amount of hardware, and cannot yet be realized at 10MHz in a single integrated circuit. Therefore, a compromise format of 22 bits, using a 16 bit significand and a 6 bit exponent, has been developed. This format is compatible with 16 bit fixed point. To support this format, TRW is developing a single chip 10MHz adder/subtractor and a single chip 10MHz multiplier.

Research paper thumbnail of Video to VGA and back

Asilomar Conference on Signals, Systems & Computers, 1993

Converting a standard analog television signal into a digital component video or computer graphic... more Converting a standard analog television signal into a digital component video or computer graphics format entails: clock and sync acquisition, color reference acquisition, sampling and quantization, filtering, linear algebra, and quadrature demodulation. The paper traces a high performance video decoding algorithm and maps it to the architecture of a cost-effective new mixed-signal integrated circuit set from Raytheon Semiconductor