Adib K Chowdhury | University College of Technology Sarawak (original) (raw)

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Conference & Journal by Adib K Chowdhury

Research paper thumbnail of Vision-based Registration for Augmented Reality - A Short Survey

IEEE International Conference on Signal and Image Processing Applications (ICSIPA), Oct 2015

The purpose of this paper is to explore some existing techniques in vision-based registration for... more The purpose of this paper is to explore some existing techniques in vision-based registration for Augmented Reality (AR) and present them collectively. AR is a branch of computer vision which generally overlays Virtual Objects (VOs) on actual images of real-world scenes in order to provide additional information about the scene to the user. Due to its wide range of applications in the fields of medical, robotics and automotive, geographic and remote sensing, military and aerospace, it has gained high demand. In any AR system, registration is the key to make the augmented scene appearing natural. Registration process must avoid occlusion of VOs and objects in the real world and align the VOs precisely. Optics-based and video-based are two well-known industrial AR systems. Researchers show that even with a single camera model registration for an AR is plausible but, VOs may be registered in front of real-world objects. It is because the registration process lacks depth information of the scene. However, employing stereo vision system and utilizing available natural features in a real-world scene and set of arbitrary multiple planes one can improve accuracy of VO registration. Thus, an AR system becomes robust if it is devised with algorithms to extract and track natural features in real-time.

Research paper thumbnail of An Analysis of MVL Neural Operators Using Feed Forward Backpropagation Realization and Application of Logic Synthesis

IEEE International Conference on Smart Sensors and Application (ICSSA), 2015

In this paper, a Neural Network Deployment (NND) algorithm is presented to realize and synthesize... more In this paper, a Neural Network Deployment (NND) algorithm is presented to realize and synthesize Multi-Valued Logic (MVL) functions. The algorithm is combined with back-propagation learning capability and MVL operators. The operators are used to synthesize the functions. Consequently the synthesized expressions are applied by the MVL neural operators. The advantages of NND-MVL algorithm are demonstrated by accuracy measurement of MVL neural operator realization. Furthermore, evaluation of NND-MVL algorithm is analyzed by its application, propagation delay and accuracy achieved for training with 4 hidden neurons. In a brief, an effort of training MVL neural operators and utilizing them for logic synthesis is observed.

Research paper thumbnail of Design and Synthesis of Reversible Arithmetic and Logic Unit (ALU)

IEEE International Conference on Computer, Communications, and Control Technology (I4CT), 2014

In low power circuit design, reversible computing has become one of the most efficient and promin... more In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design.

Research paper thumbnail of Non-Zero Multi-Valued Decision Diagram (NZMDD) Based Synthesis of Multi-Valued Logic (MVL) Functions

Advanced Materials Research Journal, 2014

In this paper a method for synthesizing Reduced Multi-Valued Logic Networks (RMVLNs) using NZMDD ... more In this paper a method for synthesizing Reduced Multi-Valued Logic Networks (RMVLNs) using NZMDD is presented. MVL functions represented as large MVLNs are reduced by RMVLN. The detailed working of NZMDD method is presented elaborately in this paper. It is observed that reduced average Product Term (PT) is achieved in MVL synthesis using NZMDD. Experimental analysis is carried out by examining randomly generated 49998 non-sequential benchmark circuits. An improvement average PT reduction of 12.486% is noted in comparison to evolutionary ACO-MVL algorithm.

Research paper thumbnail of Vision-based Registration for Augmented Reality - A Short Survey

IEEE International Conference on Signal and Image Processing Applications (ICSIPA), Oct 2015

The purpose of this paper is to explore some existing techniques in vision-based registration for... more The purpose of this paper is to explore some existing techniques in vision-based registration for Augmented Reality (AR) and present them collectively. AR is a branch of computer vision which generally overlays Virtual Objects (VOs) on actual images of real-world scenes in order to provide additional information about the scene to the user. Due to its wide range of applications in the fields of medical, robotics and automotive, geographic and remote sensing, military and aerospace, it has gained high demand. In any AR system, registration is the key to make the augmented scene appearing natural. Registration process must avoid occlusion of VOs and objects in the real world and align the VOs precisely. Optics-based and video-based are two well-known industrial AR systems. Researchers show that even with a single camera model registration for an AR is plausible but, VOs may be registered in front of real-world objects. It is because the registration process lacks depth information of the scene. However, employing stereo vision system and utilizing available natural features in a real-world scene and set of arbitrary multiple planes one can improve accuracy of VO registration. Thus, an AR system becomes robust if it is devised with algorithms to extract and track natural features in real-time.

Research paper thumbnail of An Analysis of MVL Neural Operators Using Feed Forward Backpropagation Realization and Application of Logic Synthesis

IEEE International Conference on Smart Sensors and Application (ICSSA), 2015

In this paper, a Neural Network Deployment (NND) algorithm is presented to realize and synthesize... more In this paper, a Neural Network Deployment (NND) algorithm is presented to realize and synthesize Multi-Valued Logic (MVL) functions. The algorithm is combined with back-propagation learning capability and MVL operators. The operators are used to synthesize the functions. Consequently the synthesized expressions are applied by the MVL neural operators. The advantages of NND-MVL algorithm are demonstrated by accuracy measurement of MVL neural operator realization. Furthermore, evaluation of NND-MVL algorithm is analyzed by its application, propagation delay and accuracy achieved for training with 4 hidden neurons. In a brief, an effort of training MVL neural operators and utilizing them for logic synthesis is observed.

Research paper thumbnail of Design and Synthesis of Reversible Arithmetic and Logic Unit (ALU)

IEEE International Conference on Computer, Communications, and Control Technology (I4CT), 2014

In low power circuit design, reversible computing has become one of the most efficient and promin... more In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design.

Research paper thumbnail of Non-Zero Multi-Valued Decision Diagram (NZMDD) Based Synthesis of Multi-Valued Logic (MVL) Functions

Advanced Materials Research Journal, 2014

In this paper a method for synthesizing Reduced Multi-Valued Logic Networks (RMVLNs) using NZMDD ... more In this paper a method for synthesizing Reduced Multi-Valued Logic Networks (RMVLNs) using NZMDD is presented. MVL functions represented as large MVLNs are reduced by RMVLN. The detailed working of NZMDD method is presented elaborately in this paper. It is observed that reduced average Product Term (PT) is achieved in MVL synthesis using NZMDD. Experimental analysis is carried out by examining randomly generated 49998 non-sequential benchmark circuits. An improvement average PT reduction of 12.486% is noted in comparison to evolutionary ACO-MVL algorithm.