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Papers by Robert B Staszewski
IEEE Transactions on Circuits and Systems I: Regular Papers
Nonlinearity of a digital-to-time converter (DTC) is pivotal to spur performance in DTC-based all... more Nonlinearity of a digital-to-time converter (DTC) is pivotal to spur performance in DTC-based all-digital phaselocked-loops (ADPLL). In this paper, we characterize and analyze the mismatch of cascaded-delay-unit DTCs. Through an improved built-in-self-test (BIST) time-to-digital converter (TDC) assisted with phase-to-frequency detector (PFD), a measurement system of sub-half-ps accuracy is constructed to conduct the characterization. Fabricated in 28-nm CMOS, the DTC transfer functions are measured, and mismatches are compared against Monte-Carlo simulation results. The integral nonlinearity (INL) results are compared against each other and converted to the in-band fractional spur level when the DTC would be deployed in the ADPLL. The BIST-TDC system thus characterizes the on-chip delays without expensive equipment or complex setup. The effectiveness of adding a PFD into the loop is validated. The entire BIST system consumes 0.6 mW with a system self-calibration algorithm to tackle the analog blocks' nonlinearities.
IEEE Transactions on Circuits and Systems II: Express Briefs
We propose a self-biased inverter-based amplifier for realizing a high-speed low-power second-ord... more We propose a self-biased inverter-based amplifier for realizing a high-speed low-power second-order single-loop continuous-time bandpass delta-sigma modulator (CT-BP-M). The design is amenable to nanoscale CMOS and exploits a single self-biased pseudo-differential inverter with a positive feedback to replace conventional op-amps used in an integrator configuration. The modulator also uses a 5-bit asynchronous successive approximation register (ASAR) quantizer. With a 30 MHz bandwidth at 400 MS/s sampling rate and 100 MHz intermediate frequency (IF), the modulator achieves 61 dB dynamic range (DR) and 58 dB SNDR while consuming 2.5 mW from a 1V supply. The core area in 28 nm LP CMOS is 0.04 mm 2. A 38.6 fJ/conv.-step figure of merit is achieved. Index Terms-ADC, asynchronous successive approximation register (ASAR), bandpass, continuous-time (CT), delta-sigma modulator (M), inverter-based, single-loop. I. INTRODUCTION H IGH-SPEED, high-resolution and low-power analogto-digital converters (ADC) in low-voltage nanoscale CMOS are in great demand by modern broadband wireless communication systems and IOT applications [1]. Continuoustime delta-sigma modulators (CT-M) are attractive as they promise to fulfill requirements of such systems. CT-M provides significant power savings due to reduction of bandwidth requirements of its circuitry as compared to the alternative switched-capacitor (SC) implementations [2]. It also offers a high dynamic range (DR) and implicit anti-aliasing [3]. However, with the deep scaling of CMOS technology, the resulting low supply voltage has put significant challenges on the ADC circuit design. Specifically, the operational transconductance amplifier (OTA) is now a bottleneck in filter designs
IEEE Transactions on Circuits and Systems I: Regular Papers
This paper demonstrates a wideband 2.4 GHz 2 × 9-bit Cartesian radio-frequency digital-to-analog ... more This paper demonstrates a wideband 2.4 GHz 2 × 9-bit Cartesian radio-frequency digital-to-analog converter (RFDAC). Active-under-coil integration is introduced in the physical implementation, where all key active circuitry is located underneath the matching-network transformer, achieving a core area of merely 0.35 mm 2. An 8× analog linear interpolation at the RF rate is proposed to suppress replicas close to the carrier while avoiding any high-order and high-speed digital filters in digital processing back-end. The multi-port transformer is adopted in the matching network to improve the back-off efficiency. The measured peak output power and drain efficiency at the center frequency of 2.4 GHz are 17.47 dBm and 17.6% respectively, while the peak efficiency is 19.03%. Moreover, the 6-dB back-off efficiency is at 66% of that at the peak output power. The activeunder-coil integration helps this RFDAC to achieve the smallest area among comparable prior arts.
IEEE Transactions on Circuits and Systems I: Regular Papers
A 50 MS/s two-step flash-MASH 1-1-1 timeto-digital converter (TDC) employing a two-channel time-i... more A 50 MS/s two-step flash-MASH 1-1-1 timeto-digital converter (TDC) employing a two-channel time-interleaved time-domain register with an implicit adder/subtractor realizes an error-feedback topology. Such an error-feedback unit of 1 st-order noise-shaping TDC can be cascaded as a multi-stage noise shaping (MASH) configuration to achieve higher-order noise-shaping and, thereby high resolution. This paper also discusses different noise sources, linearity and noise tradeoffs in noise-shaping TDC and then demonstrates a histogram testing technique to correct the mismatch of 1 st stage flash TDC. An on/off-chip delay modulation (DM) measurement technique is presented to characterize the TDC linearity and noise performance. Fabricated in 40-nm CMOS technology, the proposed TDC consumes 1.32 mW from a 1.1 V supply. At frequency below 2.5 MHz, the TDC error integrates to 147fs rms, which is equal to equivalent flash resolution of 1.6 ps.
IEEE Transactions on Circuits and Systems II: Express Briefs
In this brief, we introduce a 3.2-4 GHz threewinding transformer-based class-F digitally controll... more In this brief, we introduce a 3.2-4 GHz threewinding transformer-based class-F digitally controlled oscillator (DCO) with a DC-DC booster for energy harvesting applications. A π-model is adopted for this multi-turn transformer to analyze its impedance transformation and overall loop gain. The trifilar coil generates large passive voltage loop gain, allowing the DCO supply voltage of 0.2 V to be even lower than the threshold voltage of transistors without any performance degradation. Due to the gate/drain isolation as well as smaller voltage-dependent capacitance in advanced FinFET technology, this work achieves very low supply frequency pushing of 38 MHz/V. The switched capacitor placed at the tertiary winding can reach very fine resolution of 1.3 kHz due to the impedance transformations and source degeneration. The bias and control voltages of nearly zero power are generated with a switched-capacitor based DC-DC converter and a ring-based non-overlapped clock generator.
IEEE Transactions on Circuits and Systems II: Express Briefs
This brief presents a design procedure of a compact 33-GHz low-noise amplifier (LNA) for fifth ge... more This brief presents a design procedure of a compact 33-GHz low-noise amplifier (LNA) for fifth generation (5G) applications realized in 28-nm LP CMOS. Based on the unique set of challenges presented by advanced nanoscale CMOS, the emphasis is put here on the optimization of design and layout techniques for active and passive components in the presence of rigorous metal density rules and other back-end-of-the-line challenges. All passive components are designed and optimized with full-wave electromagnetic simulations for a high quality factor. In addition, layout techniques help to miniaturize the total area as the suggested 5G frequency band of 33 GHz is not high enough to provide a sufficiently compact chip size. The resulting increase in the concentration of required metal fills furthermore makes this optimization more challenging. The fabricated LNA consists of two cascode stages with a total core area of 0.68×0.34 mm 2. It exhibits 4.9-dB noise figure and 18.6-dB gain at 33 GHz while consuming only 9.7 mW from a 1.2-V power supply.
IEEE Transactions on Microwave Theory and Techniques
A phase-coherent technique for multiple all-digital phase-locked loops (ADPLLs) is presented and ... more A phase-coherent technique for multiple all-digital phase-locked loops (ADPLLs) is presented and developed in this paper to target a 57-63-GHz multiple-input multipleoutput (MIMO) transmitter (TX) with a digital beam-steering capability. The ADPLL TX chains are first fabricated in nanoscale CMOS and then time-synchronized and frequencyphase locked by a field-programmable gate array (FPGA) evaluation board. The calibration approach for phase alignment is carried out using a cancellation method to acquire the out-ofphase state within two ADPLLs. The accuracy of beam steering and phase alignment is investigated and analyzed based on a time-domain model for ADPLL to consider the impact of phase noise. The analysis results offer the required values of the ADPLL parameters to allow a millimeter-wave (mm-wave) MIMO TX with a highly accurate digital beam-steering capability.
IEEE Journal of Solid-State Circuits
In this paper, we propose a 60-GHz fractional-N digital frequency synthesizer aimed at reducing i... more In this paper, we propose a 60-GHz fractional-N digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker (1/f 3) and thermal (1/f 2) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong third harmonic at 60 GHz which is extracted to the output while canceling the 20-GHz fundamental. The latter component is fed back to the frequency dividers in an all-digital phase-locked loop for phase detection, which comprises a pair of digital-to-time and time-to-digital converters with dithering to attenuate fractional spurs. The mechanism of flicker noise upconversion to 1/f 3 PN in the DCO is investigated, and a reduction technique is proposed. The 28-nm CMOS prototype achieves 213-277-fs rms jitter in the 57.5-67.2-GHz tuning range while consuming only 40 mW. The DCO flicker PN corner is record low at 300-400 kHz.
IEEE Transactions on Circuits and Systems I: Regular Papers
We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, whic... more We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains 7-ps resolution for <−107 dBc/Hz in-band phase noise while the 7.3-mW DCO emits −157 dBc/Hz at 20 MHz offset at 2 GHz. Reference spurs are <−91 dBc, while fractional spurs are <−55 dBc. The ADPLL supports a 2-point modulation and consumes 11.5-mW while occupying 0.22 mm 2. Index Terms-All-digital PLL (ADPLL), digitally controlled oscillator (DCO), time-to-digital converter (TDC), spurs, long-term evolution (LTE), 4G cellular. I. INTRODUCTION M OBILE phones enjoy the largest production volume of any consumer electronics product. However, the demands they place on monolithic local oscillators (LO), realized as RF PLLs, are particularly tough, especially on integration with digital processors, low area of silicon, low power consumption, low phase noise (PN), and virtually no spurious tones, while being robust against environmental changes. Moreover, as each wireless standard has its own set of specifications, the implementation of a multi-standard PLLs has become a challenging task. For instance, narrow bandwidth systems, such as GSM of 2G and enhanced data rate for WCDMA of 3G, put enormous stress on low out-of-band PN, while wide bandwidth systems, such as 4G/5G, demand Manuscript
IEEE Journal of Solid-State Circuits
IEEE Transactions on Microwave Theory and Techniques
In this paper, we apply various area reduction techniques on an inductor-capacitor (LC)-tank osci... more In this paper, we apply various area reduction techniques on an inductor-capacitor (LC)-tank oscillator in order to make its size comparable to that of ring oscillators (ROs), while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The resulting oscillator employs a proposed ultracompact split transformer topology that provides a 1:2 passive voltage gain and is less susceptible to common-mode electromagnetic interference than are regular high-quality-factor LC tanks, thus making it desirable in systemon-a-chip environments. The oscillator, together with a proposed dc-coupled buffer, is incorporated within an all-digital phaselocked loop (ADPLL) intended for wireline, digital clocking, and less stringent wireless systems. The ADPLL architecture introduces a look-ahead time-to-digital converter that exploits a deterministic phase prediction to reduce power consumption and phase detection complexity. The ADPLL is realized in 40-nm CMOS and has the smallest reported area of 0.0625 mm 2 among LC-tank oscillators while providing fractional-N operation, wide tuning range of 45% (from 9.4 to 14.8 GHz), very low voltage supply sensitivity of 80 MHz/V, and integrated figure-of-merit jitter (FoM jitter) better than −230 dB. A separate identical ADPLL was implemented using an RO instead, for completeness and systematic comparisons. Index Terms-All-digital phase-locked loop (ADPLL), digitally controlled oscillator (DCO), inductor-capacitor (LC)-tank oscillator, ring oscillator (RO), time-to-digital converter (TDC), transformer.
Transmit filter using a reference clock that is no integer multiple of the symbol clock
Advances in Digital RF Architectures and Digitally-Assisted RF
Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels
Ieee Transactions on Very Large Scale Integration Systems, Feb 1, 2001
Page 1. 42 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 1, FEBRU... more Page 1. 42 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 1, FEBRUARY 2001 Speed, Power, Area, and Latency Tradeoffs in Adaptive FIR Filtering for PRML Read Channels ...
完全ディジタルPLL回路の設計 : ディープ・サブミクロンCMOSプロセスで実現する
Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOS
2007 Ieee International Symposium on Circuits and Systems, May 27, 2007
The paper proposed estimation techniques and compensation algorithms against CMOS device variabil... more The paper proposed estimation techniques and compensation algorithms against CMOS device variability in an all-digital RF polar transmitter. The transmitter is built using dense and fast digital logic and comprises two converters that transform transmit modulation from digital to RF frequency/phase and amplitude analog domains. The converters built with segmented banks consist of a large number of unit-weighted devices which exhibit a certain level of random and systematic mismatch. The techniques presented are employed in a commercial single-chip GSM/EDGE radio realized in 90 nm CMOS
Interpolative all-digital phase locked loop
Direct RF sampling mixer with recursive filtering in charge domain
2004 Ieee International Symposium on Circuits and Systems, May 23, 2004
ABSTRACT We present a novel direct RF sampling technique in which an input RF signal is converted... more ABSTRACT We present a novel direct RF sampling technique in which an input RF signal is converted to a current waveform, gated and integrated on a sampling capacitor. A rotating capacitor shares this charge with the main sampling capacitor and transfers it to a subsequent ...
Phase detector and methodology
Digital Phase Locked Loop with Gear Shifting
IEEE Transactions on Circuits and Systems I: Regular Papers
Nonlinearity of a digital-to-time converter (DTC) is pivotal to spur performance in DTC-based all... more Nonlinearity of a digital-to-time converter (DTC) is pivotal to spur performance in DTC-based all-digital phaselocked-loops (ADPLL). In this paper, we characterize and analyze the mismatch of cascaded-delay-unit DTCs. Through an improved built-in-self-test (BIST) time-to-digital converter (TDC) assisted with phase-to-frequency detector (PFD), a measurement system of sub-half-ps accuracy is constructed to conduct the characterization. Fabricated in 28-nm CMOS, the DTC transfer functions are measured, and mismatches are compared against Monte-Carlo simulation results. The integral nonlinearity (INL) results are compared against each other and converted to the in-band fractional spur level when the DTC would be deployed in the ADPLL. The BIST-TDC system thus characterizes the on-chip delays without expensive equipment or complex setup. The effectiveness of adding a PFD into the loop is validated. The entire BIST system consumes 0.6 mW with a system self-calibration algorithm to tackle the analog blocks' nonlinearities.
IEEE Transactions on Circuits and Systems II: Express Briefs
We propose a self-biased inverter-based amplifier for realizing a high-speed low-power second-ord... more We propose a self-biased inverter-based amplifier for realizing a high-speed low-power second-order single-loop continuous-time bandpass delta-sigma modulator (CT-BP-M). The design is amenable to nanoscale CMOS and exploits a single self-biased pseudo-differential inverter with a positive feedback to replace conventional op-amps used in an integrator configuration. The modulator also uses a 5-bit asynchronous successive approximation register (ASAR) quantizer. With a 30 MHz bandwidth at 400 MS/s sampling rate and 100 MHz intermediate frequency (IF), the modulator achieves 61 dB dynamic range (DR) and 58 dB SNDR while consuming 2.5 mW from a 1V supply. The core area in 28 nm LP CMOS is 0.04 mm 2. A 38.6 fJ/conv.-step figure of merit is achieved. Index Terms-ADC, asynchronous successive approximation register (ASAR), bandpass, continuous-time (CT), delta-sigma modulator (M), inverter-based, single-loop. I. INTRODUCTION H IGH-SPEED, high-resolution and low-power analogto-digital converters (ADC) in low-voltage nanoscale CMOS are in great demand by modern broadband wireless communication systems and IOT applications [1]. Continuoustime delta-sigma modulators (CT-M) are attractive as they promise to fulfill requirements of such systems. CT-M provides significant power savings due to reduction of bandwidth requirements of its circuitry as compared to the alternative switched-capacitor (SC) implementations [2]. It also offers a high dynamic range (DR) and implicit anti-aliasing [3]. However, with the deep scaling of CMOS technology, the resulting low supply voltage has put significant challenges on the ADC circuit design. Specifically, the operational transconductance amplifier (OTA) is now a bottleneck in filter designs
IEEE Transactions on Circuits and Systems I: Regular Papers
This paper demonstrates a wideband 2.4 GHz 2 × 9-bit Cartesian radio-frequency digital-to-analog ... more This paper demonstrates a wideband 2.4 GHz 2 × 9-bit Cartesian radio-frequency digital-to-analog converter (RFDAC). Active-under-coil integration is introduced in the physical implementation, where all key active circuitry is located underneath the matching-network transformer, achieving a core area of merely 0.35 mm 2. An 8× analog linear interpolation at the RF rate is proposed to suppress replicas close to the carrier while avoiding any high-order and high-speed digital filters in digital processing back-end. The multi-port transformer is adopted in the matching network to improve the back-off efficiency. The measured peak output power and drain efficiency at the center frequency of 2.4 GHz are 17.47 dBm and 17.6% respectively, while the peak efficiency is 19.03%. Moreover, the 6-dB back-off efficiency is at 66% of that at the peak output power. The activeunder-coil integration helps this RFDAC to achieve the smallest area among comparable prior arts.
IEEE Transactions on Circuits and Systems I: Regular Papers
A 50 MS/s two-step flash-MASH 1-1-1 timeto-digital converter (TDC) employing a two-channel time-i... more A 50 MS/s two-step flash-MASH 1-1-1 timeto-digital converter (TDC) employing a two-channel time-interleaved time-domain register with an implicit adder/subtractor realizes an error-feedback topology. Such an error-feedback unit of 1 st-order noise-shaping TDC can be cascaded as a multi-stage noise shaping (MASH) configuration to achieve higher-order noise-shaping and, thereby high resolution. This paper also discusses different noise sources, linearity and noise tradeoffs in noise-shaping TDC and then demonstrates a histogram testing technique to correct the mismatch of 1 st stage flash TDC. An on/off-chip delay modulation (DM) measurement technique is presented to characterize the TDC linearity and noise performance. Fabricated in 40-nm CMOS technology, the proposed TDC consumes 1.32 mW from a 1.1 V supply. At frequency below 2.5 MHz, the TDC error integrates to 147fs rms, which is equal to equivalent flash resolution of 1.6 ps.
IEEE Transactions on Circuits and Systems II: Express Briefs
In this brief, we introduce a 3.2-4 GHz threewinding transformer-based class-F digitally controll... more In this brief, we introduce a 3.2-4 GHz threewinding transformer-based class-F digitally controlled oscillator (DCO) with a DC-DC booster for energy harvesting applications. A π-model is adopted for this multi-turn transformer to analyze its impedance transformation and overall loop gain. The trifilar coil generates large passive voltage loop gain, allowing the DCO supply voltage of 0.2 V to be even lower than the threshold voltage of transistors without any performance degradation. Due to the gate/drain isolation as well as smaller voltage-dependent capacitance in advanced FinFET technology, this work achieves very low supply frequency pushing of 38 MHz/V. The switched capacitor placed at the tertiary winding can reach very fine resolution of 1.3 kHz due to the impedance transformations and source degeneration. The bias and control voltages of nearly zero power are generated with a switched-capacitor based DC-DC converter and a ring-based non-overlapped clock generator.
IEEE Transactions on Circuits and Systems II: Express Briefs
This brief presents a design procedure of a compact 33-GHz low-noise amplifier (LNA) for fifth ge... more This brief presents a design procedure of a compact 33-GHz low-noise amplifier (LNA) for fifth generation (5G) applications realized in 28-nm LP CMOS. Based on the unique set of challenges presented by advanced nanoscale CMOS, the emphasis is put here on the optimization of design and layout techniques for active and passive components in the presence of rigorous metal density rules and other back-end-of-the-line challenges. All passive components are designed and optimized with full-wave electromagnetic simulations for a high quality factor. In addition, layout techniques help to miniaturize the total area as the suggested 5G frequency band of 33 GHz is not high enough to provide a sufficiently compact chip size. The resulting increase in the concentration of required metal fills furthermore makes this optimization more challenging. The fabricated LNA consists of two cascode stages with a total core area of 0.68×0.34 mm 2. It exhibits 4.9-dB noise figure and 18.6-dB gain at 33 GHz while consuming only 9.7 mW from a 1.2-V power supply.
IEEE Transactions on Microwave Theory and Techniques
A phase-coherent technique for multiple all-digital phase-locked loops (ADPLLs) is presented and ... more A phase-coherent technique for multiple all-digital phase-locked loops (ADPLLs) is presented and developed in this paper to target a 57-63-GHz multiple-input multipleoutput (MIMO) transmitter (TX) with a digital beam-steering capability. The ADPLL TX chains are first fabricated in nanoscale CMOS and then time-synchronized and frequencyphase locked by a field-programmable gate array (FPGA) evaluation board. The calibration approach for phase alignment is carried out using a cancellation method to acquire the out-ofphase state within two ADPLLs. The accuracy of beam steering and phase alignment is investigated and analyzed based on a time-domain model for ADPLL to consider the impact of phase noise. The analysis results offer the required values of the ADPLL parameters to allow a millimeter-wave (mm-wave) MIMO TX with a highly accurate digital beam-steering capability.
IEEE Journal of Solid-State Circuits
In this paper, we propose a 60-GHz fractional-N digital frequency synthesizer aimed at reducing i... more In this paper, we propose a 60-GHz fractional-N digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker (1/f 3) and thermal (1/f 2) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong third harmonic at 60 GHz which is extracted to the output while canceling the 20-GHz fundamental. The latter component is fed back to the frequency dividers in an all-digital phase-locked loop for phase detection, which comprises a pair of digital-to-time and time-to-digital converters with dithering to attenuate fractional spurs. The mechanism of flicker noise upconversion to 1/f 3 PN in the DCO is investigated, and a reduction technique is proposed. The 28-nm CMOS prototype achieves 213-277-fs rms jitter in the 57.5-67.2-GHz tuning range while consuming only 40 mW. The DCO flicker PN corner is record low at 300-400 kHz.
IEEE Transactions on Circuits and Systems I: Regular Papers
We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, whic... more We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains 7-ps resolution for <−107 dBc/Hz in-band phase noise while the 7.3-mW DCO emits −157 dBc/Hz at 20 MHz offset at 2 GHz. Reference spurs are <−91 dBc, while fractional spurs are <−55 dBc. The ADPLL supports a 2-point modulation and consumes 11.5-mW while occupying 0.22 mm 2. Index Terms-All-digital PLL (ADPLL), digitally controlled oscillator (DCO), time-to-digital converter (TDC), spurs, long-term evolution (LTE), 4G cellular. I. INTRODUCTION M OBILE phones enjoy the largest production volume of any consumer electronics product. However, the demands they place on monolithic local oscillators (LO), realized as RF PLLs, are particularly tough, especially on integration with digital processors, low area of silicon, low power consumption, low phase noise (PN), and virtually no spurious tones, while being robust against environmental changes. Moreover, as each wireless standard has its own set of specifications, the implementation of a multi-standard PLLs has become a challenging task. For instance, narrow bandwidth systems, such as GSM of 2G and enhanced data rate for WCDMA of 3G, put enormous stress on low out-of-band PN, while wide bandwidth systems, such as 4G/5G, demand Manuscript
IEEE Journal of Solid-State Circuits
IEEE Transactions on Microwave Theory and Techniques
In this paper, we apply various area reduction techniques on an inductor-capacitor (LC)-tank osci... more In this paper, we apply various area reduction techniques on an inductor-capacitor (LC)-tank oscillator in order to make its size comparable to that of ring oscillators (ROs), while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The resulting oscillator employs a proposed ultracompact split transformer topology that provides a 1:2 passive voltage gain and is less susceptible to common-mode electromagnetic interference than are regular high-quality-factor LC tanks, thus making it desirable in systemon-a-chip environments. The oscillator, together with a proposed dc-coupled buffer, is incorporated within an all-digital phaselocked loop (ADPLL) intended for wireline, digital clocking, and less stringent wireless systems. The ADPLL architecture introduces a look-ahead time-to-digital converter that exploits a deterministic phase prediction to reduce power consumption and phase detection complexity. The ADPLL is realized in 40-nm CMOS and has the smallest reported area of 0.0625 mm 2 among LC-tank oscillators while providing fractional-N operation, wide tuning range of 45% (from 9.4 to 14.8 GHz), very low voltage supply sensitivity of 80 MHz/V, and integrated figure-of-merit jitter (FoM jitter) better than −230 dB. A separate identical ADPLL was implemented using an RO instead, for completeness and systematic comparisons. Index Terms-All-digital phase-locked loop (ADPLL), digitally controlled oscillator (DCO), inductor-capacitor (LC)-tank oscillator, ring oscillator (RO), time-to-digital converter (TDC), transformer.
Transmit filter using a reference clock that is no integer multiple of the symbol clock
Advances in Digital RF Architectures and Digitally-Assisted RF
Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels
Ieee Transactions on Very Large Scale Integration Systems, Feb 1, 2001
Page 1. 42 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 1, FEBRU... more Page 1. 42 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 1, FEBRUARY 2001 Speed, Power, Area, and Latency Tradeoffs in Adaptive FIR Filtering for PRML Read Channels ...
完全ディジタルPLL回路の設計 : ディープ・サブミクロンCMOSプロセスで実現する
Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOS
2007 Ieee International Symposium on Circuits and Systems, May 27, 2007
The paper proposed estimation techniques and compensation algorithms against CMOS device variabil... more The paper proposed estimation techniques and compensation algorithms against CMOS device variability in an all-digital RF polar transmitter. The transmitter is built using dense and fast digital logic and comprises two converters that transform transmit modulation from digital to RF frequency/phase and amplitude analog domains. The converters built with segmented banks consist of a large number of unit-weighted devices which exhibit a certain level of random and systematic mismatch. The techniques presented are employed in a commercial single-chip GSM/EDGE radio realized in 90 nm CMOS
Interpolative all-digital phase locked loop
Direct RF sampling mixer with recursive filtering in charge domain
2004 Ieee International Symposium on Circuits and Systems, May 23, 2004
ABSTRACT We present a novel direct RF sampling technique in which an input RF signal is converted... more ABSTRACT We present a novel direct RF sampling technique in which an input RF signal is converted to a current waveform, gated and integrated on a sampling capacitor. A rotating capacitor shares this charge with the main sampling capacitor and transfers it to a subsequent ...
Phase detector and methodology
Digital Phase Locked Loop with Gear Shifting
Methods and devices for generating a representation of a 3D scene at very high speed
All-Digital PLL and GSM/EDGE Transmitter in 90nm CMOS, ISSCC 2005, Session 17, RF Cellular ICs/17.5, Texas Instruments, Dallas
Radio-Frequency Digital-to-Analog Converters: Implementation in Nanoscale CMOS
Frequency synthesizers with amplitude control
Oscillator with favorable startup
Capacitor arrangement for oscillator
Transformer Based Impedance Matching Network And Related Power Amplifier, ADPLL And Transmitter Based Thereon
CMOS Tuner And Related Tuning Algorithm For A Passive Adaptive Antenna Matching Network Suitable For Use With Agile RF Transceivers
Wideband Digitally Controlled Injection-Locked Oscillator
60 GHz Wideband Class E/F2 Power Amplifier
Switching current source radio frequency oscillator
60 GHz frequency generator incorporating third harmonic boost and extraction
Split transformer based LC-tank digitally controlled oscillator
Split transformer based digitally controlled oscillator and DC-coupled buffer circuit therefor
Fractional-N all digital phase locked loop incorporating look ahead time to digital converter
Fractional-N Frequency Synthesizer Incorporating Cyclic Digital-To-Time And Time-To-Digital Circuit Pair
Millimeter-Wave Digitally Intensive Frequency Generation in CMOS
Quadrature lc tank digitally controlled ring oscillator
Characterization and Modeling of Multiple Coupled Inductors Based on On-Chip Four-Port Measurement
Tuning Range Extension of a Transformer-Based Oscillator Through Common-Mode Colpitts Resonance
System Design of a 2.75-mW Discrete-Time Superheterodyne Receiver for Bluetooth Low Energy
Software assisted Digital RF Processor (DRP{\texttrademark}) for single-chip GSM radio in 90 nm CMOS
A 0.017 mm2 9.4--14.6 GHz LC-tank Digitally Controlled Oscillator in 40nm CMOS for All-Digital Frequency Synthesis for Wireline Communications
A Reference-Free Capacitive-Discharging Oscillator Architecture Consuming 44.4 pW/75.6 nW at 2.8 Hz
Field-Programmable Gate Arrays Energy-and Time-Efficient Matrix Multiplication on FPGAs............ J.-W. Jang, SB Choi, and VK Prasanna 1305
7 OFDM Transform-Domain Receivers for Multi-Standard Communications
ADCs and DACs for Software-Defined Radio
Shower of IC Stars at SSCS Chapters in Taiwan: SSCS DL Bogdan Staszewski, Texas Tech's Donald YC Lie, and the Venerable KC Smith Visit in April and May [People]
DTC and TDC IC Design for Ultra-Low-Power ADPLL
13 CMOS RF Power Amplifiers for Mobile Communications
General Chair Peggy Ping Gui Southern Methodist University Dallas TX, 75257 Email: pgui@ engr. smu. edu
Program for the 6th IEEE Dallas/CAS Workshop (DCAS-07)
14 Digitally Assisted RF Architectures: Two Illustrative Designs
CMOS RF Circuits for Wireless Applications
Conference Chair Terry Blake
9 Oversampled ADC Using VCO-Based Quantizers
A sigma-delta ADC with a built-in anti-aliasing filter for Bluetooth receiver in 130nm digital process
Accurate self-characterization of mismatches in a capacitor array of a digitally-controlled oscillator
Digitally controlled oscillator in a 65nm GSM/EDGE transceiver with built-in compensation for capacitor mismatches
F1: Advanced transmitters for wireless infrastructure
Cellular and wireless LAN transceivers: From systems to circuit design
Digital RF Processor (DRP{\texttrademark}) for Cellular Radios
24.1 A 770pJ/b 0.85 V 0.3 mm 2 DCO-based phase-tracking RX featuring direct demodulation and data-aided carrier tracking for IoT applications
19.6 A 0.2 V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3 kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications
15.5 Cryo-CMOS circuits and systems for scalable quantum computing
A 38 GHz on-chip antenna in 28-nm CMOS using artificial magnetic conductor for 5G wireless systems
Adaptive MultiMode RF FrontEnd Circuits
A 0.5 ps 1.4 mW 50MS/s Nyquist bandwidth time amplifier based two-step flash-$\Delta$$\Sigma$ time-to-digital converter
Exponential extended flash time-to-digital converter
A 3.5--6.8 GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH Delta\DeltaDelta$\Sigma$ TDC for low in-band phase noise
A 0.034 mm 2, 725fs RMS jitter, 1.8\%/V frequency-pushing, 10.8--19.3 GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS
A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75 mW high-IF discrete-time receiver, and 3.6 mW all-digital transmitter
A 5.9 GHz RFDAC-based outphasing power amplifier in 40-nm CMOS with 49.2\% efficiency and 22.2 dBm power
An CMOS impedance sensor for MEMS adaptive antenna matching
A 60 GHz 25\% tuning range frequency generator with implicit divider based on third harmonic extraction with 182 dBc/Hz FoM
A 0.5 V 0.5 mW switching current source oscillator
1 RF Building Blocks for the Next-Gen Wireless Systems
Mitigation of CMOS Device Variability in Digital RF Processor
Digital RF Processor (DRP ‚{\~N}{{\textcent}})
Time-Domain Techniques for mm-Wave Frequency Generation
Time-to-Digital Converter (TDC) for WiMAX ADPLL in State-of-The-Art 40-nm CMOS
A Digitally Controlled Wide-band Frequency Modulator
Low Power, All-Digital Fractional-N Frequency Synthesizers for Multi-GHz Applications
An Ultra-Low-Power ADPLL for WPAN Applications
A Highly Selective, Very Linear Low Noise Transconductance Amplifier Capable of Large-Signal Handling for Current-Mode Receivers Front-End
High-performance AD and DA converters, IC design in scaled technologies, and time-domain signal processing: advances in analog circuit design 2014
Digitally-assisted analog and RF CMOS circuit design for software-defined radio
Wireless technologies: circuits, systems, and devices
Overview of FrontEnd RF Passive Integration into SoCs
Reduced External Hardware and Reconfigurable RF Receiver Front Ends for Wireless Mobile Terminals
SoftwareDefined Transceivers