Fabian Andrade | UFBA - Federal University of Bahia (original) (raw)

Papers by Fabian Andrade

Research paper thumbnail of A Graphical Interface Learning Tool for Image Processing Through Analog CNN

Circuits, Systems, and Signal Processing

Research paper thumbnail of Compact CMOS Analog Multiplier Free of Voltage Reference Generators

Journal of Integrated Circuits and Systems, 2020

This work presents a CMOS four quadrant analog multiplier architecture for application as the syn... more This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.

Research paper thumbnail of Filtragem de imagens em escala de cinza por meio de rede neuronal celular analógica em tecnologia CMOS

Este trabalho aborda a implementação em nível de simulação de operações de filtragem de imagens e... more Este trabalho aborda a implementação em nível de simulação de operações de filtragem de imagens em uma CNN (Cellular Neuronal Network-Rede Neuronal Celular) analógica desenvolvida em tecnologia CMOS (Complementary metal oxide semiconductor). Tal circuito apresenta uma arquitetura projetada para a implementação futura em próteses retinianas, sendo imprescindível, portanto, que processe funções de filtragem adequadamente. Utilizou-se uma versão modificada do algoritmo denominado CMA (Center of Mass Algorithm-Algoritmo do Centro de Massa) visando encontrar os coeficientes adequados que configuram a rede para a função desejada. Uma ferramenta com interface gráfica foi desenvolvida para aplicação do treinamento, e testada em operações de processamento de imagens já aplicadas em CNN. Os resultados das simulações são avaliados e mostram um desempenho satisfatório, considerando as limitações da rede utilizada. Além disso, a metodologia seguida permite que melhorias realizadas posteriormente na rede ou no método de treinamento sejam integradas de forma simples.

Research paper thumbnail of Using Two-Dimensional DC Characterization to Improve Distortion Level of Analog Multipliers

2019 4th International Symposium on Instrumentation Systems, Circuits and Transducers (INSCIT), 2019

Research paper thumbnail of Modeling Short-Channel Effects for Design by Hand with MOSFET Series Association

2019 Latin American Electron Devices Conference (LAEDC), 2019

Research paper thumbnail of Improvements on the Design of the Low Saturation Onset Transistor

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2020

The LSOT (low saturation onset transistor) is a four-transistor network that emulates a MOS devic... more The LSOT (low saturation onset transistor) is a four-transistor network that emulates a MOS device with much lower saturation onset voltage by compensating the reverse saturation component of the drain current through its main transistor. Due to current overcompensation in the structure, the DC output characteristic of the equivalent device may present an undesirable hump. This work presents a methodology to properly size the LSOT leading to a smoother characteristic. Moreover, the addition of a simple switch to automatically cut-off an auxiliary branch of the LSOT structure is also proposed, to allow the use of shorter devices without augmenting overall power.

Research paper thumbnail of Low Saturation Onset MOS Transistor: an Equivalent Network

2019 34th Symposium on Microelectronics Technology and Devices (SBMicro), 2019

In this work a four-transistor network is presented which is almost equivalent to a single transi... more In this work a four-transistor network is presented which is almost equivalent to a single transistor with lower saturation onset voltage. Output characteristics are analyzed and the reduction on saturation onset voltage is assessed. This network is adequate to replace output transistors in cascode mirrors, so that the low output conductance is achieved with much less prejudice to output voltage swing.

Research paper thumbnail of A CMOS Analog Two-Layer Full Signal Range Cellular Neural Network for Image Filtering

This work presents the training and realization of a CMOS analog two-layer FSR CNN obtained throu... more This work presents the training and realization of a CMOS analog two-layer FSR CNN obtained through the extension of an existing one-layer version. A genetic algorithm has been developed for the learning process and has been applied to the determination of templates parameters in a gray-scale image filtering task. Networks implementing first order Butterworth spatial filters have been simulated and the results are compared to its ideal model and FFT computations, allowing to validate the proposed learning process and circuit applicability.

Research paper thumbnail of Proportional Source Transconductances Integrator for CMOS Analog Filtering with Calibration

A CMOS current-mode companding integrator for application in continuous time analog filters is pr... more A CMOS current-mode companding integrator for application in continuous time analog filters is presented. It is a modified version of the Proportional Source Transconductances Integrator. The main improvements are increased compactness, larger first-order behavior bandwidth and manual calibration capability. The circuit has been designed in a CMOS 130 nm technology and analyzed through simulation, featuring: −20 dB/decade slope from 7 kHz to 80 MHz, 180 μW-static power and 3rd order intermodulation distortion lower than −40 dB for input sweep of +0.8 μA.

Research paper thumbnail of Evaluation of Distortion Level in Analog Multipliers through DC Analysis Only

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), 2019

This work presents a methodology for determining figures of merit to assess distortion in analog ... more This work presents a methodology for determining figures of merit to assess distortion in analog multipliers using only DC analysis. Besides the direct determination of two dimensional integral nonlinear function, the distortion coefficients are calculated to fit the DC transfer surface and are used to estimate the total harmonic distortions for single and double input. Simulation and experimental results demonstrate that figures of merit determined either by AC or DC analysis agree with enough reliability.

Research paper thumbnail of On the Distortion Analysis of Electronic, Analog Multipliers

AEU - International Journal of Electronics and Communications, 2021

Abstract This work presents a comparison between three distinct criteria for evaluating distortio... more Abstract This work presents a comparison between three distinct criteria for evaluating distortion of analog multipliers: the two-dimensional integral nonlinear function and the double input total harmonic distortion, both proposed by us, and the conventional single input total harmonic distortion. A methodology is proposed to experimentally determine these figures of merit using DC characterization. Intending to fit a two-variable polynomial to the multiplier DC transfer surface, distortion coefficients are obtained which can be used to assess the total harmonic distortions. Four different topologies of analog multipliers in CMOS technology have been characterized, by simulation or measurement, and the results demonstrate that DC analysis provides meaningful and reliable distortion figures of merit. An experimental analysis over three additional analog multipliers of commercial integrated circuits using DC characterization is also accomplished.

Research paper thumbnail of Distortion analysis of integrated analog multipliers: DC versus AC approaches

2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), 2016

This work presents a theoretical comparison between three distinct criteria for evaluating distor... more This work presents a theoretical comparison between three distinct criteria for evaluating distortion of analog multipliers: the two dimensional integral nonlinear function and the double input total harmonic distortion, both proposed by us, and the conventional single input total harmonic distortion. DC measurements have been accomplished over commercially available devices in order to identify difficulties and advantages implied in the methodology for determining the two dimensional integral nonlinear function.

Research paper thumbnail of Image filtering in a CMOS analog CNN

2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS), 2015

Research paper thumbnail of CMOS Analog Four-Quadrant Multiplier Free of Voltage Reference Generators

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI), 2019

This work presents a CMOS four quadrant analog multiplier architecture for application as the syn... more This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. The circuit has voltage-mode inputs and a current-mode output and includes a signal application method that avoids voltage or current reference generators. Simulations have been accomplished for a CMOS 130 nm technology, featuring pm50mathrmmV\pm 50\ \mathrm{mV}pm50mathrmmV input voltage range, 60mumathrmW60\ \mu\mathrm{W}60mumathrmW static power and −25 dB maximum THD. The active area is 346mumathrmm2346\ \mu\mathrm{m}^{2}346mumathrmm2.

Research paper thumbnail of A Very Compact CMOS Analog Multiplier for Application in CNN Synapses

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)

This work presents a CMOS analog multiplier architecture for application as the synapse in analog... more This work presents a CMOS analog multiplier architecture for application as the synapse in analog cellular neural networks. The circuit comprises two voltage-mode inputs and a current-mode output. Simulated performance features obtained from a circuit design in CMOS 130 nm technology include: +100 mV input voltage range, 23 µW static power, −32 dB maximum total harmonic distortion and −3 dB bandwidth of 51.2 kHz. The active area totalizes only 40 µm2.

Research paper thumbnail of CNN Learning for Image Processing: Center of Mass versus Genetic Algorithms

Anais de XXXVI Simpósio Brasileiro de Telecomunicações e Processamento de Sinais

Research paper thumbnail of A Graphical Interface Learning Tool for Image Processing Through Analog CNN

Circuits, Systems, and Signal Processing

Research paper thumbnail of Compact CMOS Analog Multiplier Free of Voltage Reference Generators

Journal of Integrated Circuits and Systems, 2020

This work presents a CMOS four quadrant analog multiplier architecture for application as the syn... more This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.

Research paper thumbnail of Filtragem de imagens em escala de cinza por meio de rede neuronal celular analógica em tecnologia CMOS

Este trabalho aborda a implementação em nível de simulação de operações de filtragem de imagens e... more Este trabalho aborda a implementação em nível de simulação de operações de filtragem de imagens em uma CNN (Cellular Neuronal Network-Rede Neuronal Celular) analógica desenvolvida em tecnologia CMOS (Complementary metal oxide semiconductor). Tal circuito apresenta uma arquitetura projetada para a implementação futura em próteses retinianas, sendo imprescindível, portanto, que processe funções de filtragem adequadamente. Utilizou-se uma versão modificada do algoritmo denominado CMA (Center of Mass Algorithm-Algoritmo do Centro de Massa) visando encontrar os coeficientes adequados que configuram a rede para a função desejada. Uma ferramenta com interface gráfica foi desenvolvida para aplicação do treinamento, e testada em operações de processamento de imagens já aplicadas em CNN. Os resultados das simulações são avaliados e mostram um desempenho satisfatório, considerando as limitações da rede utilizada. Além disso, a metodologia seguida permite que melhorias realizadas posteriormente na rede ou no método de treinamento sejam integradas de forma simples.

Research paper thumbnail of Using Two-Dimensional DC Characterization to Improve Distortion Level of Analog Multipliers

2019 4th International Symposium on Instrumentation Systems, Circuits and Transducers (INSCIT), 2019

Research paper thumbnail of Modeling Short-Channel Effects for Design by Hand with MOSFET Series Association

2019 Latin American Electron Devices Conference (LAEDC), 2019

Research paper thumbnail of Improvements on the Design of the Low Saturation Onset Transistor

2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2020

The LSOT (low saturation onset transistor) is a four-transistor network that emulates a MOS devic... more The LSOT (low saturation onset transistor) is a four-transistor network that emulates a MOS device with much lower saturation onset voltage by compensating the reverse saturation component of the drain current through its main transistor. Due to current overcompensation in the structure, the DC output characteristic of the equivalent device may present an undesirable hump. This work presents a methodology to properly size the LSOT leading to a smoother characteristic. Moreover, the addition of a simple switch to automatically cut-off an auxiliary branch of the LSOT structure is also proposed, to allow the use of shorter devices without augmenting overall power.

Research paper thumbnail of Low Saturation Onset MOS Transistor: an Equivalent Network

2019 34th Symposium on Microelectronics Technology and Devices (SBMicro), 2019

In this work a four-transistor network is presented which is almost equivalent to a single transi... more In this work a four-transistor network is presented which is almost equivalent to a single transistor with lower saturation onset voltage. Output characteristics are analyzed and the reduction on saturation onset voltage is assessed. This network is adequate to replace output transistors in cascode mirrors, so that the low output conductance is achieved with much less prejudice to output voltage swing.

Research paper thumbnail of A CMOS Analog Two-Layer Full Signal Range Cellular Neural Network for Image Filtering

This work presents the training and realization of a CMOS analog two-layer FSR CNN obtained throu... more This work presents the training and realization of a CMOS analog two-layer FSR CNN obtained through the extension of an existing one-layer version. A genetic algorithm has been developed for the learning process and has been applied to the determination of templates parameters in a gray-scale image filtering task. Networks implementing first order Butterworth spatial filters have been simulated and the results are compared to its ideal model and FFT computations, allowing to validate the proposed learning process and circuit applicability.

Research paper thumbnail of Proportional Source Transconductances Integrator for CMOS Analog Filtering with Calibration

A CMOS current-mode companding integrator for application in continuous time analog filters is pr... more A CMOS current-mode companding integrator for application in continuous time analog filters is presented. It is a modified version of the Proportional Source Transconductances Integrator. The main improvements are increased compactness, larger first-order behavior bandwidth and manual calibration capability. The circuit has been designed in a CMOS 130 nm technology and analyzed through simulation, featuring: −20 dB/decade slope from 7 kHz to 80 MHz, 180 μW-static power and 3rd order intermodulation distortion lower than −40 dB for input sweep of +0.8 μA.

Research paper thumbnail of Evaluation of Distortion Level in Analog Multipliers through DC Analysis Only

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), 2019

This work presents a methodology for determining figures of merit to assess distortion in analog ... more This work presents a methodology for determining figures of merit to assess distortion in analog multipliers using only DC analysis. Besides the direct determination of two dimensional integral nonlinear function, the distortion coefficients are calculated to fit the DC transfer surface and are used to estimate the total harmonic distortions for single and double input. Simulation and experimental results demonstrate that figures of merit determined either by AC or DC analysis agree with enough reliability.

Research paper thumbnail of On the Distortion Analysis of Electronic, Analog Multipliers

AEU - International Journal of Electronics and Communications, 2021

Abstract This work presents a comparison between three distinct criteria for evaluating distortio... more Abstract This work presents a comparison between three distinct criteria for evaluating distortion of analog multipliers: the two-dimensional integral nonlinear function and the double input total harmonic distortion, both proposed by us, and the conventional single input total harmonic distortion. A methodology is proposed to experimentally determine these figures of merit using DC characterization. Intending to fit a two-variable polynomial to the multiplier DC transfer surface, distortion coefficients are obtained which can be used to assess the total harmonic distortions. Four different topologies of analog multipliers in CMOS technology have been characterized, by simulation or measurement, and the results demonstrate that DC analysis provides meaningful and reliable distortion figures of merit. An experimental analysis over three additional analog multipliers of commercial integrated circuits using DC characterization is also accomplished.

Research paper thumbnail of Distortion analysis of integrated analog multipliers: DC versus AC approaches

2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), 2016

This work presents a theoretical comparison between three distinct criteria for evaluating distor... more This work presents a theoretical comparison between three distinct criteria for evaluating distortion of analog multipliers: the two dimensional integral nonlinear function and the double input total harmonic distortion, both proposed by us, and the conventional single input total harmonic distortion. DC measurements have been accomplished over commercially available devices in order to identify difficulties and advantages implied in the methodology for determining the two dimensional integral nonlinear function.

Research paper thumbnail of Image filtering in a CMOS analog CNN

2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS), 2015

Research paper thumbnail of CMOS Analog Four-Quadrant Multiplier Free of Voltage Reference Generators

2019 32nd Symposium on Integrated Circuits and Systems Design (SBCCI), 2019

This work presents a CMOS four quadrant analog multiplier architecture for application as the syn... more This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. The circuit has voltage-mode inputs and a current-mode output and includes a signal application method that avoids voltage or current reference generators. Simulations have been accomplished for a CMOS 130 nm technology, featuring pm50mathrmmV\pm 50\ \mathrm{mV}pm50mathrmmV input voltage range, 60mumathrmW60\ \mu\mathrm{W}60mumathrmW static power and −25 dB maximum THD. The active area is 346mumathrmm2346\ \mu\mathrm{m}^{2}346mumathrmm2.

Research paper thumbnail of A Very Compact CMOS Analog Multiplier for Application in CNN Synapses

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)

This work presents a CMOS analog multiplier architecture for application as the synapse in analog... more This work presents a CMOS analog multiplier architecture for application as the synapse in analog cellular neural networks. The circuit comprises two voltage-mode inputs and a current-mode output. Simulated performance features obtained from a circuit design in CMOS 130 nm technology include: +100 mV input voltage range, 23 µW static power, −32 dB maximum total harmonic distortion and −3 dB bandwidth of 51.2 kHz. The active area totalizes only 40 µm2.

Research paper thumbnail of CNN Learning for Image Processing: Center of Mass versus Genetic Algorithms

Anais de XXXVI Simpósio Brasileiro de Telecomunicações e Processamento de Sinais