dezsö sima | Óbuda University (original) (raw)
Papers by dezsö sima
2019 IEEE International Work Conference on Bioinspired Intelligence (IWOBI), 2019
The energy consumption of computer systems is generally an important design aspect. There are sev... more The energy consumption of computer systems is generally an important design aspect. There are several well-known solutions for reducing the power consumption of processors, among others ARM big.LITTLE architecture. In Linux systems, CPUFreq and CPUIdle governors are traditionally responsible for managing CPU consumption and performance. Our primary goal has been to develop a user-mode CPUFreq governor alternative that provides a suitable framework for the development of governors utilizing the features of big.LITTLE architectures.
The fierce demand for higher performance has provoked a dramatic evolution in the field of microp... more The fierce demand for higher performance has provoked a dramatic evolution in the field of microprocessors. In this paper we show that this immense performance increase could only be achieved by the subsequent introduction of temporal, issue and intrainstruction parallelism, in such a way that exploiting the full potential along one dimension gives rise to the additional introduction of parallelism along a further dimension. Moreover, the debut of each basic technique used to implement parallelism along a given dimension inevitably calls for the introduction of further innovative techniques in order to fully capitalize on the potential of the basic technique. In this way an underlying deterministic framework can be identified for the fascinating evolution of microprocessors, which is presented in our paper.
From the Publisher: This timely book provides an unconventional and up-to-date overview of all th... more From the Publisher: This timely book provides an unconventional and up-to-date overview of all the important computer architectures and is one of the first texts to present all the relevant concepts of advanced architecture classes by exploring their design spaces. Advanced Computer Architectures will prove an indispensable guide for anyone who needs to be acquainted with the relevant concepts and solutions introduced in recent years to the dramatically changing world of computer architecture. For the student of advanced level courses in computer architecture, this book will provide a comprehensive and accessible overview of the subject whilst its strong practical orientation will make it an invaluable reference for the practitioner.
Journal of Universal Computer Science, 2006
Register renaming is a technique to remove false data dependencies—write after read (WAR) and wri... more Register renaming is a technique to remove false data dependencies—write after read (WAR) and write after write (WAW)— that occur in straight line code between register operands of subsequent instructions. 1-3 By eliminating related precedence requirements in the execution sequence of the instructions, renaming increases the average number of instructions that are available for parallel execution per cycle. This results in increased IPC (number of instructions executed per cycle). The identification and exploration of the design space of register-renaming lead to a comprehensive understanding of this intricate technique.
Microprocessors and Microsystems, 1999
2006 7th International Conference on Information Technology Based Higher Education and Training, 2006
The emergence of the knowledge based society as well as the rapid expansion of the number of stud... more The emergence of the knowledge based society as well as the rapid expansion of the number of students enrolled into higher education is an unmistakable international trend. As a consequence, the input necessary for delivering teaching materials is on to wane compare to that required for proper knowledge assessment. In addition, a usual deficiency of distance learning systems is the
Journal of Universal Computer Science, 2006
Proceedings of the IEEE, 2000
The incessant market demand for higher and higher processor performance called for a continuous i... more The incessant market demand for higher and higher processor performance called for a continuous increase of clock frequencies as well as an impressive evolution of the microarchitecture. In this paper, we focus on the latter, highlighting major microarchitectural improvements that were introduced to more effectively utilize instruction level parallelism (ILP) in commercial performance-oriented microprocessors. We will show that designers increased the throughput of the microarchitecture at the ILP level basically by subsequently introducing temporal, issue, and intrainstruction parallelism in such a way that exploiting parallelism along one dimension compelled to introduce parallelism along a new dimension as well to further increase performance. In addition, each basic technique used to implement parallel operation along a certain dimension inevitably caused processing bottlenecks in the microarchitecture, whose elimination gave birth to the introduction of innovative auxiliary techniques. On the other hand, the auxiliary techniques applied allow the basic technique of parallel operation to reach its limits, evoking the debut of a new dimension of parallel operation in the microarchitecture. The sequence of basic and auxiliary techniques coined to increase the efficiency of microarchitectures constitutes a fascinating framework for the evolution of microarchitectures, as presented in our paper.
Journal of Systems Architecture, 1999
While using the direct issue mode, dependent instructions cause issue blockages and thus an issue... more While using the direct issue mode, dependent instructions cause issue blockages and thus an issue bottleneck. Shelving is a technique to avoid this and to increase the sustained issue rate. It takes advantage of two concepts: (a) the decoupling of dependency checking from instruction issue and (b) signi®cantly widening the instruction window that is scanned in each clock cycle for executable instructions. In this paper we identify and explore the design space of shelving. We ®rst outline its main dimensions, then we present and discuss feasible design alternatives along three of its crucial dimensions. Finally, we point out which design choices have been made in important superscalar processors. For a concise graphical representation of the design space we make use of DS-trees. Ó
IEEE Micro, 2000
Register renaming is a technique to remove false data dependencies-write after read (WAR) and wri... more Register renaming is a technique to remove false data dependencies-write after read (WAR) and write after write (WAW)that occur in straight line code between register operands of subsequent instructions. 1-3 By eliminating related precedence requirements in the execution sequence of the instructions, renaming increases the average number of instructions that are available for parallel execution per cycle. This results in increased IPC (number of instructions executed per cycle).
IEEE Micro, 1997
C learly, instruction issue and execution are closely related: The more parallel the instruction ... more C learly, instruction issue and execution are closely related: The more parallel the instruction execution, the higher the requirements for the parallelism of instruction issue. Thus, we see the continuous and harmonized increase of parallelism in instruction issue and execution.
Rapidly increasing student numbers and spreading distance learning systems strengthen the urgent ... more Rapidly increasing student numbers and spreading distance learning systems strengthen the urgent need for effective knowledge assessment systems (KAS's). Recent KAS's have however, the deficiency of not providing intelligent assessment modules for eg the evaluation of freely formulated short answers including a few sentences or partially solved mathematical problems. The eMax KAS, developed at the Intelligent Knowledge Management Innovation Center
Journal of Universal Computer Science, 2006
Proceedings of The IEEE, 2004
The incessant market demand for higher and higher processor performance called for a continuous i... more The incessant market demand for higher and higher processor performance called for a continuous increase of clock frequencies as well as an impressive evolution of the microarchitecture. In this paper, we focus on the latter, highlighting major microarchitectural improvements that were introduced to more effectively utilize instruction level parallelism (ILP) in commercial performance-oriented microprocessors. We will show that designers increased the throughput of the microarchitecture at the ILP level basically by subsequently introducing temporal, issue, and intrainstruction parallelism in such a way that exploiting parallelism along one dimension compelled to introduce parallelism along a new dimension as well to further increase performance. In addition, each basic technique used to implement parallel operation along a certain dimension inevitably caused processing bottlenecks in the microarchitecture, whose elimination gave birth to the introduction of innovative auxiliary techniques. On the other hand, the auxiliary techniques applied allow the basic technique of parallel operation to reach its limits, evoking the debut of a new dimension of parallel operation in the microarchitecture. The sequence of basic and auxiliary techniques coined to increase the efficiency of microarchitectures constitutes a fascinating framework for the evolution of microarchitectures, as presented in our paper.
2006 7th International Conference on Information Technology Based Higher Education and Training, 2006
The emergence of the knowledge based society as well as the rapid expansion of the number of stud... more The emergence of the knowledge based society as well as the rapid expansion of the number of students enrolled into higher education is an unmistakable international trend. As a consequence, the input necessary for delivering teaching materials is on to wane compare to that required for proper knowledge assessment. In addition, a usual deficiency of distance learning systems is the
2019 IEEE International Work Conference on Bioinspired Intelligence (IWOBI), 2019
The energy consumption of computer systems is generally an important design aspect. There are sev... more The energy consumption of computer systems is generally an important design aspect. There are several well-known solutions for reducing the power consumption of processors, among others ARM big.LITTLE architecture. In Linux systems, CPUFreq and CPUIdle governors are traditionally responsible for managing CPU consumption and performance. Our primary goal has been to develop a user-mode CPUFreq governor alternative that provides a suitable framework for the development of governors utilizing the features of big.LITTLE architectures.
The fierce demand for higher performance has provoked a dramatic evolution in the field of microp... more The fierce demand for higher performance has provoked a dramatic evolution in the field of microprocessors. In this paper we show that this immense performance increase could only be achieved by the subsequent introduction of temporal, issue and intrainstruction parallelism, in such a way that exploiting the full potential along one dimension gives rise to the additional introduction of parallelism along a further dimension. Moreover, the debut of each basic technique used to implement parallelism along a given dimension inevitably calls for the introduction of further innovative techniques in order to fully capitalize on the potential of the basic technique. In this way an underlying deterministic framework can be identified for the fascinating evolution of microprocessors, which is presented in our paper.
From the Publisher: This timely book provides an unconventional and up-to-date overview of all th... more From the Publisher: This timely book provides an unconventional and up-to-date overview of all the important computer architectures and is one of the first texts to present all the relevant concepts of advanced architecture classes by exploring their design spaces. Advanced Computer Architectures will prove an indispensable guide for anyone who needs to be acquainted with the relevant concepts and solutions introduced in recent years to the dramatically changing world of computer architecture. For the student of advanced level courses in computer architecture, this book will provide a comprehensive and accessible overview of the subject whilst its strong practical orientation will make it an invaluable reference for the practitioner.
Journal of Universal Computer Science, 2006
Register renaming is a technique to remove false data dependencies—write after read (WAR) and wri... more Register renaming is a technique to remove false data dependencies—write after read (WAR) and write after write (WAW)— that occur in straight line code between register operands of subsequent instructions. 1-3 By eliminating related precedence requirements in the execution sequence of the instructions, renaming increases the average number of instructions that are available for parallel execution per cycle. This results in increased IPC (number of instructions executed per cycle). The identification and exploration of the design space of register-renaming lead to a comprehensive understanding of this intricate technique.
Microprocessors and Microsystems, 1999
2006 7th International Conference on Information Technology Based Higher Education and Training, 2006
The emergence of the knowledge based society as well as the rapid expansion of the number of stud... more The emergence of the knowledge based society as well as the rapid expansion of the number of students enrolled into higher education is an unmistakable international trend. As a consequence, the input necessary for delivering teaching materials is on to wane compare to that required for proper knowledge assessment. In addition, a usual deficiency of distance learning systems is the
Journal of Universal Computer Science, 2006
Proceedings of the IEEE, 2000
The incessant market demand for higher and higher processor performance called for a continuous i... more The incessant market demand for higher and higher processor performance called for a continuous increase of clock frequencies as well as an impressive evolution of the microarchitecture. In this paper, we focus on the latter, highlighting major microarchitectural improvements that were introduced to more effectively utilize instruction level parallelism (ILP) in commercial performance-oriented microprocessors. We will show that designers increased the throughput of the microarchitecture at the ILP level basically by subsequently introducing temporal, issue, and intrainstruction parallelism in such a way that exploiting parallelism along one dimension compelled to introduce parallelism along a new dimension as well to further increase performance. In addition, each basic technique used to implement parallel operation along a certain dimension inevitably caused processing bottlenecks in the microarchitecture, whose elimination gave birth to the introduction of innovative auxiliary techniques. On the other hand, the auxiliary techniques applied allow the basic technique of parallel operation to reach its limits, evoking the debut of a new dimension of parallel operation in the microarchitecture. The sequence of basic and auxiliary techniques coined to increase the efficiency of microarchitectures constitutes a fascinating framework for the evolution of microarchitectures, as presented in our paper.
Journal of Systems Architecture, 1999
While using the direct issue mode, dependent instructions cause issue blockages and thus an issue... more While using the direct issue mode, dependent instructions cause issue blockages and thus an issue bottleneck. Shelving is a technique to avoid this and to increase the sustained issue rate. It takes advantage of two concepts: (a) the decoupling of dependency checking from instruction issue and (b) signi®cantly widening the instruction window that is scanned in each clock cycle for executable instructions. In this paper we identify and explore the design space of shelving. We ®rst outline its main dimensions, then we present and discuss feasible design alternatives along three of its crucial dimensions. Finally, we point out which design choices have been made in important superscalar processors. For a concise graphical representation of the design space we make use of DS-trees. Ó
IEEE Micro, 2000
Register renaming is a technique to remove false data dependencies-write after read (WAR) and wri... more Register renaming is a technique to remove false data dependencies-write after read (WAR) and write after write (WAW)that occur in straight line code between register operands of subsequent instructions. 1-3 By eliminating related precedence requirements in the execution sequence of the instructions, renaming increases the average number of instructions that are available for parallel execution per cycle. This results in increased IPC (number of instructions executed per cycle).
IEEE Micro, 1997
C learly, instruction issue and execution are closely related: The more parallel the instruction ... more C learly, instruction issue and execution are closely related: The more parallel the instruction execution, the higher the requirements for the parallelism of instruction issue. Thus, we see the continuous and harmonized increase of parallelism in instruction issue and execution.
Rapidly increasing student numbers and spreading distance learning systems strengthen the urgent ... more Rapidly increasing student numbers and spreading distance learning systems strengthen the urgent need for effective knowledge assessment systems (KAS's). Recent KAS's have however, the deficiency of not providing intelligent assessment modules for eg the evaluation of freely formulated short answers including a few sentences or partially solved mathematical problems. The eMax KAS, developed at the Intelligent Knowledge Management Innovation Center
Journal of Universal Computer Science, 2006
Proceedings of The IEEE, 2004
The incessant market demand for higher and higher processor performance called for a continuous i... more The incessant market demand for higher and higher processor performance called for a continuous increase of clock frequencies as well as an impressive evolution of the microarchitecture. In this paper, we focus on the latter, highlighting major microarchitectural improvements that were introduced to more effectively utilize instruction level parallelism (ILP) in commercial performance-oriented microprocessors. We will show that designers increased the throughput of the microarchitecture at the ILP level basically by subsequently introducing temporal, issue, and intrainstruction parallelism in such a way that exploiting parallelism along one dimension compelled to introduce parallelism along a new dimension as well to further increase performance. In addition, each basic technique used to implement parallel operation along a certain dimension inevitably caused processing bottlenecks in the microarchitecture, whose elimination gave birth to the introduction of innovative auxiliary techniques. On the other hand, the auxiliary techniques applied allow the basic technique of parallel operation to reach its limits, evoking the debut of a new dimension of parallel operation in the microarchitecture. The sequence of basic and auxiliary techniques coined to increase the efficiency of microarchitectures constitutes a fascinating framework for the evolution of microarchitectures, as presented in our paper.
2006 7th International Conference on Information Technology Based Higher Education and Training, 2006
The emergence of the knowledge based society as well as the rapid expansion of the number of stud... more The emergence of the knowledge based society as well as the rapid expansion of the number of students enrolled into higher education is an unmistakable international trend. As a consequence, the input necessary for delivering teaching materials is on to wane compare to that required for proper knowledge assessment. In addition, a usual deficiency of distance learning systems is the