Razaidi Hussin | Universiti Malaysia Perlis (UniMAP) (original) (raw)
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Papers by Razaidi Hussin
Semiconductor Electronics, 2006. ICSE' …, Jan 1, 2006
This paper presents the methods required to implement a high speed and high performance parallel ... more This paper presents the methods required to implement a high speed and high performance parallel complex number multiplier. The designs are structured using Radix-4 Modified Booth Algorithm and Wallace tree. These two techniques are employed to speed up the multiplication process as their capability to reduce partial products generation to 11/2 and compress partial product term by a ratio of 3:2. Despite that, carry save-adders (CSA) is used to enhance the speed of addition process for the system. The system has been designed efriciently using VHDL codes for 16x16-bit signed numbers and successfully simulated and synthesized using ModelSim XE II 5.8c and Xilinx ISE 6.1i. As a proof of concept, the system is implemented on Xilinx Virtex-It Pro FPGA board.
… Design, Jan 1, 2008
in this paper, we present the design of an efficient multiplication unit. This multiplier archite... more in this paper, we present the design of an efficient multiplication unit. This multiplier architecture is based on Radix 4 Booth multiplier. In order to improve his architecture, we have made 2 enhancements. The first is to modify the Wen-Chang's Modified Booth Encoder (MBE) since it is the fastest scheme to generate a partial product. However, when implementing this MBE with the Simplified Sign Extension (SSE) method, the multiplication's output is incorrect. The 2 nd part is to improve the delay in the 4:2 compressor circuit. The redesigned 4:2 compressor reduced the delay of the Carry signal. This modification has been made by rearranging the Boolean equation of the Carry signal. This architecture has been designed using Quartus II. The Gajski rule has been adopted in order to estimate the delay and size of the circuit. The total transistor count for this new multiplier is being a slightly bigger. This is due to the new MBE which is uses more transistor. However in performance speed, this efficiency multiplier is quite good. The propagation delay is reduced by about 2% -7% from other designers.
structure
In this paper, we attempt to redesign the 4:2 compressors. Since its inception by Weinberger in 1... more In this paper, we attempt to redesign the 4:2 compressors. Since its inception by Weinberger in 1981[1], this concept of compressor has been used in most digital multiplications and multi operand operation scheme. The original of 4:2 compressor has been build using the full adder unit. Hence this compressor is no improvement compare using Wallace tree or other tree structure. Early 90's some designer has modified the 4:2 compressor in order to reduce the critical path. As a result, a worse case to cross a level of 4:2 compressor is 3 XOR [4]. While in this paper, we have redesign 4:2 compressor based on modification of 4:2 compressor . This design has been simulated using Quartus II software to verify the circuit. As a result, total transistor used in our compressor is less 4 than the modified 4:2 compressor and less 2 transistor than the original 4:2 compressor. In term of speed, the critical path of Carry Out signal is same as the original 4:2 compressor. Our compressor is 0.05% faster than modified 4:2 compressor.
… , 2006. ICSE'06. …, Jan 1, 2006
The user has requested enhancement of the downloaded file.
Feature extraction of speech is one of the most important issues in the field of speech recogniti... more Feature extraction of speech is one of the most important issues in the field of speech recognition and representative of the speech. Mel Frequency Cepstral Coefficient (MFCC) is one the most important features required among various kinds of speech application. In this paper, ...
Semiconductor Electronics, 2006. ICSE' …, Jan 1, 2006
This paper presents the methods required to implement a high speed and high performance parallel ... more This paper presents the methods required to implement a high speed and high performance parallel complex number multiplier. The designs are structured using Radix-4 Modified Booth Algorithm and Wallace tree. These two techniques are employed to speed up the multiplication process as their capability to reduce partial products generation to 11/2 and compress partial product term by a ratio of 3:2. Despite that, carry save-adders (CSA) is used to enhance the speed of addition process for the system. The system has been designed efriciently using VHDL codes for 16x16-bit signed numbers and successfully simulated and synthesized using ModelSim XE II 5.8c and Xilinx ISE 6.1i. As a proof of concept, the system is implemented on Xilinx Virtex-It Pro FPGA board.
… Design, Jan 1, 2008
in this paper, we present the design of an efficient multiplication unit. This multiplier archite... more in this paper, we present the design of an efficient multiplication unit. This multiplier architecture is based on Radix 4 Booth multiplier. In order to improve his architecture, we have made 2 enhancements. The first is to modify the Wen-Chang's Modified Booth Encoder (MBE) since it is the fastest scheme to generate a partial product. However, when implementing this MBE with the Simplified Sign Extension (SSE) method, the multiplication's output is incorrect. The 2 nd part is to improve the delay in the 4:2 compressor circuit. The redesigned 4:2 compressor reduced the delay of the Carry signal. This modification has been made by rearranging the Boolean equation of the Carry signal. This architecture has been designed using Quartus II. The Gajski rule has been adopted in order to estimate the delay and size of the circuit. The total transistor count for this new multiplier is being a slightly bigger. This is due to the new MBE which is uses more transistor. However in performance speed, this efficiency multiplier is quite good. The propagation delay is reduced by about 2% -7% from other designers.
structure
In this paper, we attempt to redesign the 4:2 compressors. Since its inception by Weinberger in 1... more In this paper, we attempt to redesign the 4:2 compressors. Since its inception by Weinberger in 1981[1], this concept of compressor has been used in most digital multiplications and multi operand operation scheme. The original of 4:2 compressor has been build using the full adder unit. Hence this compressor is no improvement compare using Wallace tree or other tree structure. Early 90's some designer has modified the 4:2 compressor in order to reduce the critical path. As a result, a worse case to cross a level of 4:2 compressor is 3 XOR [4]. While in this paper, we have redesign 4:2 compressor based on modification of 4:2 compressor . This design has been simulated using Quartus II software to verify the circuit. As a result, total transistor used in our compressor is less 4 than the modified 4:2 compressor and less 2 transistor than the original 4:2 compressor. In term of speed, the critical path of Carry Out signal is same as the original 4:2 compressor. Our compressor is 0.05% faster than modified 4:2 compressor.
… , 2006. ICSE'06. …, Jan 1, 2006
The user has requested enhancement of the downloaded file.
Feature extraction of speech is one of the most important issues in the field of speech recogniti... more Feature extraction of speech is one of the most important issues in the field of speech recognition and representative of the speech. Mel Frequency Cepstral Coefficient (MFCC) is one the most important features required among various kinds of speech application. In this paper, ...