Deepak Gangadharan | University of Pennsylvania (original) (raw)

Papers by Deepak Gangadharan

2021 IEEE 93rd Vehicular Technology Conference (VTC2021-Spring)

With the rise in state-of-the-art communication modes for vehicles such as vehicle to vehicle (V2... more With the rise in state-of-the-art communication modes for vehicles such as vehicle to vehicle (V2V), vehicle to infrastructure (V2I) and vehicle to cloud (V2C), modern vehicles are increasingly being connected to cloud and fog/edge nodes. These vehicle connectivity modes have enabled the realization of Vehicular Edge Computing (VEC) paradigm, whereby vehicles can leverage fog/edge node resources for storage/computation. In a VEC system, vehicles receive very important and large quantity of data from edge nodes, which is termed as data delivery. In addition, edge nodes can execute some services and send the results back to the vehicle, which is called service delivery. Fast and efficient edge resource allocation for data/service delivery is important in order to serve as many vehicles as possible in the VEC system. However, edge resource allocation is complex with large number of edges and vehicles, while also considering vehicle flow parameters. In this work, we propose Edge-Pairwise Optimal Data/Service Delivery (E-PODS), which is a fast and efficient heuristic for data/service delivery. Through experiments with synthetic and real vehicular traces, we demonstrate that E-PODS is considerably faster than the optimal approach, while making resource allocations that are close to optimal in terms of total edge bandwidth cost and number of serviced vehicles.

Reliability and flexibility are among the key required features of a framework used to model a sy... more Reliability and flexibility are among the key required features of a framework used to model a system. Existing approaches to design resource-constrained, soft-real time systems either provide guarantees for output quality or account for loss in the system, but not both. We propose two independent solutions where each modeling technique has both the above mentioned characteristics. We present a probabilistic analytical framework and a statistical model checking approach to design system-on-chips for low-cost multimedia systems. We apply the modeling techniques to size the output buffer in a video decoder. The results shows that, for our stochastic design metric, the analytical framework upper bounds (and relatively accurate) compare to the statistical model checking technique. Also, we observed significant reduction in resource usage (such as output buffer size) with tolerable loss in output quality.

Reliability and flexibility are among the key required features of a framework used to model a sy... more Reliability and flexibility are among the key required features of a framework used to model a system. Existing approaches to design resource-constrained, soft-real time systems either provide guarantees for output quality or account for loss in the system, but not both. We propose two independent solutions where each modeling technique has both the above mentioned characteristics. We present a probabilistic analytical framework and a statistical model checking approach to design system-on-chips for low-cost multimedia systems. We apply the modeling techniques to size the output buffer in a video decoder. The results shows that, for our stochastic design metric, the analytical framework upper bounds (and relatively accurate) compare to the statistical model checking technique. Also, we observed significant reduction in resource usage (such as output buffer size) with tolerable loss in output quality.

2018 IEEE 11th International Conference on Cloud Computing (CLOUD), 2018

2016 IEEE 22nd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), 2016

Optional software-based features are increasingly becoming an important cost driver in automotive... more Optional software-based features are increasingly becoming an important cost driver in automotive systems. These include features pertaining to active safety, infotainment, etc. Currently, these optional features are integrated into the vehicles at the factory during assembly. This severely restricts the flexibility of the customer to select and use features on-demand and therefore, the customer will either have to be satisfied with an available set of feature options or pre-order a car with the required features from the manufacturer resulting in considerable delay. In order to increase flexibility and reduce the delay, it is necessary to provide the option to configure the vehicle on-demand at the dealership or remotely. In this paper, we present our vision and challenges involved in developing a platform infrastructure that allows on-demand deployment of automotive safety features and ensures their correct execution.

2021 IEEE 7th World Forum on Internet of Things (WF-IoT), 2021

This paper focuses on designing a low-cost and robust IoT-based TDS measurement system for the sm... more This paper focuses on designing a low-cost and robust IoT-based TDS measurement system for the smart campus. The objective of this low-cost design problem is to find a solution that guarantees precise and uninterrupted output data. The dynamic reading of data, storage capacity, and calibration errors of sensors are the major challenges for IoT-based TDS measurement systems. These challenges are combated in the proposed design using a non-invasive mechanism for data collection, wireless connectivity to the data server, and machine learning calibration of sensor nodes. The TDS data of various water stations located inside the campus is used for the experimental study to develop a regression model for temperature compensation and calibration. The value of TDS sensor voltage variation against temperature is analyzed. The evaluation of the model was performed based on the R2 and the root mean square error. By using 3rd degree polynomial regression, we have obtained an R2 value of 93.96 % and an RMSE of 27.93.

2017 IEEE 20th International Symposium on Real-Time Distributed Computing (ISORC), May 1, 2017

Cyber-physical systems (CSPs) are demanding energy-efficient design not only of hardware (HW), bu... more Cyber-physical systems (CSPs) are demanding energy-efficient design not only of hardware (HW), but also of software (SW). Dynamic Voltage and and Frequency Scaling (DVFS) and Dynamic Power Manage (DPM) are most popular techniques to improve the energy efficiency. However, contemporary complicated HW and SW designs requires more elaborate and sophisticated energy management and efficiency evaluation techniques. This paper is concerned about energy supply planning for real-time scheduling systems (units) of which tasks need to meet deadlines. This paper presents a modelbased compositional energy planning technique that computes a minimal ratio of processor frequency that preserves schedulability of independent and preemptive tasks. The minimal ratio of processor frequency can be used to plan the energy supply of realtime components. Our model-based technique is extensible by refining our model with additional features so that energy management techniques and their energy efficiency can be evaluated by model checking techniques. We exploit the compositional framework for hierarchical scheduling systems and provide a new resource model for the frequency computation. As results, our use-case for avionics software components shows that our new method outperforms the classical real-time calculus (RTC) method, requiring 36.21% less frequency ratio on average for scheduling units under RM than the RTC method. Disciplines

ACM Transactions on Embedded Computing Systems, 2018

Executing multiple applications on a single MPSoC brings the major challenge of satisfying multip... more Executing multiple applications on a single MPSoC brings the major challenge of satisfying multiple quality requirements regarding real-time, energy, and so on. Hybrid application mapping denotes the combination of design-time analysis with run-time application mapping. In this article, we present such a methodology, which comprises a design space exploration coupled with a formal performance analysis. This results in several resource reservation configurations, optimized for multiple objectives, with verified real-time guarantees for each individual application. The Pareto-optimal configurations are handed over to run-time management, which searches for a suitable mapping according to this information. To provide any real-time guarantees, the performance analysis needs to be composable and the influence of the applications on each other has to be bounded. We achieve this either by spatial or a novel temporal isolation for tasks and by exploiting composable networks-on-chip (NoCs). ...

SAE Technical Paper Series, 2016

Microprocessors and Microsystems, 2013

With the rise in state-of-the-art communication modes for vehicles such as vehicle to vehicle (V2... more With the rise in state-of-the-art communication modes for vehicles such as vehicle to vehicle (V2V), vehicle to infrastructure (V2I) and vehicle to cloud (V2C), modern vehicles are increasingly being connected to cloud and fog/edge nodes. These vehicle connectivity modes have enabled the realization of Vehicular Edge Computing (VEC) paradigm, whereby vehicles can leverage fog/edge node resources for storage/computation. In a VEC system, vehicles receive very important and large quantity of data from edge nodes, which is termed as data delivery. In addition, edge nodes can execute some services and send the results back to the vehicle, which is called service delivery. Fast and efficient edge resource allocation for data/service delivery is important in order to serve as many vehicles as possible in the VEC system. However, edge resource allocation is complex with large number of edges and vehicles, while also considering vehicle flow parameters. In this work, we propose Edge-Pairwis...

2007 International Symposium on Signals, Circuits and Systems, 2007

Abstract In this paper, we present area-delay and power-delay characteristics against varying lev... more Abstract In this paper, we present area-delay and power-delay characteristics against varying levels of parallel and pipelined implementations of finite impulse response (FIR) filter in FPGA platform for high throughput applications. From the synthesis results, it has been observed that the parallel systolic architecture (PSA) has a better overall resource utilization based on the area-delay product and power-delay product. The area-delay product of the PSA is 40% lesser than the parallel retimed broadcast architecture (PRBA) ...

2007 International Symposium on Signals, Circuits and Systems, 2007

Abstract Window based spatial domain two dimensional (2-D) image convolution is a widely used alg... more Abstract Window based spatial domain two dimensional (2-D) image convolution is a widely used algorithm in many image processing applications including intrusion detection. Systolic array architectures have been widely used to implement 2-D convolvers so as to exploit ...

2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006

Abstract Two dimensional (2D) image convolution is a typical algorithm executed by window-based s... more Abstract Two dimensional (2D) image convolution is a typical algorithm executed by window-based spatial domain filters, which are in turn used in many applications including intrusion detection. Systolic arrays have been widely used in them by exploiting the hardware ...

We study the impact of video frame drops in buffer-constrained multiprocessor system-on-chip (MPS... more We study the impact of video frame drops in buffer-constrained multiprocessor system-on-chip (MPSoC) platforms. Since on-chip buffer memory occupies a significant amount of silicon area, accurate buffer sizing has attracted a lot of research interest lately. However, all previous work studied this problem with the underlying assumption that no video frame drops can be tolerated. In reality, multimedia applications can often tolerate some frame drops without significantly deteriorating their output quality. Although system simulations can be used to perform video quality driven buffer sizing, they are time consuming. In this paper, we first demonstrate a dual-buffer management scheme to drop only the less significant frames. Based on this scheme, we then propose a formal framework to evaluate the buffer size vs. video quality trade-offs, which in turn will help a system designer to perform quality driven buffer sizing. In particular, we mathematically characterize the maximum numbers...

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors, 2014

ABSTRACT Current mobile devices extensively run video players that are power hungry. Further, hig... more ABSTRACT Current mobile devices extensively run video players that are power hungry. Further, higher power densities as a result of technology scaling results in higher on-chip temperatures. Unlike general purpose computer systems, mobile devices that run on batteries cannot afford to have expensive cooling mechanisms. Therefore, in order to satisfy thermal constraints while running power hungry applications, dynamic thermal management (DTM) techniques have been employed. For multimedia applications, the techniques primarily relied on dynamic voltage and frequency scaling (DVFS) and dynamic power management (DPM) while taking care that maximum video quality is achieved. However, no prior work has exploited frame drops to lower the inserted idle times under predetermined quality constraints. In this work, we propose a DPM framework that utilizes frame drops to dynamically insert low idle times in order to satisfy a peak temperature constraint under a given quality constraint. This also reduces the end-to-end latency. The latencies are further reduced by maintaining lightweight workload histories. For the videos used in our experiments, it was observed that a small reduction in quality of 2 dB (reduction from 32 dB to 30 dB) due to frame drops in motion videos results in a maximum latency reduction of 1.7 sec.

2014 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013

ABSTRACT In this paper, we propose a technique to synthesize a cost-efficient distributed platfor... more ABSTRACT In this paper, we propose a technique to synthesize a cost-efficient distributed platform consisting of multiple Application Specific Instruction Set Processors (multi-ASIPs) running applications with strict timing constraints. Multi-ASIP platform synthesis is a non-trivial task for two reasons. Firstly, we need to know the WCET of tasks in target applications to derive platforms (including synthesized ASIPs) in which the tasks are schedulable. However, the WCET of tasks can be known only after the ASIPs are synthesized. We break this circular dependency by using a probability distribution of the WCET of a task (further referred to as the WCET uncertainty model), which takes into account the underlying microarchitectural configurations for the ASIP implementation. Secondly, the datapath area of the multi-ASIPs synthesized is an important design factor that contributes significantly towards the overall cost of the platform. We propose an area estimation model and a WCET uncertainty model that consider the effect of task datapath similarity. Based on these two models, we support the designer in exploring cost/performance trade-offs during the platform synthesis. We propose an Evolutionary Algorithm-based approach to solve this multiobjective optimization problem. The proposed approach has been evaluated using several benchmarks and it provides a number of multi-ASIP platform solutions exploring the trade-offs in the cost/performance design space.

2021 IEEE 93rd Vehicular Technology Conference (VTC2021-Spring)

With the rise in state-of-the-art communication modes for vehicles such as vehicle to vehicle (V2... more With the rise in state-of-the-art communication modes for vehicles such as vehicle to vehicle (V2V), vehicle to infrastructure (V2I) and vehicle to cloud (V2C), modern vehicles are increasingly being connected to cloud and fog/edge nodes. These vehicle connectivity modes have enabled the realization of Vehicular Edge Computing (VEC) paradigm, whereby vehicles can leverage fog/edge node resources for storage/computation. In a VEC system, vehicles receive very important and large quantity of data from edge nodes, which is termed as data delivery. In addition, edge nodes can execute some services and send the results back to the vehicle, which is called service delivery. Fast and efficient edge resource allocation for data/service delivery is important in order to serve as many vehicles as possible in the VEC system. However, edge resource allocation is complex with large number of edges and vehicles, while also considering vehicle flow parameters. In this work, we propose Edge-Pairwise Optimal Data/Service Delivery (E-PODS), which is a fast and efficient heuristic for data/service delivery. Through experiments with synthetic and real vehicular traces, we demonstrate that E-PODS is considerably faster than the optimal approach, while making resource allocations that are close to optimal in terms of total edge bandwidth cost and number of serviced vehicles.

Reliability and flexibility are among the key required features of a framework used to model a sy... more Reliability and flexibility are among the key required features of a framework used to model a system. Existing approaches to design resource-constrained, soft-real time systems either provide guarantees for output quality or account for loss in the system, but not both. We propose two independent solutions where each modeling technique has both the above mentioned characteristics. We present a probabilistic analytical framework and a statistical model checking approach to design system-on-chips for low-cost multimedia systems. We apply the modeling techniques to size the output buffer in a video decoder. The results shows that, for our stochastic design metric, the analytical framework upper bounds (and relatively accurate) compare to the statistical model checking technique. Also, we observed significant reduction in resource usage (such as output buffer size) with tolerable loss in output quality.

Reliability and flexibility are among the key required features of a framework used to model a sy... more Reliability and flexibility are among the key required features of a framework used to model a system. Existing approaches to design resource-constrained, soft-real time systems either provide guarantees for output quality or account for loss in the system, but not both. We propose two independent solutions where each modeling technique has both the above mentioned characteristics. We present a probabilistic analytical framework and a statistical model checking approach to design system-on-chips for low-cost multimedia systems. We apply the modeling techniques to size the output buffer in a video decoder. The results shows that, for our stochastic design metric, the analytical framework upper bounds (and relatively accurate) compare to the statistical model checking technique. Also, we observed significant reduction in resource usage (such as output buffer size) with tolerable loss in output quality.

2018 IEEE 11th International Conference on Cloud Computing (CLOUD), 2018

2016 IEEE 22nd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), 2016

Optional software-based features are increasingly becoming an important cost driver in automotive... more Optional software-based features are increasingly becoming an important cost driver in automotive systems. These include features pertaining to active safety, infotainment, etc. Currently, these optional features are integrated into the vehicles at the factory during assembly. This severely restricts the flexibility of the customer to select and use features on-demand and therefore, the customer will either have to be satisfied with an available set of feature options or pre-order a car with the required features from the manufacturer resulting in considerable delay. In order to increase flexibility and reduce the delay, it is necessary to provide the option to configure the vehicle on-demand at the dealership or remotely. In this paper, we present our vision and challenges involved in developing a platform infrastructure that allows on-demand deployment of automotive safety features and ensures their correct execution.

2021 IEEE 7th World Forum on Internet of Things (WF-IoT), 2021

This paper focuses on designing a low-cost and robust IoT-based TDS measurement system for the sm... more This paper focuses on designing a low-cost and robust IoT-based TDS measurement system for the smart campus. The objective of this low-cost design problem is to find a solution that guarantees precise and uninterrupted output data. The dynamic reading of data, storage capacity, and calibration errors of sensors are the major challenges for IoT-based TDS measurement systems. These challenges are combated in the proposed design using a non-invasive mechanism for data collection, wireless connectivity to the data server, and machine learning calibration of sensor nodes. The TDS data of various water stations located inside the campus is used for the experimental study to develop a regression model for temperature compensation and calibration. The value of TDS sensor voltage variation against temperature is analyzed. The evaluation of the model was performed based on the R2 and the root mean square error. By using 3rd degree polynomial regression, we have obtained an R2 value of 93.96 % and an RMSE of 27.93.

2017 IEEE 20th International Symposium on Real-Time Distributed Computing (ISORC), May 1, 2017

Cyber-physical systems (CSPs) are demanding energy-efficient design not only of hardware (HW), bu... more Cyber-physical systems (CSPs) are demanding energy-efficient design not only of hardware (HW), but also of software (SW). Dynamic Voltage and and Frequency Scaling (DVFS) and Dynamic Power Manage (DPM) are most popular techniques to improve the energy efficiency. However, contemporary complicated HW and SW designs requires more elaborate and sophisticated energy management and efficiency evaluation techniques. This paper is concerned about energy supply planning for real-time scheduling systems (units) of which tasks need to meet deadlines. This paper presents a modelbased compositional energy planning technique that computes a minimal ratio of processor frequency that preserves schedulability of independent and preemptive tasks. The minimal ratio of processor frequency can be used to plan the energy supply of realtime components. Our model-based technique is extensible by refining our model with additional features so that energy management techniques and their energy efficiency can be evaluated by model checking techniques. We exploit the compositional framework for hierarchical scheduling systems and provide a new resource model for the frequency computation. As results, our use-case for avionics software components shows that our new method outperforms the classical real-time calculus (RTC) method, requiring 36.21% less frequency ratio on average for scheduling units under RM than the RTC method. Disciplines

ACM Transactions on Embedded Computing Systems, 2018

Executing multiple applications on a single MPSoC brings the major challenge of satisfying multip... more Executing multiple applications on a single MPSoC brings the major challenge of satisfying multiple quality requirements regarding real-time, energy, and so on. Hybrid application mapping denotes the combination of design-time analysis with run-time application mapping. In this article, we present such a methodology, which comprises a design space exploration coupled with a formal performance analysis. This results in several resource reservation configurations, optimized for multiple objectives, with verified real-time guarantees for each individual application. The Pareto-optimal configurations are handed over to run-time management, which searches for a suitable mapping according to this information. To provide any real-time guarantees, the performance analysis needs to be composable and the influence of the applications on each other has to be bounded. We achieve this either by spatial or a novel temporal isolation for tasks and by exploiting composable networks-on-chip (NoCs). ...

SAE Technical Paper Series, 2016

Microprocessors and Microsystems, 2013

With the rise in state-of-the-art communication modes for vehicles such as vehicle to vehicle (V2... more With the rise in state-of-the-art communication modes for vehicles such as vehicle to vehicle (V2V), vehicle to infrastructure (V2I) and vehicle to cloud (V2C), modern vehicles are increasingly being connected to cloud and fog/edge nodes. These vehicle connectivity modes have enabled the realization of Vehicular Edge Computing (VEC) paradigm, whereby vehicles can leverage fog/edge node resources for storage/computation. In a VEC system, vehicles receive very important and large quantity of data from edge nodes, which is termed as data delivery. In addition, edge nodes can execute some services and send the results back to the vehicle, which is called service delivery. Fast and efficient edge resource allocation for data/service delivery is important in order to serve as many vehicles as possible in the VEC system. However, edge resource allocation is complex with large number of edges and vehicles, while also considering vehicle flow parameters. In this work, we propose Edge-Pairwis...

2007 International Symposium on Signals, Circuits and Systems, 2007

Abstract In this paper, we present area-delay and power-delay characteristics against varying lev... more Abstract In this paper, we present area-delay and power-delay characteristics against varying levels of parallel and pipelined implementations of finite impulse response (FIR) filter in FPGA platform for high throughput applications. From the synthesis results, it has been observed that the parallel systolic architecture (PSA) has a better overall resource utilization based on the area-delay product and power-delay product. The area-delay product of the PSA is 40% lesser than the parallel retimed broadcast architecture (PRBA) ...

2007 International Symposium on Signals, Circuits and Systems, 2007

Abstract Window based spatial domain two dimensional (2-D) image convolution is a widely used alg... more Abstract Window based spatial domain two dimensional (2-D) image convolution is a widely used algorithm in many image processing applications including intrusion detection. Systolic array architectures have been widely used to implement 2-D convolvers so as to exploit ...

2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006

Abstract Two dimensional (2D) image convolution is a typical algorithm executed by window-based s... more Abstract Two dimensional (2D) image convolution is a typical algorithm executed by window-based spatial domain filters, which are in turn used in many applications including intrusion detection. Systolic arrays have been widely used in them by exploiting the hardware ...

We study the impact of video frame drops in buffer-constrained multiprocessor system-on-chip (MPS... more We study the impact of video frame drops in buffer-constrained multiprocessor system-on-chip (MPSoC) platforms. Since on-chip buffer memory occupies a significant amount of silicon area, accurate buffer sizing has attracted a lot of research interest lately. However, all previous work studied this problem with the underlying assumption that no video frame drops can be tolerated. In reality, multimedia applications can often tolerate some frame drops without significantly deteriorating their output quality. Although system simulations can be used to perform video quality driven buffer sizing, they are time consuming. In this paper, we first demonstrate a dual-buffer management scheme to drop only the less significant frames. Based on this scheme, we then propose a formal framework to evaluate the buffer size vs. video quality trade-offs, which in turn will help a system designer to perform quality driven buffer sizing. In particular, we mathematically characterize the maximum numbers...

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors, 2014

ABSTRACT Current mobile devices extensively run video players that are power hungry. Further, hig... more ABSTRACT Current mobile devices extensively run video players that are power hungry. Further, higher power densities as a result of technology scaling results in higher on-chip temperatures. Unlike general purpose computer systems, mobile devices that run on batteries cannot afford to have expensive cooling mechanisms. Therefore, in order to satisfy thermal constraints while running power hungry applications, dynamic thermal management (DTM) techniques have been employed. For multimedia applications, the techniques primarily relied on dynamic voltage and frequency scaling (DVFS) and dynamic power management (DPM) while taking care that maximum video quality is achieved. However, no prior work has exploited frame drops to lower the inserted idle times under predetermined quality constraints. In this work, we propose a DPM framework that utilizes frame drops to dynamically insert low idle times in order to satisfy a peak temperature constraint under a given quality constraint. This also reduces the end-to-end latency. The latencies are further reduced by maintaining lightweight workload histories. For the videos used in our experiments, it was observed that a small reduction in quality of 2 dB (reduction from 32 dB to 30 dB) due to frame drops in motion videos results in a maximum latency reduction of 1.7 sec.

2014 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013

ABSTRACT In this paper, we propose a technique to synthesize a cost-efficient distributed platfor... more ABSTRACT In this paper, we propose a technique to synthesize a cost-efficient distributed platform consisting of multiple Application Specific Instruction Set Processors (multi-ASIPs) running applications with strict timing constraints. Multi-ASIP platform synthesis is a non-trivial task for two reasons. Firstly, we need to know the WCET of tasks in target applications to derive platforms (including synthesized ASIPs) in which the tasks are schedulable. However, the WCET of tasks can be known only after the ASIPs are synthesized. We break this circular dependency by using a probability distribution of the WCET of a task (further referred to as the WCET uncertainty model), which takes into account the underlying microarchitectural configurations for the ASIP implementation. Secondly, the datapath area of the multi-ASIPs synthesized is an important design factor that contributes significantly towards the overall cost of the platform. We propose an area estimation model and a WCET uncertainty model that consider the effect of task datapath similarity. Based on these two models, we support the designer in exploring cost/performance trade-offs during the platform synthesis. We propose an Evolutionary Algorithm-based approach to solve this multiobjective optimization problem. The proposed approach has been evaluated using several benchmarks and it provides a number of multi-ASIP platform solutions exploring the trade-offs in the cost/performance design space.