Mohamed Ali Belaid | Umm Al-Qura University, Makkah, Saudi Arabia (original) (raw)

Papers by Mohamed Ali Belaid

Recent studies have shown that the aging time effect on power RF LDMOS transistor may modify elec... more Recent studies have shown that the aging time effect on power RF LDMOS transistor may modify electromagnetic emission significantly. It is even rarer to use of RF LDMOS (Radio Frequency Lateral Diffused Metal–Oxide–Semiconductor) devices in a power application. This paper reports on an experiment that prove to elucidate the origins of level changes in the Electro-Magnetic Interference (EMI) in DCDC buck converter. In addition, their influences on the electrical parameters and their relationship with charge trapping at the interface are studied. The experimental results (spectre and waveform parameters), obtained after various thermal aging times are presented and discussed. The experimental results have highlighted that there is an increase in the amplitude of resonances on the interference spectra after aging. The level changes are proportional to the aging time. The charge trapping in gate oxide caused Miller capacity value to decrease (Crss), thereafter in turn a decrease in the level of disturbance.

SN applied sciences, Apr 20, 2020

This paper presents an innovative reliability bench of aging life tests designed to high power RF... more This paper presents an innovative reliability bench of aging life tests designed to high power RF applications for device lifetime under pulse conditions. The temperature effect on the parameters of power RF LDMOS (Radio Frequency Laterally Diffused-Metal-Oxide-Semiconductor) devices is highlighted. Indeed, the acceleration of the degradation mechanisms is related, directly or indirectly, to the temperature variation. The tests carried out on the power amplifier will be "Life-test RF" type (accelerated aging under constant constraints) over a period of 1500 h to quantify the drifts of the parameters measured (mainly P OUT and I DSS) under reliability bench life-test at different temperatures. The parameters of devices have been characterized i.e. static, dynamic and RF before and after testing. This allows us to quantify the degradation, of the shift, of a certain number of electrical quantities (V TH , G M , R DSON , C RSS , etc.). The analysis of the physical results has been presented (simulator 2D ATLAS-SILVACO) to explain and observe the physical review of temperature impacts on power RF LDMOS performance. Finally, initial impacts analysis have been discussed.

The papier study the temperature effects on I-V characteristics of N-channel power RF LDMOS devic... more The papier study the temperature effects on I-V characteristics of N-channel power RF LDMOS devices, and especially of RDS-on resistance; which is a main constraint of LDMOS devices in high temperature operations, that can partially or total change the performances of physical and electrical device. RDS-on has strong temperature dependence. The main parameters electrical relevant to the temperature effects of the device behavior is reported and proven by the basic physical behavior. The analysis of the experimental results is presented and the physical simulations (2D ATLAS-SILVACO) are used to explain and observe the preview of temperature impacts on power RF LDMOS performance. The physical parameters like current lines, concentration, electric field and mobility are taken into consideration follows temperature dependence. Finally, initial impacts analysis is discussed.

Thermal constraints and the variation of high temperature levels are two of the most observed deg... more Thermal constraints and the variation of high temperature levels are two of the most observed degradation mechanisms in power RF electronic devices. In order to evaluate the degradation level, the main indicator may be the measurement of on-state resistance (R$_{DS-on}$), which is systematically associated with the evolution of the internal device structure. This is a study of temperature effects on I-V characteristics of N-channel power RF LDMOS devices, and especially of RDS-on resistance; which is a main constraint of LDMOS devices in high temperature operations, that can partially or total change the performances of physical and electrical device. R$_{DS-on}$ has strong temperature dependence. The main parameters relevant to the temperature effects of the electrical characterization of the device is reported and proven by the basic physical behavior. The analysis of the experimental results is presented and the physical simulations (2D ATLAS–SILVACO) are used to explain and observe the physical preview of temperature impacts on power RF LDMOS performance. The physical parameters like current lines, concentration, electric field and mobility are taken into consideration follows temperature dependence. Finally, initial impacts analysis is discussed.

IET circuits, devices & systems, Aug 31, 2020

This study presents firstly, experimental results through an innovative reliability bench of puls... more This study presents firstly, experimental results through an innovative reliability bench of pulsed RF life test in a radar application for device lifetime under pulse conditions, then the physical clarifications of the failure phenomenon. The results of accelerated aging stress relative to various temperatures (3000 h at 150 and 10°C) are presented. Based on the radio-frequency (RF) behaviour parameters shifts (gain, P out , drain efficiency: DE, and P sat ), the reliability of different tests have been compared. To explain and confirm these effects according to the degradation data, the dominant physical phonemes involved have been studied and the failure modes of the metal-oxide-semiconductor field-effect transistors have been examined and proved with the SILVACO-ATLAS simulator. What supports finding a relationship between the shifts of RF electrical parameters to failure physical phenomena caused by impact ionisation. The behaviour degradation of N-LDMOS is related to interface states generated by hot carriers (traps) and by the electrons that are trapped, which leads to an accumulation of negative charge at the Si/SiO 2 interface. At low temperature, the interface states are created more, due to a maximum impact ionisation rate targeted in the gate edge area. Finally, RF behaviour reliability analysis has been discussed.

... The detail of the lateral electric field distribution of the active silicon layer in channel ... more ... The detail of the lateral electric field distribution of the active silicon layer in channel and drift regions is shown in Fig. 6, using physical simulation software (Silvaco-Atlas, 2D). ... “Comparative analysis of accelerated ageing effects on power RF LDMOS reliability”, ESREF 2005. ...

Microelectronics Reliability, Sep 1, 2013

ABSTRACT The electromagnetic compatibility (EMC) study is an indispensable step in the power syst... more ABSTRACT The electromagnetic compatibility (EMC) study is an indispensable step in the power system development cycle components. In this paper, we present a study on the evolution of conducted (in common and differential mode voltages) and radiated interferences generated by a static converter after various accelerated ageing tests (thermal and electrical) of the power switching RF N-LDMOS devices. Experimental results are presented and analyzed. We notice a clear increase in the amplitude of resonances in the interference spectra after ageing tests.

An analysis of the degradation occurred in RF life-tests of n-type MOSFETs operated from pulsed b... more An analysis of the degradation occurred in RF life-tests of n-type MOSFETs operated from pulsed bench for a radar application in S-band is introduced. The analysis comes accompanied with experimental results, which are used to facilitate optimization of the robustness of Power RF MOSFETs. The recorded S-parameters before and after degradation allows the observation of the corresponding changes in the transmission and reflection features, as well as in the miller capacitance and the transconductance. The physical processes responsible for the observed degradation at different stress conditions are studied by means of ATLAS-SILVACO simulations. These are resulted from the interface state generation (traps), which results in a build up of negative charge at Si/SiO2 interface. More interface states are created due to a located maximum impact ionization rate at the gate edge. This analysis is relevant for power RF MOS devices operating in the RF frequency regime. From our experimental results, hot electron induced RF performance degradation should be taken in to consideration in the design of these devices.

This is a study of thermal effects on performance of N-channel power RF LDMOS devices, under reli... more This is a study of thermal effects on performance of N-channel power RF LDMOS devices, under reliability bench of pulsed RF life test in a radar application from 10° C to 150° C. The behaviour of semiconductor is delicate to temperature variation, especially power RF devices, that can partially or total change the performances of physical and electrical device. The temperature evolution during the operations causes a significant drift in device reliability and a considerable influence on reliability, which leads to failure. The main parameters (threshold voltage Vth, on-state resistance RDS-on, capacity Miller CRSS, Gain, Drain efficiency,) relevant to the temperature effects of the electrical performance of the device is reported and proven by the basic physical behaviour. The analysis of the experimental results are presented. Rarely, the physical simulations 3D ATLAS–SILVACO, are used to prove the mechanisms responsible of thermal impacts on power RF LDMOS performance.

Aeu-international Journal of Electronics and Communications, Mar 1, 2018

This research work presents the design and characterization of planar discrete lens antennas (TA ... more This research work presents the design and characterization of planar discrete lens antennas (TA Transmit-Array antennas) based on a simple tri-layer elementary cell operating in the 10-GHz band. The structure of the proposed elementary cell allows 1-bit and 2-bit phase quantization and easy fabrication with a simple printedcircuit board. The linear/circular polarization can be generated with 1-bit/2-bit configuration. The elementary cell consists of two C-slot loaded patch antennas interconnected by a metalized via hole. The simulation of the elementary cell has been validated by the measurement that confirmed a good accord in terms of return loss (10 dB-bandwidth is equal to 9%) and insertion loss (0.35 dB at 10 GHz). The linearly-polarized transmit-array achieves a maximum directivity of 25.1 dBi and a gain of 22.7 dBi. The 1-dB gain bandwidth is up to 9.6% around 9.8 GHz with 56.3% of radiation efficiency. Beam-steering up to 30°is achieved by tilting the focal source.

HAL (Le Centre pour la Communication Scientifique Directe), Sep 1, 2005

This paper presents the results of comparative reliability study of two accelerated ageing tests ... more This paper presents the results of comparative reliability study of two accelerated ageing tests for thermal stress applied on power RF LDMOS: Thermal Shock Tests (TST, air-air test) and Thermal Cycling Tests (TCT, airair test) under various conditions (with and without DC bias, TST cold and hot, different extremes temperatures T). The performances shift for some critical electrical parameters such as on-state resistance (R ds_on) and feedback capacitance (C rs) have been demonstrated under various tests. To better understand the parameter shift that appear after thermal stress, we used a physical simulation software (Silvaco-Atlas, 2D) to confirm qualitatively degradation phenomena.

Results in Engineering

This paper describes a new methodology to initiate a thermal accelerated aging test, and identify... more This paper describes a new methodology to initiate a thermal accelerated aging test, and identify the key parameters affecting the reliability of a power RF N-LDMOS transistor. The method is based on two aging techniques namely cold and hot thermal shock tests (TST, air-air test), carried out at different junction temperatures varying from −25 °C to +75 °C as well as a deep theoretical analysis. We particularly focus on the thermal chock degradation of three important bond parameters: time, temperature and channel current. The experimental results show that the degradation phenomenon at cold TST is more important than at hot TST. Moreover, we observe an increase in the amplitude of the leakage gate current IGS as well as a shift in the following electric parameters: threshold voltage VTH, transconductance GM, on-state resistance RDSON, feedback capacity CRSS, and S parameters. 3D Silvaco-ATLAS based physical simulations are also carried out, and reveal the effect of the TST on the degradation of the structure zone, which in turn has led to the shift in the values of the electrical parameters. A deep theoretical analysis confirms the observed phenomenon, and shows that the degradation process leads to an increased carrier injection into the developed silicon dioxide layer (SiO2) and/or into the interface state Si/SiO2. Therefore, much more interface states are created due to a located maximum impact ionization rate at the gate.

Microelectronics Reliability

This paper focuses on correlation between the electrical parameter shifts and the failure phenome... more This paper focuses on correlation between the electrical parameter shifts and the failure phenomena that appeared after pulsed RF life tests applied to RF power LDMOS transistor (Radio Frequency Laterally Diffused-Metal-Oxide-Semiconductor). The results of the test bench (radar circuit) are measured in real time. The failure rate is more significant at low temperatures after the aging life test. The electrical performances are shifted, notably, I GS , V TH , G M , R DSON , C RSS , gain, and S-parameter S 21. A 3D physical simulation (SILVACO-TCAD) is used to highlight the phenomena linked to the characteristic's degradation. The impact ionization induces physical degradations in the study of transistors, which are manifested by a variation in their electrical performance. It showed that the located failure zone is due to the device's shifted characteristics, which are deeply correlated with the structure area. The goal of the paper is to prove the failure mechanism through the characteristics evaluation origin, that is started by the carrier generation, because of the impact ionization phenomenon. The demonstration is based on the physical simulations are conducted at RF power NLDMOS. The outcomes show that the mechanism is due to the augmented carrier injection into the advanced silicon dioxide layer (SiO 2) or/ and in the Si/SiO 2 interface state. The consistency between the physical simulations and experimental results emphasizes the theoretical analysis performed in this work.

Case Studies in Thermal Engineering

This paper focuses on exploring the correlation between electrical parameters shift of a power RF... more This paper focuses on exploring the correlation between electrical parameters shift of a power RF N-LDMOS transistor and the failure phenomenon that appeared after the conditioning of the pulsed RF life tests (1500 h). Investigational tests are first carried out in real-time using a test bench circuit dedicated for radar circuits' experimentation. The obtained results show that the degradation at low temperature is more adverse after the RF-life tests. Indeed, the leakage gate current amplitude (IGS) has increased. Moreover, the values of the threshold voltage (VTH), transconductance (GM), on-state resistance (RDSON), feedback capacity (CRSS), gain, drain efficiency (DE), and S-parameter S21 has been shifted from their nominal values. A theoretical analysis of the impact of the ionization effect is thereafter made at the electrical macroscopic scale (static, dynamic, and RF) and physical microscopic quantities (electric field, carrier's concentration, current lines, ionization impact rate, etc.). It showed that the located degradation area is due to transistor's parameters shift, which are deeply related to the structure zone. This degradation mechanism at the parameter evaluation origin, which is activated by the carrier generation due to impact ionization approached is confirmed with numerical simulation (Silvaco-TCAD) carried out at on a power RF N-LDMOS, through the increased carrier injection into the developed silicon dioxide layer (SiO2) and/or into interface state Si/SiO2. The obtained results are consistent with the experimental data which confirms the impact of the ionization effect on the degradation of the transistor's performances

International Transactions on Electrical Energy Systems, 2021

2020 26th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC), 2020

In a metal-oxide-semiconductor (MOS) the leakage current can be a significant contributor to heat... more In a metal-oxide-semiconductor (MOS) the leakage current can be a significant contributor to heat dissipation, resulting in higher power consumption. This paper presents a synthesis of leakage current effects on MOSFET performances, and its relation with charge trapping in the interface, after RF life-tests of operational reliability pulsed bench for radar applications in S-band. It is important to understand the degradation mechanism effects caused by the increase leakage current and by relationship on drifts of electrical parameters such as threshold voltage (Vth), drain-source breakdown voltage (V(BR)DSS) and feedback capacitance (Crss). The tracking of set parameters shows that only Hot Carrier Injection (HCI) phenomenon appears. It is the main cause for device degradation leading to the interface state generation (traps), which results in a build-up of negative charge at Si/SiO2 interface. More interface states are created due to a located maximum impact ionization rate at the gate edge. To understanding the physical mechanisms in device inside, a numerical model (Silvaco-Atlas) was used to confirm degradation phenomena. From experimental results, the problem of leakage current should be taken into consideration in the design process of the power RF MOS devices. And can be used as useful tool to investigate reliability in MOSFET.

IET Circuits, Devices & Systems, 2020

This study presents firstly, experimental results through an innovative reliability bench of puls... more This study presents firstly, experimental results through an innovative reliability bench of pulsed RF life test in a radar application for device lifetime under pulse conditions, then the physical clarifications of the failure phenomenon. The results of accelerated aging stress relative to various temperatures (3000 h at 150 and 10°C) are presented. Based on the radio-frequency (RF) behaviour parameters shifts (gain, P out , drain efficiency: DE, and P sat ), the reliability of different tests have been compared. To explain and confirm these effects according to the degradation data, the dominant physical phonemes involved have been studied and the failure modes of the metal-oxide-semiconductor field-effect transistors have been examined and proved with the SILVACO-ATLAS simulator. What supports finding a relationship between the shifts of RF electrical parameters to failure physical phenomena caused by impact ionisation. The behaviour degradation of N-LDMOS is related to interface states generated by hot carriers (traps) and by the electrons that are trapped, which leads to an accumulation of negative charge at the Si/SiO 2 interface. At low temperature, the interface states are created more, due to a maximum impact ionisation rate targeted in the gate edge area. Finally, RF behaviour reliability analysis has been discussed.

Microelectronics Reliability, 2018

An analysis of the degradation occurred in RF life-tests of n-type MOSFETs operated from pulsed b... more An analysis of the degradation occurred in RF life-tests of n-type MOSFETs operated from pulsed bench for a radar application in S-band is introduced. The analysis comes accompanied with experimental results, which are used to facilitate optimization of the robustness of Power RF MOSFETs. The recorded S-parameters before and after degradation allow the observation of the corresponding changes, in the transmission and reflection features, as well as in the miller capacitance, and the transconductance. The physical processes responsible for the observed degradation at different stress conditions are studied by means of ATLAS-SILVACO simulations. These are resulted from the interface state generation (traps), which results in a build up of negative charge at Si/SiO 2 interface. More interface states are created due to a located maximum impact ionization rate at the gate edge. This analysis is relevant for power RF MOS devices operating in the RF frequency regime. From our experimental results, hot electron induced RF performance degradation should be taken in to consideration in the design of these devices. Recently, the characterization, optimization, and reliability of power RF LDMOS devices have drawn much attention [11,12]. For this purpose, we designed and implemented an innovative reliability bench able to keep track of all RF powers [2], voltages and device base-plate temperatures whose values correspond to stress operating conditions

AEU - International Journal of Electronics and Communications, 2018

This research work presents the design and characterization of planar discrete lens antennas (TA ... more This research work presents the design and characterization of planar discrete lens antennas (TA Transmit-Array antennas) based on a simple tri-layer elementary cell operating in the 10-GHz band. The structure of the proposed elementary cell allows 1-bit and 2-bit phase quantization and easy fabrication with a simple printedcircuit board. The linear/circular polarization can be generated with 1-bit/2-bit configuration. The elementary cell consists of two C-slot loaded patch antennas interconnected by a metalized via hole. The simulation of the elementary cell has been validated by the measurement that confirmed a good accord in terms of return loss (10 dB-bandwidth is equal to 9%) and insertion loss (0.35 dB at 10 GHz). The linearly-polarized transmit-array achieves a maximum directivity of 25.1 dBi and a gain of 22.7 dBi. The 1-dB gain bandwidth is up to 9.6% around 9.8 GHz with 56.3% of radiation efficiency. Beam-steering up to 30°is achieved by tilting the focal source.

Recent studies have shown that the aging time effect on power RF LDMOS transistor may modify elec... more Recent studies have shown that the aging time effect on power RF LDMOS transistor may modify electromagnetic emission significantly. It is even rarer to use of RF LDMOS (Radio Frequency Lateral Diffused Metal–Oxide–Semiconductor) devices in a power application. This paper reports on an experiment that prove to elucidate the origins of level changes in the Electro-Magnetic Interference (EMI) in DCDC buck converter. In addition, their influences on the electrical parameters and their relationship with charge trapping at the interface are studied. The experimental results (spectre and waveform parameters), obtained after various thermal aging times are presented and discussed. The experimental results have highlighted that there is an increase in the amplitude of resonances on the interference spectra after aging. The level changes are proportional to the aging time. The charge trapping in gate oxide caused Miller capacity value to decrease (Crss), thereafter in turn a decrease in the level of disturbance.

SN applied sciences, Apr 20, 2020

This paper presents an innovative reliability bench of aging life tests designed to high power RF... more This paper presents an innovative reliability bench of aging life tests designed to high power RF applications for device lifetime under pulse conditions. The temperature effect on the parameters of power RF LDMOS (Radio Frequency Laterally Diffused-Metal-Oxide-Semiconductor) devices is highlighted. Indeed, the acceleration of the degradation mechanisms is related, directly or indirectly, to the temperature variation. The tests carried out on the power amplifier will be "Life-test RF" type (accelerated aging under constant constraints) over a period of 1500 h to quantify the drifts of the parameters measured (mainly P OUT and I DSS) under reliability bench life-test at different temperatures. The parameters of devices have been characterized i.e. static, dynamic and RF before and after testing. This allows us to quantify the degradation, of the shift, of a certain number of electrical quantities (V TH , G M , R DSON , C RSS , etc.). The analysis of the physical results has been presented (simulator 2D ATLAS-SILVACO) to explain and observe the physical review of temperature impacts on power RF LDMOS performance. Finally, initial impacts analysis have been discussed.

The papier study the temperature effects on I-V characteristics of N-channel power RF LDMOS devic... more The papier study the temperature effects on I-V characteristics of N-channel power RF LDMOS devices, and especially of RDS-on resistance; which is a main constraint of LDMOS devices in high temperature operations, that can partially or total change the performances of physical and electrical device. RDS-on has strong temperature dependence. The main parameters electrical relevant to the temperature effects of the device behavior is reported and proven by the basic physical behavior. The analysis of the experimental results is presented and the physical simulations (2D ATLAS-SILVACO) are used to explain and observe the preview of temperature impacts on power RF LDMOS performance. The physical parameters like current lines, concentration, electric field and mobility are taken into consideration follows temperature dependence. Finally, initial impacts analysis is discussed.

Thermal constraints and the variation of high temperature levels are two of the most observed deg... more Thermal constraints and the variation of high temperature levels are two of the most observed degradation mechanisms in power RF electronic devices. In order to evaluate the degradation level, the main indicator may be the measurement of on-state resistance (R$_{DS-on}$), which is systematically associated with the evolution of the internal device structure. This is a study of temperature effects on I-V characteristics of N-channel power RF LDMOS devices, and especially of RDS-on resistance; which is a main constraint of LDMOS devices in high temperature operations, that can partially or total change the performances of physical and electrical device. R$_{DS-on}$ has strong temperature dependence. The main parameters relevant to the temperature effects of the electrical characterization of the device is reported and proven by the basic physical behavior. The analysis of the experimental results is presented and the physical simulations (2D ATLAS–SILVACO) are used to explain and observe the physical preview of temperature impacts on power RF LDMOS performance. The physical parameters like current lines, concentration, electric field and mobility are taken into consideration follows temperature dependence. Finally, initial impacts analysis is discussed.

IET circuits, devices & systems, Aug 31, 2020

This study presents firstly, experimental results through an innovative reliability bench of puls... more This study presents firstly, experimental results through an innovative reliability bench of pulsed RF life test in a radar application for device lifetime under pulse conditions, then the physical clarifications of the failure phenomenon. The results of accelerated aging stress relative to various temperatures (3000 h at 150 and 10°C) are presented. Based on the radio-frequency (RF) behaviour parameters shifts (gain, P out , drain efficiency: DE, and P sat ), the reliability of different tests have been compared. To explain and confirm these effects according to the degradation data, the dominant physical phonemes involved have been studied and the failure modes of the metal-oxide-semiconductor field-effect transistors have been examined and proved with the SILVACO-ATLAS simulator. What supports finding a relationship between the shifts of RF electrical parameters to failure physical phenomena caused by impact ionisation. The behaviour degradation of N-LDMOS is related to interface states generated by hot carriers (traps) and by the electrons that are trapped, which leads to an accumulation of negative charge at the Si/SiO 2 interface. At low temperature, the interface states are created more, due to a maximum impact ionisation rate targeted in the gate edge area. Finally, RF behaviour reliability analysis has been discussed.

... The detail of the lateral electric field distribution of the active silicon layer in channel ... more ... The detail of the lateral electric field distribution of the active silicon layer in channel and drift regions is shown in Fig. 6, using physical simulation software (Silvaco-Atlas, 2D). ... “Comparative analysis of accelerated ageing effects on power RF LDMOS reliability”, ESREF 2005. ...

Microelectronics Reliability, Sep 1, 2013

ABSTRACT The electromagnetic compatibility (EMC) study is an indispensable step in the power syst... more ABSTRACT The electromagnetic compatibility (EMC) study is an indispensable step in the power system development cycle components. In this paper, we present a study on the evolution of conducted (in common and differential mode voltages) and radiated interferences generated by a static converter after various accelerated ageing tests (thermal and electrical) of the power switching RF N-LDMOS devices. Experimental results are presented and analyzed. We notice a clear increase in the amplitude of resonances in the interference spectra after ageing tests.

An analysis of the degradation occurred in RF life-tests of n-type MOSFETs operated from pulsed b... more An analysis of the degradation occurred in RF life-tests of n-type MOSFETs operated from pulsed bench for a radar application in S-band is introduced. The analysis comes accompanied with experimental results, which are used to facilitate optimization of the robustness of Power RF MOSFETs. The recorded S-parameters before and after degradation allows the observation of the corresponding changes in the transmission and reflection features, as well as in the miller capacitance and the transconductance. The physical processes responsible for the observed degradation at different stress conditions are studied by means of ATLAS-SILVACO simulations. These are resulted from the interface state generation (traps), which results in a build up of negative charge at Si/SiO2 interface. More interface states are created due to a located maximum impact ionization rate at the gate edge. This analysis is relevant for power RF MOS devices operating in the RF frequency regime. From our experimental results, hot electron induced RF performance degradation should be taken in to consideration in the design of these devices.

This is a study of thermal effects on performance of N-channel power RF LDMOS devices, under reli... more This is a study of thermal effects on performance of N-channel power RF LDMOS devices, under reliability bench of pulsed RF life test in a radar application from 10° C to 150° C. The behaviour of semiconductor is delicate to temperature variation, especially power RF devices, that can partially or total change the performances of physical and electrical device. The temperature evolution during the operations causes a significant drift in device reliability and a considerable influence on reliability, which leads to failure. The main parameters (threshold voltage Vth, on-state resistance RDS-on, capacity Miller CRSS, Gain, Drain efficiency,) relevant to the temperature effects of the electrical performance of the device is reported and proven by the basic physical behaviour. The analysis of the experimental results are presented. Rarely, the physical simulations 3D ATLAS–SILVACO, are used to prove the mechanisms responsible of thermal impacts on power RF LDMOS performance.

Aeu-international Journal of Electronics and Communications, Mar 1, 2018

This research work presents the design and characterization of planar discrete lens antennas (TA ... more This research work presents the design and characterization of planar discrete lens antennas (TA Transmit-Array antennas) based on a simple tri-layer elementary cell operating in the 10-GHz band. The structure of the proposed elementary cell allows 1-bit and 2-bit phase quantization and easy fabrication with a simple printedcircuit board. The linear/circular polarization can be generated with 1-bit/2-bit configuration. The elementary cell consists of two C-slot loaded patch antennas interconnected by a metalized via hole. The simulation of the elementary cell has been validated by the measurement that confirmed a good accord in terms of return loss (10 dB-bandwidth is equal to 9%) and insertion loss (0.35 dB at 10 GHz). The linearly-polarized transmit-array achieves a maximum directivity of 25.1 dBi and a gain of 22.7 dBi. The 1-dB gain bandwidth is up to 9.6% around 9.8 GHz with 56.3% of radiation efficiency. Beam-steering up to 30°is achieved by tilting the focal source.

HAL (Le Centre pour la Communication Scientifique Directe), Sep 1, 2005

This paper presents the results of comparative reliability study of two accelerated ageing tests ... more This paper presents the results of comparative reliability study of two accelerated ageing tests for thermal stress applied on power RF LDMOS: Thermal Shock Tests (TST, air-air test) and Thermal Cycling Tests (TCT, airair test) under various conditions (with and without DC bias, TST cold and hot, different extremes temperatures T). The performances shift for some critical electrical parameters such as on-state resistance (R ds_on) and feedback capacitance (C rs) have been demonstrated under various tests. To better understand the parameter shift that appear after thermal stress, we used a physical simulation software (Silvaco-Atlas, 2D) to confirm qualitatively degradation phenomena.

Results in Engineering

This paper describes a new methodology to initiate a thermal accelerated aging test, and identify... more This paper describes a new methodology to initiate a thermal accelerated aging test, and identify the key parameters affecting the reliability of a power RF N-LDMOS transistor. The method is based on two aging techniques namely cold and hot thermal shock tests (TST, air-air test), carried out at different junction temperatures varying from −25 °C to +75 °C as well as a deep theoretical analysis. We particularly focus on the thermal chock degradation of three important bond parameters: time, temperature and channel current. The experimental results show that the degradation phenomenon at cold TST is more important than at hot TST. Moreover, we observe an increase in the amplitude of the leakage gate current IGS as well as a shift in the following electric parameters: threshold voltage VTH, transconductance GM, on-state resistance RDSON, feedback capacity CRSS, and S parameters. 3D Silvaco-ATLAS based physical simulations are also carried out, and reveal the effect of the TST on the degradation of the structure zone, which in turn has led to the shift in the values of the electrical parameters. A deep theoretical analysis confirms the observed phenomenon, and shows that the degradation process leads to an increased carrier injection into the developed silicon dioxide layer (SiO2) and/or into the interface state Si/SiO2. Therefore, much more interface states are created due to a located maximum impact ionization rate at the gate.

Microelectronics Reliability

This paper focuses on correlation between the electrical parameter shifts and the failure phenome... more This paper focuses on correlation between the electrical parameter shifts and the failure phenomena that appeared after pulsed RF life tests applied to RF power LDMOS transistor (Radio Frequency Laterally Diffused-Metal-Oxide-Semiconductor). The results of the test bench (radar circuit) are measured in real time. The failure rate is more significant at low temperatures after the aging life test. The electrical performances are shifted, notably, I GS , V TH , G M , R DSON , C RSS , gain, and S-parameter S 21. A 3D physical simulation (SILVACO-TCAD) is used to highlight the phenomena linked to the characteristic's degradation. The impact ionization induces physical degradations in the study of transistors, which are manifested by a variation in their electrical performance. It showed that the located failure zone is due to the device's shifted characteristics, which are deeply correlated with the structure area. The goal of the paper is to prove the failure mechanism through the characteristics evaluation origin, that is started by the carrier generation, because of the impact ionization phenomenon. The demonstration is based on the physical simulations are conducted at RF power NLDMOS. The outcomes show that the mechanism is due to the augmented carrier injection into the advanced silicon dioxide layer (SiO 2) or/ and in the Si/SiO 2 interface state. The consistency between the physical simulations and experimental results emphasizes the theoretical analysis performed in this work.

Case Studies in Thermal Engineering

This paper focuses on exploring the correlation between electrical parameters shift of a power RF... more This paper focuses on exploring the correlation between electrical parameters shift of a power RF N-LDMOS transistor and the failure phenomenon that appeared after the conditioning of the pulsed RF life tests (1500 h). Investigational tests are first carried out in real-time using a test bench circuit dedicated for radar circuits' experimentation. The obtained results show that the degradation at low temperature is more adverse after the RF-life tests. Indeed, the leakage gate current amplitude (IGS) has increased. Moreover, the values of the threshold voltage (VTH), transconductance (GM), on-state resistance (RDSON), feedback capacity (CRSS), gain, drain efficiency (DE), and S-parameter S21 has been shifted from their nominal values. A theoretical analysis of the impact of the ionization effect is thereafter made at the electrical macroscopic scale (static, dynamic, and RF) and physical microscopic quantities (electric field, carrier's concentration, current lines, ionization impact rate, etc.). It showed that the located degradation area is due to transistor's parameters shift, which are deeply related to the structure zone. This degradation mechanism at the parameter evaluation origin, which is activated by the carrier generation due to impact ionization approached is confirmed with numerical simulation (Silvaco-TCAD) carried out at on a power RF N-LDMOS, through the increased carrier injection into the developed silicon dioxide layer (SiO2) and/or into interface state Si/SiO2. The obtained results are consistent with the experimental data which confirms the impact of the ionization effect on the degradation of the transistor's performances

International Transactions on Electrical Energy Systems, 2021

2020 26th International Workshop on Thermal Investigations of ICs and Systems (THERMINIC), 2020

In a metal-oxide-semiconductor (MOS) the leakage current can be a significant contributor to heat... more In a metal-oxide-semiconductor (MOS) the leakage current can be a significant contributor to heat dissipation, resulting in higher power consumption. This paper presents a synthesis of leakage current effects on MOSFET performances, and its relation with charge trapping in the interface, after RF life-tests of operational reliability pulsed bench for radar applications in S-band. It is important to understand the degradation mechanism effects caused by the increase leakage current and by relationship on drifts of electrical parameters such as threshold voltage (Vth), drain-source breakdown voltage (V(BR)DSS) and feedback capacitance (Crss). The tracking of set parameters shows that only Hot Carrier Injection (HCI) phenomenon appears. It is the main cause for device degradation leading to the interface state generation (traps), which results in a build-up of negative charge at Si/SiO2 interface. More interface states are created due to a located maximum impact ionization rate at the gate edge. To understanding the physical mechanisms in device inside, a numerical model (Silvaco-Atlas) was used to confirm degradation phenomena. From experimental results, the problem of leakage current should be taken into consideration in the design process of the power RF MOS devices. And can be used as useful tool to investigate reliability in MOSFET.

IET Circuits, Devices & Systems, 2020

This study presents firstly, experimental results through an innovative reliability bench of puls... more This study presents firstly, experimental results through an innovative reliability bench of pulsed RF life test in a radar application for device lifetime under pulse conditions, then the physical clarifications of the failure phenomenon. The results of accelerated aging stress relative to various temperatures (3000 h at 150 and 10°C) are presented. Based on the radio-frequency (RF) behaviour parameters shifts (gain, P out , drain efficiency: DE, and P sat ), the reliability of different tests have been compared. To explain and confirm these effects according to the degradation data, the dominant physical phonemes involved have been studied and the failure modes of the metal-oxide-semiconductor field-effect transistors have been examined and proved with the SILVACO-ATLAS simulator. What supports finding a relationship between the shifts of RF electrical parameters to failure physical phenomena caused by impact ionisation. The behaviour degradation of N-LDMOS is related to interface states generated by hot carriers (traps) and by the electrons that are trapped, which leads to an accumulation of negative charge at the Si/SiO 2 interface. At low temperature, the interface states are created more, due to a maximum impact ionisation rate targeted in the gate edge area. Finally, RF behaviour reliability analysis has been discussed.

Microelectronics Reliability, 2018

An analysis of the degradation occurred in RF life-tests of n-type MOSFETs operated from pulsed b... more An analysis of the degradation occurred in RF life-tests of n-type MOSFETs operated from pulsed bench for a radar application in S-band is introduced. The analysis comes accompanied with experimental results, which are used to facilitate optimization of the robustness of Power RF MOSFETs. The recorded S-parameters before and after degradation allow the observation of the corresponding changes, in the transmission and reflection features, as well as in the miller capacitance, and the transconductance. The physical processes responsible for the observed degradation at different stress conditions are studied by means of ATLAS-SILVACO simulations. These are resulted from the interface state generation (traps), which results in a build up of negative charge at Si/SiO 2 interface. More interface states are created due to a located maximum impact ionization rate at the gate edge. This analysis is relevant for power RF MOS devices operating in the RF frequency regime. From our experimental results, hot electron induced RF performance degradation should be taken in to consideration in the design of these devices. Recently, the characterization, optimization, and reliability of power RF LDMOS devices have drawn much attention [11,12]. For this purpose, we designed and implemented an innovative reliability bench able to keep track of all RF powers [2], voltages and device base-plate temperatures whose values correspond to stress operating conditions

AEU - International Journal of Electronics and Communications, 2018

This research work presents the design and characterization of planar discrete lens antennas (TA ... more This research work presents the design and characterization of planar discrete lens antennas (TA Transmit-Array antennas) based on a simple tri-layer elementary cell operating in the 10-GHz band. The structure of the proposed elementary cell allows 1-bit and 2-bit phase quantization and easy fabrication with a simple printedcircuit board. The linear/circular polarization can be generated with 1-bit/2-bit configuration. The elementary cell consists of two C-slot loaded patch antennas interconnected by a metalized via hole. The simulation of the elementary cell has been validated by the measurement that confirmed a good accord in terms of return loss (10 dB-bandwidth is equal to 9%) and insertion loss (0.35 dB at 10 GHz). The linearly-polarized transmit-array achieves a maximum directivity of 25.1 dBi and a gain of 22.7 dBi. The 1-dB gain bandwidth is up to 9.6% around 9.8 GHz with 56.3% of radiation efficiency. Beam-steering up to 30°is achieved by tilting the focal source.