Enrique Canto | Universitat Rovira i Virgili (original) (raw)
Papers by Enrique Canto
Ieee Transactions on Circuits and Systems Ii Express Briefs, 2010
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Itssa, 2006
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Lecture Notes in Computer Science, 1999
Most partitioning algorithms have been developed for conventional programmable logic (especially ... more Most partitioning algorithms have been developed for conventional programmable logic (especially FPGAs), being their main goal the minimisation of the signals constituting the interface (cutsize) between partitions, while balancing partition sizes. New families of dynamic reconfigurable programmable logic (DRPL) offer new possibilities to improve functional density of circuits, but traditional partitioning techniques are not able to exploit the novel features offered by these devices. A new family of partitioning techniques for DRPL should be developed, being its main goal the maximisation of the functional density on balanced partition sizes. This paper presents a new partitioning algorithm based on a temporal separation of the system functionality. As our experimental results will show, the algorithm is able to benefit from the dynamic reconfiguration properties of FPGA devices.
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This paper will describe a systematic method to map synchronous digital systems into Dynamically ... more This paper will describe a systematic method to map synchronous digital systems into Dynamically Reconfigurable Logic, as the FIPSOC device. The method is based on a temporal bipartitioning technique able to separate the functionality of a static implementation in two temporal independence hardware contexts. As the experimental results show, the method capable of improving the functional density of the dynamic implementation with respect to the static one.
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Resumen La computación reconfigurable tiende, cada vez más, a fusionarse con el codiseño hardware... more Resumen La computación reconfigurable tiende, cada vez más, a fusionarse con el codiseño hardware-software (HW-SW) en el ámbito del desarrollo de aplicaciones embebidas que exigen alta complejidad de procesado, tiempo real y bajo coste. Ambas técnicas de diseño están presentes en la programación de un dispositivo system-on-chip (SoC), el cual combina aspectos SW a través de un microcontrolador (MCU) de propósito general y aspectos de HW flexible mediante un dispositivo lógico FPGA reconfigurable. Este trabajo aborda la implementación de un sistema automático de reconocimiento biométrico de huella dactilar fundamentado en estas dos técnicas de diseño. Se pretende alcanzar una eficiente arquitectura HW-SW que se adapte a la aplicación con un correcto balance entre área (coste) y tiempo (prestaciones).
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Resumen. En este trabajo se presenta la experiencia didáctica desarrollada por los profesores de ... more Resumen. En este trabajo se presenta la experiencia didáctica desarrollada por los profesores de la Universidad Politécnica de Cataluña y la Universidad Rovira i Virgili con relación a los dispositivos FPGA (Field Programmable Gate Array) y su actual aplicación tecnológica. En este sentido se expone un conjunto de experiencias prácti-cas que permiten al estudiante profundizar en el diseño del sistemas de instrumenta-ción y control basados en dispositivos FPGA's. Las experiencias presentadas forman parte del contenido de la asignatura "Sistemas Digitales de Instrumentación y Con-trol" que se oferta actualmente como asignatura optativa en la Escuela Politécnica Superior de Ingeniería de Vilanova y la Geltrú (UPC).
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El presente artículo muestra la implementación de una unidad en coma flotante (FPU) que actúa com... more El presente artículo muestra la implementación de una unidad en coma flotante (FPU) que actúa como coprocesador dentro de un sistema auto-reconfigurable dinámicamente. La FPU tiene capacidad para resolver operaciones básicas como la suma, la resta, el producto, el cociente, la raíz cuadrada, la inversa y el cuadrado. Además, dispone de un registro en el que se almacena el último resultado obtenido con la intención de utilizarlo como operador en el siguiente cálculo, de modo que se reducen los accesos a los buses de comunicación en la resolución de las operaciones matemáticas. El diseño emplea Microblaze como microprocesador del sistema y su implementación se ha realizado sobre una FPGA Spartan 3 de bajo coste. El artículo muestra resultados experimentales en relación al área total ocupada, así como los tiempos de ejecución obtenidos con un ejemplo particular basado en un algoritmo de CORDIC resuelto en coma flotante. Peer Reviewed Postprint (author’s final draft)
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Resumen Este artículo presenta un procedimiento simple para la obtención de la clave criptográfic... more Resumen Este artículo presenta un procedimiento simple para la obtención de la clave criptográfica del algoritmo AES ejecutado sobre MicroBlaze. La clave se obtiene analizando la correlación estadística que existe entre ésta y el consumo del dispositivo hardware que ejecuta el propio algoritmo. El trabajo también muestra como las contramedidas clásicas de enmascarado del texto plano son únicamente eficientes frente ataques de primer orden. Los resultados experimentales muestran diferentes ataques realizados sobre varios bloques del algoritmo, y concluyen que es posible obtener la clave criptográfica tomando un número de trazas de corriente inferior a 40.
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Proceedings of the First NASA/DoD Workshop on Evolvable Hardware, 1999
In this paper we shall address the physical implementation of self-repairing and evolvable hardwa... more In this paper we shall address the physical implementation of self-repairing and evolvable hardware strategies. These alternatives will be enabled by the specific dynamic reconfiguration capabilities included in a new family of FPGA devices, called FIPSOC (Field programmable System On a Chip). The main features of these devices are given by the integration on a single chip of a dynamically
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Lecture Notes in Computer Science, 1999
In this paper we address the problems posed when Artificial Neural Networks models are implemente... more In this paper we address the problems posed when Artificial Neural Networks models are implemented in programmable digital hardware. Within this context, we shall especially emphasise the realisation of the arithmetic operators required by these models, since it constitutes the main constraint (due to the required amount of resources) found when they are to be translated into physical hardware. The
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Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 2000
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Lecture Notes in Computer Science, 1998
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1999 7th IEEE International Conference on Emerging Technologies and Factory Automation. Proceedings ETFA '99 (Cat. No.99TH8467), 1999
FIPSOC (field programmable system on chip) is a novel device shown to be suitable for rapid proto... more FIPSOC (field programmable system on chip) is a novel device shown to be suitable for rapid prototyping of electronic systems. After a description of its architecture and associated development tools, its distinguishing features are highlighted. In particular, integration of a microprocessor, programmable logic and configurable analog channels in the same chip provides a monolithic platform with capability to prototype complete
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Lecture Notes in Computer Science, 2000
ABSTRACT This paper will explain a systematic technique for the implementation of a synchronous c... more ABSTRACT This paper will explain a systematic technique for the implementation of a synchronous circuit into the DRFPGA (dynamic reconfigurable FPGA) included in the FIPSOC devices, taking advantage of their properties of dynamic reconfiguration. The circuit to be implemented is partitioned using a set of temporal bipartitioning rules, and each partition is mapped on a separated context, sharing both contexts the same hardware resources. The time-multiplexed execution of both contexts constitutes a virtual circuit.
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Architektur von Rechensystemen, 2006
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Journal of Real-time Image Processing, 2000
This work aims to pave the way for an efficient open system architecture applied to embedded elec... more This work aims to pave the way for an efficient open system architecture applied to embedded electronic applications to manage the processing of computationally complex algorithms at real-time and low-cost. The target is to define a standard architecture able to enhance the performance-cost trade-off delivered by other alternatives nowadays in the market like general-purpose multi-core processors. Our approach, sustained by
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Lecture Notes in Computer Science, 2004
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Proceedings of the IEEE International Symposium on Industrial Electronics, 2005. ISIE 2005., 2005
Nature has provided human beings unique and different each one in relation to the others; even &a... more Nature has provided human beings unique and different each one in relation to the others; even 'identical' twins have infinite differences between them. Every individual has his own biological characteristics that allow him to be distinguished from the rest of the humanity. In recent years, biometrics and computer technology have joined together in order to improve the security in everyday
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2007 International Conference on Field Programmable Logic and Applications, 2007
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Ieee Transactions on Circuits and Systems Ii Express Briefs, 2010
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Itssa, 2006
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Bookmarks Related papers MentionsView impact
Lecture Notes in Computer Science, 1999
Most partitioning algorithms have been developed for conventional programmable logic (especially ... more Most partitioning algorithms have been developed for conventional programmable logic (especially FPGAs), being their main goal the minimisation of the signals constituting the interface (cutsize) between partitions, while balancing partition sizes. New families of dynamic reconfigurable programmable logic (DRPL) offer new possibilities to improve functional density of circuits, but traditional partitioning techniques are not able to exploit the novel features offered by these devices. A new family of partitioning techniques for DRPL should be developed, being its main goal the maximisation of the functional density on balanced partition sizes. This paper presents a new partitioning algorithm based on a temporal separation of the system functionality. As our experimental results will show, the algorithm is able to benefit from the dynamic reconfiguration properties of FPGA devices.
Bookmarks Related papers MentionsView impact
This paper will describe a systematic method to map synchronous digital systems into Dynamically ... more This paper will describe a systematic method to map synchronous digital systems into Dynamically Reconfigurable Logic, as the FIPSOC device. The method is based on a temporal bipartitioning technique able to separate the functionality of a static implementation in two temporal independence hardware contexts. As the experimental results show, the method capable of improving the functional density of the dynamic implementation with respect to the static one.
Bookmarks Related papers MentionsView impact
Resumen La computación reconfigurable tiende, cada vez más, a fusionarse con el codiseño hardware... more Resumen La computación reconfigurable tiende, cada vez más, a fusionarse con el codiseño hardware-software (HW-SW) en el ámbito del desarrollo de aplicaciones embebidas que exigen alta complejidad de procesado, tiempo real y bajo coste. Ambas técnicas de diseño están presentes en la programación de un dispositivo system-on-chip (SoC), el cual combina aspectos SW a través de un microcontrolador (MCU) de propósito general y aspectos de HW flexible mediante un dispositivo lógico FPGA reconfigurable. Este trabajo aborda la implementación de un sistema automático de reconocimiento biométrico de huella dactilar fundamentado en estas dos técnicas de diseño. Se pretende alcanzar una eficiente arquitectura HW-SW que se adapte a la aplicación con un correcto balance entre área (coste) y tiempo (prestaciones).
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Resumen. En este trabajo se presenta la experiencia didáctica desarrollada por los profesores de ... more Resumen. En este trabajo se presenta la experiencia didáctica desarrollada por los profesores de la Universidad Politécnica de Cataluña y la Universidad Rovira i Virgili con relación a los dispositivos FPGA (Field Programmable Gate Array) y su actual aplicación tecnológica. En este sentido se expone un conjunto de experiencias prácti-cas que permiten al estudiante profundizar en el diseño del sistemas de instrumenta-ción y control basados en dispositivos FPGA's. Las experiencias presentadas forman parte del contenido de la asignatura "Sistemas Digitales de Instrumentación y Con-trol" que se oferta actualmente como asignatura optativa en la Escuela Politécnica Superior de Ingeniería de Vilanova y la Geltrú (UPC).
Bookmarks Related papers MentionsView impact
El presente artículo muestra la implementación de una unidad en coma flotante (FPU) que actúa com... more El presente artículo muestra la implementación de una unidad en coma flotante (FPU) que actúa como coprocesador dentro de un sistema auto-reconfigurable dinámicamente. La FPU tiene capacidad para resolver operaciones básicas como la suma, la resta, el producto, el cociente, la raíz cuadrada, la inversa y el cuadrado. Además, dispone de un registro en el que se almacena el último resultado obtenido con la intención de utilizarlo como operador en el siguiente cálculo, de modo que se reducen los accesos a los buses de comunicación en la resolución de las operaciones matemáticas. El diseño emplea Microblaze como microprocesador del sistema y su implementación se ha realizado sobre una FPGA Spartan 3 de bajo coste. El artículo muestra resultados experimentales en relación al área total ocupada, así como los tiempos de ejecución obtenidos con un ejemplo particular basado en un algoritmo de CORDIC resuelto en coma flotante. Peer Reviewed Postprint (author’s final draft)
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Resumen Este artículo presenta un procedimiento simple para la obtención de la clave criptográfic... more Resumen Este artículo presenta un procedimiento simple para la obtención de la clave criptográfica del algoritmo AES ejecutado sobre MicroBlaze. La clave se obtiene analizando la correlación estadística que existe entre ésta y el consumo del dispositivo hardware que ejecuta el propio algoritmo. El trabajo también muestra como las contramedidas clásicas de enmascarado del texto plano son únicamente eficientes frente ataques de primer orden. Los resultados experimentales muestran diferentes ataques realizados sobre varios bloques del algoritmo, y concluyen que es posible obtener la clave criptográfica tomando un número de trazas de corriente inferior a 40.
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Proceedings of the First NASA/DoD Workshop on Evolvable Hardware, 1999
In this paper we shall address the physical implementation of self-repairing and evolvable hardwa... more In this paper we shall address the physical implementation of self-repairing and evolvable hardware strategies. These alternatives will be enabled by the specific dynamic reconfiguration capabilities included in a new family of FPGA devices, called FIPSOC (Field programmable System On a Chip). The main features of these devices are given by the integration on a single chip of a dynamically
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Lecture Notes in Computer Science, 1999
In this paper we address the problems posed when Artificial Neural Networks models are implemente... more In this paper we address the problems posed when Artificial Neural Networks models are implemented in programmable digital hardware. Within this context, we shall especially emphasise the realisation of the arithmetic operators required by these models, since it constitutes the main constraint (due to the required amount of resources) found when they are to be translated into physical hardware. The
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Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, 2000
Bookmarks Related papers MentionsView impact
Lecture Notes in Computer Science, 1998
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1999 7th IEEE International Conference on Emerging Technologies and Factory Automation. Proceedings ETFA '99 (Cat. No.99TH8467), 1999
FIPSOC (field programmable system on chip) is a novel device shown to be suitable for rapid proto... more FIPSOC (field programmable system on chip) is a novel device shown to be suitable for rapid prototyping of electronic systems. After a description of its architecture and associated development tools, its distinguishing features are highlighted. In particular, integration of a microprocessor, programmable logic and configurable analog channels in the same chip provides a monolithic platform with capability to prototype complete
Bookmarks Related papers MentionsView impact
Lecture Notes in Computer Science, 2000
ABSTRACT This paper will explain a systematic technique for the implementation of a synchronous c... more ABSTRACT This paper will explain a systematic technique for the implementation of a synchronous circuit into the DRFPGA (dynamic reconfigurable FPGA) included in the FIPSOC devices, taking advantage of their properties of dynamic reconfiguration. The circuit to be implemented is partitioned using a set of temporal bipartitioning rules, and each partition is mapped on a separated context, sharing both contexts the same hardware resources. The time-multiplexed execution of both contexts constitutes a virtual circuit.
Bookmarks Related papers MentionsView impact
Architektur von Rechensystemen, 2006
Bookmarks Related papers MentionsView impact
Journal of Real-time Image Processing, 2000
This work aims to pave the way for an efficient open system architecture applied to embedded elec... more This work aims to pave the way for an efficient open system architecture applied to embedded electronic applications to manage the processing of computationally complex algorithms at real-time and low-cost. The target is to define a standard architecture able to enhance the performance-cost trade-off delivered by other alternatives nowadays in the market like general-purpose multi-core processors. Our approach, sustained by
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Lecture Notes in Computer Science, 2004
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Proceedings of the IEEE International Symposium on Industrial Electronics, 2005. ISIE 2005., 2005
Nature has provided human beings unique and different each one in relation to the others; even &a... more Nature has provided human beings unique and different each one in relation to the others; even 'identical' twins have infinite differences between them. Every individual has his own biological characteristics that allow him to be distinguished from the rest of the humanity. In recent years, biometrics and computer technology have joined together in order to improve the security in everyday
Bookmarks Related papers MentionsView impact
2007 International Conference on Field Programmable Logic and Applications, 2007
Bookmarks Related papers MentionsView impact