Poras Balsara | University of Texas at Dallas (original) (raw)

Papers by Poras Balsara

Research paper thumbnail of Tutorial on interconnect modeling, signal integrity and reliability verification in deep sub-micron digital designs

Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454)

ABSTRACT Not Available

Research paper thumbnail of LAPLUS: An Efficient, Effective and Stable Switch Algorithm for Flow Control of the Available Bit Rate ATM Service

Proceedings - IEEE INFOCOM

Research paper thumbnail of Mismatch considerations in an RF-DAC design for a digital polar EDGE transmitter

2011 IEEE International Symposium on Radio-Frequency Integration Technology, 2011

ABSTRACT We present a systematic approach for the design and analysis of a high-resolution RF-DAC... more ABSTRACT We present a systematic approach for the design and analysis of a high-resolution RF-DAC. The RF-DAC is implemented in 65 nm CMOS as an integral part of a digital polar EDGE transmitter based on the Digital-RF-Processor (DRP™). It combines the functionality of a traditional baseband DAC and a mixer. This paper addresses the issue of a transistor mismatch, which has become a key design challenge at fine geometry process nodes. A method is presented to analyze the mismatch, quantify it and relate it to the system specifications. The presented techniques are used in a commercial GSM/EDGE SoC radio, in which the transmitter's wideband noise (WBN) performance significantly exceeds the EDGE specifications with more than 6 dB margin at 20 MHz offset from the carrier frequency.

Research paper thumbnail of Energy optimization of multilevel cache architectures for RISC and CISC processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1998

Abstract—In this paper, we present the characterization and design of energy-efficient, on-chip c... more Abstract—In this paper, we present the characterization and design of energy-efficient, on-chip cache memories. The charac-terization of power dissipation in on-chip cache memories reveals that the memory peripheral interface circuits and bit array dissipate comparable power. To ...

Research paper thumbnail of 1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS

IEEE Transactions on Circuits and Systems II: Express Briefs, 2006

Abstract—We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm dig... more Abstract—We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile ...

Research paper thumbnail of Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2003

A novel digitally controlled oscillator (DCO)-based architecture for frequency synthesis in wirel... more A novel digitally controlled oscillator (DCO)-based architecture for frequency synthesis in wireless RF applications is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed 61 dithering. Other imperfections of analog circuits are compensated through digital means. The presented ideas enable the employment of fully-digital frequency synthesizers using sophisticated signal processing algorithms, realized in the most advanced deep-submicrometer digital CMOS processes which allow almost no analog extensions. They also promote costeffective integration with the digital back-end onto a single silicon die. The demonstrator test chip has been fabricated in a digital 0.13-m CMOS process together with a DSP, which acts as a digital baseband processor with a large number of digital gates in order to investigate noise coupling. The phase noise is 112 dBc/Hz at 500-kHz offset. The close-in spurious tones are below 62 dBc, while the far-out spurs are below 80 dBc. The presented ideas have been incorporated in a commercial Bluetooth transceiver.

Research paper thumbnail of All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

IEEE Journal of Solid-State Circuits, 2004

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS proc... more We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm 2 and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

Research paper thumbnail of A first digitally-controlled oscillator in a deep-submicron CMOS process for multi-GHz wireless applications

IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003

Abstract A novel digitally-controlled oscillator (DCO) architecture for multi-GHz RF applications... more Abstract A novel digitally-controlled oscillator (DCO) architecture for multi-GHz RF applications is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed ...

Research paper thumbnail of Passivity-Based Control for Direct Voltage Regulation for Boost DC-DC Converter

Research paper thumbnail of Digit Serial Multipliers

Journal of Parallel and Distributed Computing, Feb 1, 1991

... 11, 1S61oZ ( 1991) Digit Serial Multipliers PORAS T. BALSARA Erik Jonsson School of Engineeri... more ... 11, 1S61oZ ( 1991) Digit Serial Multipliers PORAS T. BALSARA Erik Jonsson School of Engineering Computer Science, The University of Texas at Dallas, PO Box 830688, MP33, Richardson, Texas 75083 AND ROBERT M. OWENS AND MARY JANE IRWIN Department of ...

Research paper thumbnail of Analog Input Output Linearization Control

Research paper thumbnail of VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition

Proceedings of the 20th International Conference on Vlsi Design Held Jointly With 6th International Conference Embedded Systems, 2007

Matrix inversion and triangularization problems are common to a wide variety of communication sys... more Matrix inversion and triangularization problems are common to a wide variety of communication systems, signal processing applications and solution of a set of linear equations. Matrix inversion is a computationally intensive process and its hardware implementation based on fixed-point (FP) arithmetic is a challenging problem. This paper proposes a fully parallel VLSI architecture under fixed-precision for the inverse computation of

Research paper thumbnail of 完全ディジタルPLL回路の設計 : ディープ・サブミクロンCMOSプロセスで実現する

Research paper thumbnail of QMOS digital logic circuits

Research paper thumbnail of Characterization and design of a low-power, high-performance cache architecture

1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers, 2000

We present results of characterization of power dissipation in on-chip cache memories. Details of... more We present results of characterization of power dissipation in on-chip cache memories. Details of power dissipated in different sub-circuits are presented. These results reveal that the memory peripherals and bit array dissipate comparable power. To optimize performance and power of a processor's cache, a multi-divided module (MDM) cache architecture is proposed to save power at memory peripherals as well as

Research paper thumbnail of A self-timed method to minimize spurious transitions in low power CMOS circuits

Proceedings of 1994 IEEE Symposium on Low Power Electronics, 2000

ABSTRACT

Research paper thumbnail of Iterative (TURBO) IQ Imbalance Estimation and Correction in BICM-ID for Flat Fading Channels

2007 Ieee 66th Vehicular Technology Conference, Sep 1, 2007

ABSTRACT

Research paper thumbnail of Effect of Word-length Precision on the Performance of MIMO Systems

2007 Ieee International Symposium on Circuits and Systems, May 27, 2007

ABSTRACT

Research paper thumbnail of System, apparatus and methods for controlling multiple output converters

Research paper thumbnail of Implementation of a High Speed Digital Band-Pass Sigma-Delta Modulator for a Wireless Transmitter

2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs, 2005

Abstract Digital sigma-delta modulators are used extensively in CMOS wireless SoC designs to achi... more Abstract Digital sigma-delta modulators are used extensively in CMOS wireless SoC designs to achieve high-resolution data conversion while controlling the quantization noise spectrum. This paper presents an implementation of a 90 nm CMOS digital band-pass ...

Research paper thumbnail of Tutorial on interconnect modeling, signal integrity and reliability verification in deep sub-micron digital designs

Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454)

ABSTRACT Not Available

Research paper thumbnail of LAPLUS: An Efficient, Effective and Stable Switch Algorithm for Flow Control of the Available Bit Rate ATM Service

Proceedings - IEEE INFOCOM

Research paper thumbnail of Mismatch considerations in an RF-DAC design for a digital polar EDGE transmitter

2011 IEEE International Symposium on Radio-Frequency Integration Technology, 2011

ABSTRACT We present a systematic approach for the design and analysis of a high-resolution RF-DAC... more ABSTRACT We present a systematic approach for the design and analysis of a high-resolution RF-DAC. The RF-DAC is implemented in 65 nm CMOS as an integral part of a digital polar EDGE transmitter based on the Digital-RF-Processor (DRP™). It combines the functionality of a traditional baseband DAC and a mixer. This paper addresses the issue of a transistor mismatch, which has become a key design challenge at fine geometry process nodes. A method is presented to analyze the mismatch, quantify it and relate it to the system specifications. The presented techniques are used in a commercial GSM/EDGE SoC radio, in which the transmitter's wideband noise (WBN) performance significantly exceeds the EDGE specifications with more than 6 dB margin at 20 MHz offset from the carrier frequency.

Research paper thumbnail of Energy optimization of multilevel cache architectures for RISC and CISC processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1998

Abstract—In this paper, we present the characterization and design of energy-efficient, on-chip c... more Abstract—In this paper, we present the characterization and design of energy-efficient, on-chip cache memories. The charac-terization of power dissipation in on-chip cache memories reveals that the memory peripheral interface circuits and bit array dissipate comparable power. To ...

Research paper thumbnail of 1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS

IEEE Transactions on Circuits and Systems II: Express Briefs, 2006

Abstract—We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm dig... more Abstract—We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile ...

Research paper thumbnail of Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2003

A novel digitally controlled oscillator (DCO)-based architecture for frequency synthesis in wirel... more A novel digitally controlled oscillator (DCO)-based architecture for frequency synthesis in wireless RF applications is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed 61 dithering. Other imperfections of analog circuits are compensated through digital means. The presented ideas enable the employment of fully-digital frequency synthesizers using sophisticated signal processing algorithms, realized in the most advanced deep-submicrometer digital CMOS processes which allow almost no analog extensions. They also promote costeffective integration with the digital back-end onto a single silicon die. The demonstrator test chip has been fabricated in a digital 0.13-m CMOS process together with a DSP, which acts as a digital baseband processor with a large number of digital gates in order to investigate noise coupling. The phase noise is 112 dBc/Hz at 500-kHz offset. The close-in spurious tones are below 62 dBc, while the far-out spurs are below 80 dBc. The presented ideas have been incorporated in a commercial Bluetooth transceiver.

Research paper thumbnail of All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

IEEE Journal of Solid-State Circuits, 2004

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS proc... more We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm 2 and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

Research paper thumbnail of A first digitally-controlled oscillator in a deep-submicron CMOS process for multi-GHz wireless applications

IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003

Abstract A novel digitally-controlled oscillator (DCO) architecture for multi-GHz RF applications... more Abstract A novel digitally-controlled oscillator (DCO) architecture for multi-GHz RF applications is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed ...

Research paper thumbnail of Passivity-Based Control for Direct Voltage Regulation for Boost DC-DC Converter

Research paper thumbnail of Digit Serial Multipliers

Journal of Parallel and Distributed Computing, Feb 1, 1991

... 11, 1S61oZ ( 1991) Digit Serial Multipliers PORAS T. BALSARA Erik Jonsson School of Engineeri... more ... 11, 1S61oZ ( 1991) Digit Serial Multipliers PORAS T. BALSARA Erik Jonsson School of Engineering Computer Science, The University of Texas at Dallas, PO Box 830688, MP33, Richardson, Texas 75083 AND ROBERT M. OWENS AND MARY JANE IRWIN Department of ...

Research paper thumbnail of Analog Input Output Linearization Control

Research paper thumbnail of VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition

Proceedings of the 20th International Conference on Vlsi Design Held Jointly With 6th International Conference Embedded Systems, 2007

Matrix inversion and triangularization problems are common to a wide variety of communication sys... more Matrix inversion and triangularization problems are common to a wide variety of communication systems, signal processing applications and solution of a set of linear equations. Matrix inversion is a computationally intensive process and its hardware implementation based on fixed-point (FP) arithmetic is a challenging problem. This paper proposes a fully parallel VLSI architecture under fixed-precision for the inverse computation of

Research paper thumbnail of 完全ディジタルPLL回路の設計 : ディープ・サブミクロンCMOSプロセスで実現する

Research paper thumbnail of QMOS digital logic circuits

Research paper thumbnail of Characterization and design of a low-power, high-performance cache architecture

1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers, 2000

We present results of characterization of power dissipation in on-chip cache memories. Details of... more We present results of characterization of power dissipation in on-chip cache memories. Details of power dissipated in different sub-circuits are presented. These results reveal that the memory peripherals and bit array dissipate comparable power. To optimize performance and power of a processor's cache, a multi-divided module (MDM) cache architecture is proposed to save power at memory peripherals as well as

Research paper thumbnail of A self-timed method to minimize spurious transitions in low power CMOS circuits

Proceedings of 1994 IEEE Symposium on Low Power Electronics, 2000

ABSTRACT

Research paper thumbnail of Iterative (TURBO) IQ Imbalance Estimation and Correction in BICM-ID for Flat Fading Channels

2007 Ieee 66th Vehicular Technology Conference, Sep 1, 2007

ABSTRACT

Research paper thumbnail of Effect of Word-length Precision on the Performance of MIMO Systems

2007 Ieee International Symposium on Circuits and Systems, May 27, 2007

ABSTRACT

Research paper thumbnail of System, apparatus and methods for controlling multiple output converters

Research paper thumbnail of Implementation of a High Speed Digital Band-Pass Sigma-Delta Modulator for a Wireless Transmitter

2005 IEEE Dallas/CAS Workshop on Architecture, Circuits and Implementtation of SOCs, 2005

Abstract Digital sigma-delta modulators are used extensively in CMOS wireless SoC designs to achi... more Abstract Digital sigma-delta modulators are used extensively in CMOS wireless SoC designs to achieve high-resolution data conversion while controlling the quantization noise spectrum. This paper presents an implementation of a 90 nm CMOS digital band-pass ...