Siwat Saibua | University of Texas at Dallas (original) (raw)
Papers by Siwat Saibua
IEEE Transactions on Circuits and Systems II: Express Briefs, 2012
IEEE Transactions on Circuits and Systems I: Regular Papers, 2013
To reduce the substantial leakage current, the supply voltage of SRAM cells has being scaled down... more To reduce the substantial leakage current, the supply voltage of SRAM cells has being scaled down towards its lower limit, which is called the data Retention Voltage (DRV). Although the power consumption is largely reduced, this down-scaling trend, however, impacts the stability of the SRAM cell due to the unpredictable process or device parameter variations. In this work, we propose a novel method to evaluate the DRV of SRAM cells at the presence of variations. The DRV issue is first formulated as a time domain worst performance bound problem. To accurately and efficiently evaluate the DRV, a multi-start point (MSP) optimization strategy is then studied and developed with the use of practical circuit simulator. One feature of the proposed method is that it can efficiently evaluate the DRV without suffering from any process/model accuracy. Experiment results show that it achieves a speedup of 3 and 5-7 order over the Importance Sampling (IS) and Monte Carlo (MC) method respectively under the context of the DRV evaluation in this paper. The proposed method can serve as an efficient DRV evaluation tool on any specific technology process or in-house circuit simulator. In this work, the DRVs at the technology node from 130 nm to 45 nm under the influence of different variation sources are also presented and analyzed.
JMIR mHealth and uHealth
Background: Hearing ability is important for children to develop speech and language skills as th... more Background: Hearing ability is important for children to develop speech and language skills as they grow. After a mandatory newborn hearing screening, group or mass screening of children at later ages, such as at preschool age, is often practiced. For this practice to be effective and accessible in low-resource countries such as Thailand, innovative enabling tools that make use of pervasive mobile and smartphone technology should be considered. Objective: This study aims to develop a cost-effective, tablet-based hearing screening system that can perform a rapid minimal speech recognition level test. Methods: An Android-based screening app was developed. The screening protocol involved asking children to choose pictures corresponding to a set of predefined words heard at various sound levels offered in a specifically designed sequence. For the app, the set of words was validated, and their corresponding speech power levels were calibrated. We recruited 122 children, aged 4-5 years, during the development phase. Another 63 children of the same age were screened for their hearing abilities using the app in version 2. The results in terms of the sensitivity and specificity were compared with those measured using the conventional audiometric equipment. Results: For screening purposes, the sensitivity of the developed screening system version 2 was 76.67% (95% CI 59.07-88.21), and the specificity was 95.83% (95% CI 89.77-98.37) for screening children with mild hearing loss (pure-tone average threshold at 1, 2, and 4 kHz, >20 dB). The time taken for the screening of each child was 150.52 (SD 19.07) seconds (95% CI 145.71-155.32 seconds). The average time used for conventional play audiometry was 11.79 (SD 3.66) minutes (95% CI 10.85-12.71 minutes). Conclusions: This study shows the potential use of a tablet-based system for rapid and mobile hearing screening. The system was shown to have good overall sensitivity and specificity. Overall, the idea can be easily adopted for systems based on other languages.
JMIR mHealth and uHealth, Oct 23, 2018
Background: Hearing ability is important for children to develop speech and language skills as th... more Background: Hearing ability is important for children to develop speech and language skills as they grow. After a mandatory newborn hearing screening, group or mass screening of children at later ages, such as at preschool age, is often practiced. For this practice to be effective and accessible in low-resource countries such as Thailand, innovative enabling tools that make use of pervasive mobile and smartphone technology should be considered. Objective: This study aims to develop a cost-effective, tablet-based hearing screening system that can perform a rapid minimal speech recognition level test. Methods: An Android-based screening app was developed. The screening protocol involved asking children to choose pictures corresponding to a set of predefined words heard at various sound levels offered in a specifically designed sequence. For the app, the set of words was validated, and their corresponding speech power levels were calibrated. We recruited 122 children, aged 4-5 years, during the development phase. Another 63 children of the same age were screened for their hearing abilities using the app in version 2. The results in terms of the sensitivity and specificity were compared with those measured using the conventional audiometric equipment. Results: For screening purposes, the sensitivity of the developed screening system version 2 was 76.67% (95% CI 59.07-88.21), and the specificity was 95.83% (95% CI 89.77-98.37) for screening children with mild hearing loss (pure-tone average threshold at 1, 2, and 4 kHz, >20 dB). The time taken for the screening of each child was 150.52 (SD 19.07) seconds (95% CI 145.71-155.32 seconds). The average time used for conventional play audiometry was 11.79 (SD 3.66) minutes (95% CI 10.85-12.71 minutes). Conclusions: This study shows the potential use of a tablet-based system for rapid and mobile hearing screening. The system was shown to have good overall sensitivity and specificity. Overall, the idea can be easily adopted for systems based on other languages.
To reduce the substantial leakage current, the supply voltage of SRAM cells has being scaled down... more To reduce the substantial leakage current, the supply voltage of SRAM cells has being scaled down towards its lower limit, which is called the data Retention Voltage (DRV). Although the power consumption is largely reduced, this down-scaling trend, however, impacts the stability of the SRAM cell due to the unpredictable process or device parameter variations. In this work, we propose a novel method to evaluate the DRV of SRAM cells at the presence of variations. The DRV issue is first formulated as a time domain worst performance bound problem. To accurately and efficiently evaluate the DRV, a multi-start point (MSP) optimization strategy is then studied and developed with the use of practical circuit simulator. One feature of the proposed method is that it can efficiently evaluate the DRV without suffering from any process/model accuracy. Experiment results show that it achieves a speedup of 3 and 5-7 order over the Importance Sampling (IS) and Monte Carlo (MC) method respectively under the context of the DRV evaluation in this paper. The proposed method can serve as an efficient DRV evaluation tool on any specific technology process or in-house circuit simulator. In this work, the DRVs at the technology node from 130 nm to 45 nm under the influence of different variation sources are also presented and analyzed.
The continued scaling of the minimum feature size of contemporary chips has made circuit performa... more The continued scaling of the minimum feature size of contemporary chips has made circuit performance increasingly susceptible to the process variations. Many approaches have been proposed to estimate the circuit performance bounds with respect to process or circuit parameter variations in the recent years. The Monte Carlo method is the most popular one among them. However, this method usually produces underestimated results and needs a large number of simulation runs to achieve an accurate estimation. The approach based on Kharitonov's method has been recently proposed. This method requires all coefficient variations in the system transfer function to be independent from each other. Unfortunately, most real circuits do not satisfy this constraint. Therefore, it tends to overestimate the performance bounds in real application due to the parameter-independent requirement. This short paper proposes an optimization approach on a transfer function of a linear circuit to evaluate the performance bounds under process variations. The magnitude and phase bounds of a linear system can be calculated by the proposed method at each frequency point. Furthermore, the parameter-independent requirement in Kharitonov's method is resolved by the proposed method. The proposed method has been applied to a CMOS two-stage amplifier. The experimental result shows that it evaluates the magnitude and phase bounds of a linear system accurately in much less computation time as compared with the Monte Carlo method. All experimental results were carried out using a standard 0.35-μm CMOS process technology.
The process variations are unavoidable in today's VLSI circuits due to the continuing scaled IC t... more The process variations are unavoidable in today's VLSI circuits due to the continuing scaled IC technologies, therefore, the likely behaviors of VLSI circuits with process variations may fail to meet the performance specifications. This paper addresses an efficient method to evaluate the performance bounds of VLSI circuits with process variations in time domain. The described approach proceeds by solving a Nonlinear Programming (NLP) problem to find the upper and lower bounds of the interested outputs, either a node voltage or a branch current, constrained by linearlized equations, circuit equations and parameter variations. The preliminary result shows the performance bounds from the proposed method are sufficiently tight comparing with the bounds obtained from intensive Monte Carlo samplings in SPICE.
Proceeding of IEEE International SoC Conference (SOCC), Sep 26, 2011
Abstract Continuous scaling in CMOS fabrication process makes integrated circuits more vulnerable... more Abstract Continuous scaling in CMOS fabrication process makes integrated circuits more vulnerable to process variations. The impact on circuit performance caused by process variations in CMOS circuit is usually analyzed by Monte Carlo method with a large number ...
SAT problem has been an active research subject and many impressive SAT solvers have been propose... more SAT problem has been an active research subject and many impressive SAT solvers have been proposed. Most of algorithms used in modern SAT solvers are based on tree structured searching strategy, combining with heuristic approaches to reduce the search space. In contrast to most existing solvers, we treat SAT problem as a logical optimization issue which can be solved by a logic minimizer. In this paper, we propose a Folding Strategy (FS) based on the Shannon's expansion theorem such that in every step, one variable is deducted and the size of search space is shrunk. The new method will find the solution after Karnaugh Map (K-Map) is folded no more than n (number of variables) times because search space is decreased by half in each folding step.
IEEE Transactions on Circuits and Systems II: Express Briefs, 2012
IEEE Transactions on Circuits and Systems I: Regular Papers, 2013
To reduce the substantial leakage current, the supply voltage of SRAM cells has being scaled down... more To reduce the substantial leakage current, the supply voltage of SRAM cells has being scaled down towards its lower limit, which is called the data Retention Voltage (DRV). Although the power consumption is largely reduced, this down-scaling trend, however, impacts the stability of the SRAM cell due to the unpredictable process or device parameter variations. In this work, we propose a novel method to evaluate the DRV of SRAM cells at the presence of variations. The DRV issue is first formulated as a time domain worst performance bound problem. To accurately and efficiently evaluate the DRV, a multi-start point (MSP) optimization strategy is then studied and developed with the use of practical circuit simulator. One feature of the proposed method is that it can efficiently evaluate the DRV without suffering from any process/model accuracy. Experiment results show that it achieves a speedup of 3 and 5-7 order over the Importance Sampling (IS) and Monte Carlo (MC) method respectively under the context of the DRV evaluation in this paper. The proposed method can serve as an efficient DRV evaluation tool on any specific technology process or in-house circuit simulator. In this work, the DRVs at the technology node from 130 nm to 45 nm under the influence of different variation sources are also presented and analyzed.
JMIR mHealth and uHealth
Background: Hearing ability is important for children to develop speech and language skills as th... more Background: Hearing ability is important for children to develop speech and language skills as they grow. After a mandatory newborn hearing screening, group or mass screening of children at later ages, such as at preschool age, is often practiced. For this practice to be effective and accessible in low-resource countries such as Thailand, innovative enabling tools that make use of pervasive mobile and smartphone technology should be considered. Objective: This study aims to develop a cost-effective, tablet-based hearing screening system that can perform a rapid minimal speech recognition level test. Methods: An Android-based screening app was developed. The screening protocol involved asking children to choose pictures corresponding to a set of predefined words heard at various sound levels offered in a specifically designed sequence. For the app, the set of words was validated, and their corresponding speech power levels were calibrated. We recruited 122 children, aged 4-5 years, during the development phase. Another 63 children of the same age were screened for their hearing abilities using the app in version 2. The results in terms of the sensitivity and specificity were compared with those measured using the conventional audiometric equipment. Results: For screening purposes, the sensitivity of the developed screening system version 2 was 76.67% (95% CI 59.07-88.21), and the specificity was 95.83% (95% CI 89.77-98.37) for screening children with mild hearing loss (pure-tone average threshold at 1, 2, and 4 kHz, >20 dB). The time taken for the screening of each child was 150.52 (SD 19.07) seconds (95% CI 145.71-155.32 seconds). The average time used for conventional play audiometry was 11.79 (SD 3.66) minutes (95% CI 10.85-12.71 minutes). Conclusions: This study shows the potential use of a tablet-based system for rapid and mobile hearing screening. The system was shown to have good overall sensitivity and specificity. Overall, the idea can be easily adopted for systems based on other languages.
JMIR mHealth and uHealth, Oct 23, 2018
Background: Hearing ability is important for children to develop speech and language skills as th... more Background: Hearing ability is important for children to develop speech and language skills as they grow. After a mandatory newborn hearing screening, group or mass screening of children at later ages, such as at preschool age, is often practiced. For this practice to be effective and accessible in low-resource countries such as Thailand, innovative enabling tools that make use of pervasive mobile and smartphone technology should be considered. Objective: This study aims to develop a cost-effective, tablet-based hearing screening system that can perform a rapid minimal speech recognition level test. Methods: An Android-based screening app was developed. The screening protocol involved asking children to choose pictures corresponding to a set of predefined words heard at various sound levels offered in a specifically designed sequence. For the app, the set of words was validated, and their corresponding speech power levels were calibrated. We recruited 122 children, aged 4-5 years, during the development phase. Another 63 children of the same age were screened for their hearing abilities using the app in version 2. The results in terms of the sensitivity and specificity were compared with those measured using the conventional audiometric equipment. Results: For screening purposes, the sensitivity of the developed screening system version 2 was 76.67% (95% CI 59.07-88.21), and the specificity was 95.83% (95% CI 89.77-98.37) for screening children with mild hearing loss (pure-tone average threshold at 1, 2, and 4 kHz, >20 dB). The time taken for the screening of each child was 150.52 (SD 19.07) seconds (95% CI 145.71-155.32 seconds). The average time used for conventional play audiometry was 11.79 (SD 3.66) minutes (95% CI 10.85-12.71 minutes). Conclusions: This study shows the potential use of a tablet-based system for rapid and mobile hearing screening. The system was shown to have good overall sensitivity and specificity. Overall, the idea can be easily adopted for systems based on other languages.
To reduce the substantial leakage current, the supply voltage of SRAM cells has being scaled down... more To reduce the substantial leakage current, the supply voltage of SRAM cells has being scaled down towards its lower limit, which is called the data Retention Voltage (DRV). Although the power consumption is largely reduced, this down-scaling trend, however, impacts the stability of the SRAM cell due to the unpredictable process or device parameter variations. In this work, we propose a novel method to evaluate the DRV of SRAM cells at the presence of variations. The DRV issue is first formulated as a time domain worst performance bound problem. To accurately and efficiently evaluate the DRV, a multi-start point (MSP) optimization strategy is then studied and developed with the use of practical circuit simulator. One feature of the proposed method is that it can efficiently evaluate the DRV without suffering from any process/model accuracy. Experiment results show that it achieves a speedup of 3 and 5-7 order over the Importance Sampling (IS) and Monte Carlo (MC) method respectively under the context of the DRV evaluation in this paper. The proposed method can serve as an efficient DRV evaluation tool on any specific technology process or in-house circuit simulator. In this work, the DRVs at the technology node from 130 nm to 45 nm under the influence of different variation sources are also presented and analyzed.
The continued scaling of the minimum feature size of contemporary chips has made circuit performa... more The continued scaling of the minimum feature size of contemporary chips has made circuit performance increasingly susceptible to the process variations. Many approaches have been proposed to estimate the circuit performance bounds with respect to process or circuit parameter variations in the recent years. The Monte Carlo method is the most popular one among them. However, this method usually produces underestimated results and needs a large number of simulation runs to achieve an accurate estimation. The approach based on Kharitonov's method has been recently proposed. This method requires all coefficient variations in the system transfer function to be independent from each other. Unfortunately, most real circuits do not satisfy this constraint. Therefore, it tends to overestimate the performance bounds in real application due to the parameter-independent requirement. This short paper proposes an optimization approach on a transfer function of a linear circuit to evaluate the performance bounds under process variations. The magnitude and phase bounds of a linear system can be calculated by the proposed method at each frequency point. Furthermore, the parameter-independent requirement in Kharitonov's method is resolved by the proposed method. The proposed method has been applied to a CMOS two-stage amplifier. The experimental result shows that it evaluates the magnitude and phase bounds of a linear system accurately in much less computation time as compared with the Monte Carlo method. All experimental results were carried out using a standard 0.35-μm CMOS process technology.
The process variations are unavoidable in today's VLSI circuits due to the continuing scaled IC t... more The process variations are unavoidable in today's VLSI circuits due to the continuing scaled IC technologies, therefore, the likely behaviors of VLSI circuits with process variations may fail to meet the performance specifications. This paper addresses an efficient method to evaluate the performance bounds of VLSI circuits with process variations in time domain. The described approach proceeds by solving a Nonlinear Programming (NLP) problem to find the upper and lower bounds of the interested outputs, either a node voltage or a branch current, constrained by linearlized equations, circuit equations and parameter variations. The preliminary result shows the performance bounds from the proposed method are sufficiently tight comparing with the bounds obtained from intensive Monte Carlo samplings in SPICE.
Proceeding of IEEE International SoC Conference (SOCC), Sep 26, 2011
Abstract Continuous scaling in CMOS fabrication process makes integrated circuits more vulnerable... more Abstract Continuous scaling in CMOS fabrication process makes integrated circuits more vulnerable to process variations. The impact on circuit performance caused by process variations in CMOS circuit is usually analyzed by Monte Carlo method with a large number ...
SAT problem has been an active research subject and many impressive SAT solvers have been propose... more SAT problem has been an active research subject and many impressive SAT solvers have been proposed. Most of algorithms used in modern SAT solvers are based on tree structured searching strategy, combining with heuristic approaches to reduce the search space. In contrast to most existing solvers, we treat SAT problem as a logical optimization issue which can be solved by a logic minimizer. In this paper, we propose a Folding Strategy (FS) based on the Shannon's expansion theorem such that in every step, one variable is deducted and the size of search space is shrunk. The new method will find the solution after Karnaugh Map (K-Map) is folded no more than n (number of variables) times because search space is decreased by half in each folding step.