Rakesh Nair | VIT University (original) (raw)

Rakesh Nair

Address: Thiruvananthapuram, Kerala, India

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Papers by Rakesh Nair

Research paper thumbnail of Microcontroller based electronic modules for low velocity airburst Counter Defilade munitions

Present counter defilade airburst weapon systems in defense sector make use of simple logic chips... more Present counter defilade airburst weapon systems in defense sector make use of simple logic chips which are devoid of efficient inbuilt software safety that may cause accidental triggering of munitions. This paper deals with the design and development of microcontroller based electronic modules for counter defilade system for low velocity airburst munitions. The proposed design increases safety, cost efficiency and is highly feasible with existing weapons for infantry units. For system development, airburst analysis of munitions was investigated to theoretically determine the effect on target in defilade. Static rig testing of the entire system has also been performed to determine the response, triggering time and optimization of module design.

Research paper thumbnail of Microcontroller based electronic modules for low velocity airburst Counter Defilade munitions

Present counter defilade airburst weapon systems in defense sector make use of simple logic chips... more Present counter defilade airburst weapon systems in defense sector make use of simple logic chips which are devoid of efficient inbuilt software safety that may cause accidental triggering of munitions. This paper deals with the design and development of microcontroller based electronic modules for counter defilade system for low velocity airburst munitions. The proposed design increases safety, cost efficiency and is highly feasible with existing weapons for infantry units. For system development, airburst analysis of munitions was investigated to theoretically determine the effect on target in defilade. Static rig testing of the entire system has also been performed to determine the response, triggering time and optimization of module design.

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