sridevi sriadibhatla | VIT University (original) (raw)

Papers by sridevi sriadibhatla

Research paper thumbnail of Design and analysis of a dual gate tunnel FET with InGaAs source pockets for improved performance

Research paper thumbnail of Dual bit control low-power dynamic content addressable memory design for IoT applications

TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES, 2019

The Internet of things (IoT) is an emerging area in the semiconductor industry for low-power and ... more The Internet of things (IoT) is an emerging area in the semiconductor industry for low-power and high-speed applications. Many search engines of IoT applications require low power consumption and high-speed content addressable memory (CAM) devices for the transmission of data packets between servers and end devices. A CAM is a hardware device used for transfer of packets in a network router with high speed at the cost of power consumption. In this paper, a new dual bit control precharge free (PF) dynamic content addressable memory (DCAM) has been introduced. The proposed design uses a new charge control circuitry, which is used to control the dual DCAM cell to get the match line output for match/miss. Elimination of the precharge phase before the evaluation phase allows the proposed design to perform more search operations within the evaluation time. The proposed 64-bit PF-DCAM design is implemented using a CMOS 45-nm technology node and Monte Carlo simulations are performed for power and search delay validation. The simulation results show that the proposed design reduces power and search delay when compared to conventional DCAM designs.

Research paper thumbnail of Tunnel FET Based SRAM Cells – A Comparative Review

Communications in Computer and Information Science, 2021

Research paper thumbnail of Hybrid self-controlled precharge-free CAM design for low power and high performance

TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES, 2019

Content-addressable memory (CAM) is a prominent hardware for high-speed lookup search, but consum... more Content-addressable memory (CAM) is a prominent hardware for high-speed lookup search, but consumes larger power. Traditional NOR and NAND match-line (ML) architectures suffer from a short circuit current path sharing and charge sharing respectively during precharge. The recently proposed precharge-free CAM suffers from high search delay and the subsequently proposed self-controlled precharge-free CAM suffers from high power consumption. This paper presents a hybrid self-controlled precharge-free (HSCPF) CAM architecture, which uses a novel charge control circuitry to reduce search delay as well as power consumption. The proposed and existing CAM ML architectures were developed using CMOS 45nm technology node with a supply voltage of 1 V. Simulation results show that the proposed HSCPF CAM-type ML design reduces power consumption and search delay effectively when compared to recent precharge-free CAM-type ML architectural designs.

Research paper thumbnail of InGaAs-Si Double Pocket-Dual Gate Tunnel FET Based 7T SRAM Design

Silicon, 2022

Tunnel FETs (TFETs) are preferable over MOSFETs at lower technology nodes due to their superior p... more Tunnel FETs (TFETs) are preferable over MOSFETs at lower technology nodes due to their superior performance in the subthreshold region in terms of extremely low off current and low subthreshold swing. However, limitations like low drive current, ambipolarity and unidirectional conductivity hamper the usage of TFET device in designing memory structures such as SRAM. In this paper, a new TFET device called Indium Gallium Arsenide - Silicon Double Pocket Dual Gate TFET (InGaAs-Si DP-DGTFET) is proposed. The proposed design shows a relatively high drive current, ON to OFF current ratio, ON current to gate capacitance ratio, subthreshold swing (SS), and lower threshold voltage. The 7T SRAM cell designed using the proposed TFET device significantly improves the performance in terms of read and write speed when compared to Si-DP-DGTFET based SRAM at a supply voltage of 0.7V. The proposed 7T SRAM cell also includes a TFET based NDR sense amplifier circuit to enhance the read operation for l...

Research paper thumbnail of A Low complexity solution to the implementation of linear periodically time varying filters-FPGA implementation

This paper presents an area efficient architecture for a linear periodically time varying (LPTV) ... more This paper presents an area efficient architecture for a linear periodically time varying (LPTV) filter. It is developed from the output switching representation of LPTV filter. In this representation, an N-tap,M Period LPTV filter can be realized by M linear time invariant (LTI) filters of N taps each connected in parallel with an M periodic switch at the output. We devloped an area efficient architecture for LPTV filter from a single N tap LTI filter. We achieve this by distributing the coefficient memory. The proposed architecture utilizes N coefficient multipliers, whereas the conventional output switching realization needs NM multipliers. The proposed architecture is simulated, synthesized and implemented on Virtex FPGA.

Research paper thumbnail of Efficient Precharge-Free CAM Match-Line Architecture Design for Low Power

Lecture Notes in Electrical Engineering, 2018

Content-addressable memory (CAM) is a hardware device which stores lookup data in the memory and ... more Content-addressable memory (CAM) is a hardware device which stores lookup data in the memory and searches that data parallel within a single clock cycle. Conventional CAM operates in three phases which are writing the binary data in the memory, pre-charging, and evaluating the match line (ML). Recently, it is identified that CAM with precharge ML consumes more power due to the short circuit current path. To overcome this problem, here, we proposed CAM architecture without applying precharge to ML which helps to operate CAM with low power and high performance. The precharge-free CAM works on two stages writing and evaluation. This paper compares conventional precharge-based ML architecture like NOR CAM and master-slave CAM of 1 (word) \(\times \) 8 (bits) with a proposed design for power consumption at different mismatches. Simulations results show that when compared to conventional designs, the proposed design minimizes approximately from 86 to 88% of average power.

Research paper thumbnail of Pre-Charge Free Soft Error Hardened Cam Cell Design for Low Power and High Performance

The Content Addressable Memory (CAM) is a high throughput large capacity hardware device. It sear... more The Content Addressable Memory (CAM) is a high throughput large capacity hardware device. It searches stored lookup data in parallel but consumes a large amount of power. NOR CAM cell offers high speed but suffers from high power consumption due to a short circuit current path in the precharge phase during mismatch. The Self-Controlled Precharge Free (SCPF) CAM cell, which removes the precharge phase offers low power consumption. As technology scales down, the reliability of memory nodes are sensitive to Soft Errors Single Event Upsets (SEUs). In this paper, a NOR CAM cell with different types of SRAM cells has been studied by inserting Double Exponential Current Pulse (DECP) at sensitive nodes of a memory cell for soft error hardened design. In addition, radiation hardened precharge-free CAM cell has been proposed for low power and high-performance design. The proposed CAM cell design and soft error hardened NOR CAM cell designs had been simulated and verified using Virtuoso tool a...

Research paper thumbnail of Design and implementation of Area and Power efficient reconfigurable FIR filter with low complexity coefficients

gazi university journal of science, 2019

This paper presents the design and implementation of area and power efficient reconfigurable fini... more This paper presents the design and implementation of area and power efficient reconfigurable finite impulse response (FIR) filter. We present a method for designing a reconfigurable filter with low binary complexity coefficients (LBCC) and thus to optimize the filter while satisfying the design specifications. The total number of non zero binary bits is taken as a measure of the binary complexity (BC) of a coefficient. We propose two implementation architectures namely signed-magnitude architecture (SMA) and signed-decimal architecture (SDA) which are based on 3-bit binary common sub expression elimination (BCSE) algorithm and vertical horizontal BCSE (VHBCSE) algorithm respectively. SMA and SDA reduce the redundant computations of the coefficient multiplications in the filter. The proposed filters are synthesized on tsmc 65nm CMOS technology. The synthesis results show that the proposed filters are area and power efficient when compared with the existing ones.

Research paper thumbnail of Gate diffusion input (Gdi) technique based CAM cell design for low power and high performance

Research paper thumbnail of Efficient CAM cell design for low power and low delay

Content-addressable memory (CAM) is the hardware based particular type of memory device utilized ... more Content-addressable memory (CAM) is the hardware based particular type of memory device utilized for low power and high-speed application. CAMs are developed for precise application without sacrificing their search speed, and it is much faster than random accessmemory (RAM) in search application. CAM executes two essential functions storing and comparing. The additional circuitry during comparison process builds the size of CAM which expands fabrication cost. The new hardware enhances the power consumption since each comparison of the circuitry is dynamic on each clock cycle accordingly. To achieve low power design, some new implementations emulate the operation of CAM by utilizing different CAM cell designs in the CAM architecture. Therefore designing novel CAM cells for low power application in CAM architecture is a challenging task for the designer. This paper compares various CAM cell design at 180nm, 90nm and 45nm for power, delay and analysis is performed in cadence virtuoso t...

Research paper thumbnail of A Survey on Different Techniques and Approaches for Low Power Content-Addressable Memory Architectures

This paper presents a survey on current trends adapted in the low power content addressable memor... more This paper presents a survey on current trends adapted in the low power content addressable memory (CAM) architectures. CAMs are modified for the requirement of high speed, low power table look up function and are especially popular in network routers. CAM is a special type of memory with comparison circuitry. It stores or searches the look up table data with the help of one clock cycle. Large amount of power is consuming during comparison process because of parallel circuitry. CAM architectures are designed to reduce the power by eliminating the number of comparisons. In this paper at architectural level we survey different architectures for reducing dynamic power in CAM design. We reviewed seven different methods at the architectural level for low power.

Research paper thumbnail of SEU sensitivity analysis of low power, precharge-free modified CAM cell

2018 4th International Conference on Devices, Circuits and Systems (ICDCS), 2018

CAM (Content Addressable Memory) is one of the promising memory family used in high speed search ... more CAM (Content Addressable Memory) is one of the promising memory family used in high speed search applications. CAM power dissipation is more due to large number of search operation. NAND and NOR type match-line CAMs are useful in low power applications but they have drawbacks like charge sharing and short circuit at match-lines of the CAM array. Recently the CAM cell was implemented with free of pre-charge circuit by adding a control bit in order to boost-up the match-line only, but not the internal SRAM. In this paper, we are proposing a precharge-free PMOS logic based CAM cell and comparing the metrics of proposed CAM cell with precharge-free NMOS based CAM cell in terms of delay, power and Power-Delay Product (PDP). The simulations are carried out in technology node Cadence design environment. The simulation results shows the PDP of proposed design is 91.17% reduction than NMOS based precharge-free CAM. We also performed a radiation study on both PMOS and NMOS based precharge-fre...

Research paper thumbnail of ASIC Implementation of Low Power, Area Efficient Adaptive FIR Filter Using Pipelined DA

Lecture Notes in Electrical Engineering

This paper presents a brief information on the ASIC implementation of adaptive finite impulse res... more This paper presents a brief information on the ASIC implementation of adaptive finite impulse response (FIR) filters based on pipelined distributed arithmetic (DA) architecture. The pipelined sum of partial products of input samples is stored in the lookup table of the DA. The area of the proposed design is reduced by replacing the adder of the shift accumulation unit with the carry-save adder. The throughput rate of the design is increased by having fast clock to the carry-save adder and slow clock to the remaining circuit. The proposed design is implemented in Synopsys 90 nm CMOS technology. The area delay product (ADP), minimum cycle period (MCP), and energy per sample are reduced when compared with the conventional DA-based architectures.

Research paper thumbnail of Dual-chirality GAA-CNTFET-based SCPF-TCAM cell design for low power and high performance

Journal of Computational Electronics

Ternary content-addressable memory (TCAM) is a type of associative memory used in many applicatio... more Ternary content-addressable memory (TCAM) is a type of associative memory used in many applications for high-speed data searching. We present herein a gate-all-around (GAA) carbon nanotube field-effect transistor (CNTFET)-based self-controlled TCAM cell design with a precharge-free match line. We compare the power–delay product (PDP) and static noise margin between the GAA-CNTFET-based traditional and proposed TCAM cell designs at the 11-nm technology node with a supply voltage of 0.8 V. The simulations are performed using the Virtuoso tool for different parameter values with the Stanford University GAA-CNTFET model. The simulation results show that, compared with the traditional design, the proposed design exhibits a significant reduction in power by 51.30%, delay by 17.16%, and PDP by 59.66% for a chiral vector of (20, 16, 0) with two channels. It is observed that the best chirality for the proposed design is (14, 20, 0) for a single channel, but (16, 16, 0) and (20, 16, 0) for a dual channel in terms of power, delay, stability, and PDP.

Research paper thumbnail of A Microwatt Low Voltage Bandgap Reference for Bio-medical Applications

2017 International Conference on Recent Advances in Electronics and Communication Technology (ICRAECT)

In this paper a microwatt low voltage bandgap reference suitable for the bio-medical application.... more In this paper a microwatt low voltage bandgap reference suitable for the bio-medical application. The Present technique relies on the principle of generating CTAT and PTAT without using any (Bipolar Junction Transistor) BJT and adding them with a proper scaling factor for minimal temperature sensitive reference voltage. Beta multiplier reference circuit has been explored to generate CTAT and PTAT. Implemented in 45nm CMOS technology and simulated with Spectre. Simulation results shows that the proposed reference circuit exhibits 1.2% variation at nominal 745mV output voltage. The circuit consumes 16uW from 0.8V supply and occupying 0.004875mm2 silicon area.

Research paper thumbnail of FPGA Implementation of 32 Tap FIR Filter with Multi Hierarchy Pipeline Architecture

This paper presents an efficient architecture for FIR filter using multi hierarchy pipelining. By... more This paper presents an efficient architecture for FIR filter using multi hierarchy pipelining. By choosing inner clock frequency several times more than the input sampling frequency multiply and accumulate components can be shared and hence the area and delay are optimized. An N tap FIR filter can be divided into N/M groups and two hierarchies of pipelining stages are inserted between N/M groups, within N/M groups and another five within a pipelined multiply and accumulate component (MAC). The design is implemented on vertex v50efg256-7 FPGA and the results presented, show that the proposed filter is optimized in area and delay.

Research paper thumbnail of Design and analysis of a dual gate tunnel FET with InGaAs source pockets for improved performance

Research paper thumbnail of Dual bit control low-power dynamic content addressable memory design for IoT applications

TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES, 2019

The Internet of things (IoT) is an emerging area in the semiconductor industry for low-power and ... more The Internet of things (IoT) is an emerging area in the semiconductor industry for low-power and high-speed applications. Many search engines of IoT applications require low power consumption and high-speed content addressable memory (CAM) devices for the transmission of data packets between servers and end devices. A CAM is a hardware device used for transfer of packets in a network router with high speed at the cost of power consumption. In this paper, a new dual bit control precharge free (PF) dynamic content addressable memory (DCAM) has been introduced. The proposed design uses a new charge control circuitry, which is used to control the dual DCAM cell to get the match line output for match/miss. Elimination of the precharge phase before the evaluation phase allows the proposed design to perform more search operations within the evaluation time. The proposed 64-bit PF-DCAM design is implemented using a CMOS 45-nm technology node and Monte Carlo simulations are performed for power and search delay validation. The simulation results show that the proposed design reduces power and search delay when compared to conventional DCAM designs.

Research paper thumbnail of Tunnel FET Based SRAM Cells – A Comparative Review

Communications in Computer and Information Science, 2021

Research paper thumbnail of Hybrid self-controlled precharge-free CAM design for low power and high performance

TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES, 2019

Content-addressable memory (CAM) is a prominent hardware for high-speed lookup search, but consum... more Content-addressable memory (CAM) is a prominent hardware for high-speed lookup search, but consumes larger power. Traditional NOR and NAND match-line (ML) architectures suffer from a short circuit current path sharing and charge sharing respectively during precharge. The recently proposed precharge-free CAM suffers from high search delay and the subsequently proposed self-controlled precharge-free CAM suffers from high power consumption. This paper presents a hybrid self-controlled precharge-free (HSCPF) CAM architecture, which uses a novel charge control circuitry to reduce search delay as well as power consumption. The proposed and existing CAM ML architectures were developed using CMOS 45nm technology node with a supply voltage of 1 V. Simulation results show that the proposed HSCPF CAM-type ML design reduces power consumption and search delay effectively when compared to recent precharge-free CAM-type ML architectural designs.

Research paper thumbnail of InGaAs-Si Double Pocket-Dual Gate Tunnel FET Based 7T SRAM Design

Silicon, 2022

Tunnel FETs (TFETs) are preferable over MOSFETs at lower technology nodes due to their superior p... more Tunnel FETs (TFETs) are preferable over MOSFETs at lower technology nodes due to their superior performance in the subthreshold region in terms of extremely low off current and low subthreshold swing. However, limitations like low drive current, ambipolarity and unidirectional conductivity hamper the usage of TFET device in designing memory structures such as SRAM. In this paper, a new TFET device called Indium Gallium Arsenide - Silicon Double Pocket Dual Gate TFET (InGaAs-Si DP-DGTFET) is proposed. The proposed design shows a relatively high drive current, ON to OFF current ratio, ON current to gate capacitance ratio, subthreshold swing (SS), and lower threshold voltage. The 7T SRAM cell designed using the proposed TFET device significantly improves the performance in terms of read and write speed when compared to Si-DP-DGTFET based SRAM at a supply voltage of 0.7V. The proposed 7T SRAM cell also includes a TFET based NDR sense amplifier circuit to enhance the read operation for l...

Research paper thumbnail of A Low complexity solution to the implementation of linear periodically time varying filters-FPGA implementation

This paper presents an area efficient architecture for a linear periodically time varying (LPTV) ... more This paper presents an area efficient architecture for a linear periodically time varying (LPTV) filter. It is developed from the output switching representation of LPTV filter. In this representation, an N-tap,M Period LPTV filter can be realized by M linear time invariant (LTI) filters of N taps each connected in parallel with an M periodic switch at the output. We devloped an area efficient architecture for LPTV filter from a single N tap LTI filter. We achieve this by distributing the coefficient memory. The proposed architecture utilizes N coefficient multipliers, whereas the conventional output switching realization needs NM multipliers. The proposed architecture is simulated, synthesized and implemented on Virtex FPGA.

Research paper thumbnail of Efficient Precharge-Free CAM Match-Line Architecture Design for Low Power

Lecture Notes in Electrical Engineering, 2018

Content-addressable memory (CAM) is a hardware device which stores lookup data in the memory and ... more Content-addressable memory (CAM) is a hardware device which stores lookup data in the memory and searches that data parallel within a single clock cycle. Conventional CAM operates in three phases which are writing the binary data in the memory, pre-charging, and evaluating the match line (ML). Recently, it is identified that CAM with precharge ML consumes more power due to the short circuit current path. To overcome this problem, here, we proposed CAM architecture without applying precharge to ML which helps to operate CAM with low power and high performance. The precharge-free CAM works on two stages writing and evaluation. This paper compares conventional precharge-based ML architecture like NOR CAM and master-slave CAM of 1 (word) \(\times \) 8 (bits) with a proposed design for power consumption at different mismatches. Simulations results show that when compared to conventional designs, the proposed design minimizes approximately from 86 to 88% of average power.

Research paper thumbnail of Pre-Charge Free Soft Error Hardened Cam Cell Design for Low Power and High Performance

The Content Addressable Memory (CAM) is a high throughput large capacity hardware device. It sear... more The Content Addressable Memory (CAM) is a high throughput large capacity hardware device. It searches stored lookup data in parallel but consumes a large amount of power. NOR CAM cell offers high speed but suffers from high power consumption due to a short circuit current path in the precharge phase during mismatch. The Self-Controlled Precharge Free (SCPF) CAM cell, which removes the precharge phase offers low power consumption. As technology scales down, the reliability of memory nodes are sensitive to Soft Errors Single Event Upsets (SEUs). In this paper, a NOR CAM cell with different types of SRAM cells has been studied by inserting Double Exponential Current Pulse (DECP) at sensitive nodes of a memory cell for soft error hardened design. In addition, radiation hardened precharge-free CAM cell has been proposed for low power and high-performance design. The proposed CAM cell design and soft error hardened NOR CAM cell designs had been simulated and verified using Virtuoso tool a...

Research paper thumbnail of Design and implementation of Area and Power efficient reconfigurable FIR filter with low complexity coefficients

gazi university journal of science, 2019

This paper presents the design and implementation of area and power efficient reconfigurable fini... more This paper presents the design and implementation of area and power efficient reconfigurable finite impulse response (FIR) filter. We present a method for designing a reconfigurable filter with low binary complexity coefficients (LBCC) and thus to optimize the filter while satisfying the design specifications. The total number of non zero binary bits is taken as a measure of the binary complexity (BC) of a coefficient. We propose two implementation architectures namely signed-magnitude architecture (SMA) and signed-decimal architecture (SDA) which are based on 3-bit binary common sub expression elimination (BCSE) algorithm and vertical horizontal BCSE (VHBCSE) algorithm respectively. SMA and SDA reduce the redundant computations of the coefficient multiplications in the filter. The proposed filters are synthesized on tsmc 65nm CMOS technology. The synthesis results show that the proposed filters are area and power efficient when compared with the existing ones.

Research paper thumbnail of Gate diffusion input (Gdi) technique based CAM cell design for low power and high performance

Research paper thumbnail of Efficient CAM cell design for low power and low delay

Content-addressable memory (CAM) is the hardware based particular type of memory device utilized ... more Content-addressable memory (CAM) is the hardware based particular type of memory device utilized for low power and high-speed application. CAMs are developed for precise application without sacrificing their search speed, and it is much faster than random accessmemory (RAM) in search application. CAM executes two essential functions storing and comparing. The additional circuitry during comparison process builds the size of CAM which expands fabrication cost. The new hardware enhances the power consumption since each comparison of the circuitry is dynamic on each clock cycle accordingly. To achieve low power design, some new implementations emulate the operation of CAM by utilizing different CAM cell designs in the CAM architecture. Therefore designing novel CAM cells for low power application in CAM architecture is a challenging task for the designer. This paper compares various CAM cell design at 180nm, 90nm and 45nm for power, delay and analysis is performed in cadence virtuoso t...

Research paper thumbnail of A Survey on Different Techniques and Approaches for Low Power Content-Addressable Memory Architectures

This paper presents a survey on current trends adapted in the low power content addressable memor... more This paper presents a survey on current trends adapted in the low power content addressable memory (CAM) architectures. CAMs are modified for the requirement of high speed, low power table look up function and are especially popular in network routers. CAM is a special type of memory with comparison circuitry. It stores or searches the look up table data with the help of one clock cycle. Large amount of power is consuming during comparison process because of parallel circuitry. CAM architectures are designed to reduce the power by eliminating the number of comparisons. In this paper at architectural level we survey different architectures for reducing dynamic power in CAM design. We reviewed seven different methods at the architectural level for low power.

Research paper thumbnail of SEU sensitivity analysis of low power, precharge-free modified CAM cell

2018 4th International Conference on Devices, Circuits and Systems (ICDCS), 2018

CAM (Content Addressable Memory) is one of the promising memory family used in high speed search ... more CAM (Content Addressable Memory) is one of the promising memory family used in high speed search applications. CAM power dissipation is more due to large number of search operation. NAND and NOR type match-line CAMs are useful in low power applications but they have drawbacks like charge sharing and short circuit at match-lines of the CAM array. Recently the CAM cell was implemented with free of pre-charge circuit by adding a control bit in order to boost-up the match-line only, but not the internal SRAM. In this paper, we are proposing a precharge-free PMOS logic based CAM cell and comparing the metrics of proposed CAM cell with precharge-free NMOS based CAM cell in terms of delay, power and Power-Delay Product (PDP). The simulations are carried out in technology node Cadence design environment. The simulation results shows the PDP of proposed design is 91.17% reduction than NMOS based precharge-free CAM. We also performed a radiation study on both PMOS and NMOS based precharge-fre...

Research paper thumbnail of ASIC Implementation of Low Power, Area Efficient Adaptive FIR Filter Using Pipelined DA

Lecture Notes in Electrical Engineering

This paper presents a brief information on the ASIC implementation of adaptive finite impulse res... more This paper presents a brief information on the ASIC implementation of adaptive finite impulse response (FIR) filters based on pipelined distributed arithmetic (DA) architecture. The pipelined sum of partial products of input samples is stored in the lookup table of the DA. The area of the proposed design is reduced by replacing the adder of the shift accumulation unit with the carry-save adder. The throughput rate of the design is increased by having fast clock to the carry-save adder and slow clock to the remaining circuit. The proposed design is implemented in Synopsys 90 nm CMOS technology. The area delay product (ADP), minimum cycle period (MCP), and energy per sample are reduced when compared with the conventional DA-based architectures.

Research paper thumbnail of Dual-chirality GAA-CNTFET-based SCPF-TCAM cell design for low power and high performance

Journal of Computational Electronics

Ternary content-addressable memory (TCAM) is a type of associative memory used in many applicatio... more Ternary content-addressable memory (TCAM) is a type of associative memory used in many applications for high-speed data searching. We present herein a gate-all-around (GAA) carbon nanotube field-effect transistor (CNTFET)-based self-controlled TCAM cell design with a precharge-free match line. We compare the power–delay product (PDP) and static noise margin between the GAA-CNTFET-based traditional and proposed TCAM cell designs at the 11-nm technology node with a supply voltage of 0.8 V. The simulations are performed using the Virtuoso tool for different parameter values with the Stanford University GAA-CNTFET model. The simulation results show that, compared with the traditional design, the proposed design exhibits a significant reduction in power by 51.30%, delay by 17.16%, and PDP by 59.66% for a chiral vector of (20, 16, 0) with two channels. It is observed that the best chirality for the proposed design is (14, 20, 0) for a single channel, but (16, 16, 0) and (20, 16, 0) for a dual channel in terms of power, delay, stability, and PDP.

Research paper thumbnail of A Microwatt Low Voltage Bandgap Reference for Bio-medical Applications

2017 International Conference on Recent Advances in Electronics and Communication Technology (ICRAECT)

In this paper a microwatt low voltage bandgap reference suitable for the bio-medical application.... more In this paper a microwatt low voltage bandgap reference suitable for the bio-medical application. The Present technique relies on the principle of generating CTAT and PTAT without using any (Bipolar Junction Transistor) BJT and adding them with a proper scaling factor for minimal temperature sensitive reference voltage. Beta multiplier reference circuit has been explored to generate CTAT and PTAT. Implemented in 45nm CMOS technology and simulated with Spectre. Simulation results shows that the proposed reference circuit exhibits 1.2% variation at nominal 745mV output voltage. The circuit consumes 16uW from 0.8V supply and occupying 0.004875mm2 silicon area.

Research paper thumbnail of FPGA Implementation of 32 Tap FIR Filter with Multi Hierarchy Pipeline Architecture

This paper presents an efficient architecture for FIR filter using multi hierarchy pipelining. By... more This paper presents an efficient architecture for FIR filter using multi hierarchy pipelining. By choosing inner clock frequency several times more than the input sampling frequency multiply and accumulate components can be shared and hence the area and delay are optimized. An N tap FIR filter can be divided into N/M groups and two hierarchies of pipelining stages are inserted between N/M groups, within N/M groups and another five within a pipelined multiply and accumulate component (MAC). The design is implemented on vertex v50efg256-7 FPGA and the results presented, show that the proposed filter is optimized in area and delay.