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Papers by Rajendra Patrikar

Microsystem Technologies, 2015

2014 8th Asia Modelling Symposium, 2014

Communications in Computer and Information Science, 2013

ABSTRACT The potential impact of fin width and graded channel doping on the analog performance of... more ABSTRACT The potential impact of fin width and graded channel doping on the analog performance of 22nm n-channel FinFET are studied using well calibrated 3D TCAD simulations. It is ascertained that for FinFETs, lesser the fin width, better the characteristics. But limitations in lithography process curb the fin width to be scaled beyond 10nm. Stability of the fins patterned beyond 10nm width is to be viewed with suspected eyes. It is observed that Graded doping of the channel will improve threshold voltage and hence the ratio of Ion to Ioff will also increase, which is desired for enhanced performance in analog applications.

The Network-on-Chip (NoC) is Network-version of Systemon-Chip (SoC) means that on-chip communicat... more The Network-on-Chip (NoC) is Network-version of Systemon-Chip (SoC) means that on-chip communication is done through packet based networks. In NOC topology, routing algorithm and switching are main terminology .The routing algorithm is one of the key factor in NOC architecture. The routing algorithm ,which defines as the path taken by a packet between the source and the destination .As XY routing algorithm mainly used in NOC because of its simplicity. This paper basically review of XY routing algorithm in which we study a different type of XY routing algorithm. The classification of XY routing algorithm is totally depend upon the environment and requirement. Such that IX/Y routing algorithm is for less collision in network, for deadlock-free and livelock-free DyXY is used, for fault-tolerant XYX routing algorithm is proposed and Adaptive XY routing algorithm is used for fully utilization of network resource.

In The Network on chip (NoC) is an approach to designing the communication subsystem between IP c... more In The Network on chip (NoC) is an approach to designing the communication subsystem between IP cores in System on Chip (SoC). Network on chip provides an attractive alternative solution to traditional bus based interconnection scheme. NoC architectural design has ability by which various IP cores communicate with one another through router & switching mechanism. The switching mechanism plays a vital role to move the data from an input channel and place it on an output channel. Virtual cut through (VCT) and wormhole (WH) switching techniques are widely used in NoC architecture. In this paper, virtual cut through switching technique has been proposed for Network on chip architecture and its performance is analyzed using the parameters such as latency & power.

Microelectronics Reliability

... 173–178. [2] PK Lala, Self-checking and fault-tolerant digital system design, Morgan Kauffman... more ... 173–178. [2] PK Lala, Self-checking and fault-tolerant digital system design, Morgan Kauffman Publishers, San Francisco (2001). [3] Alderighi' Monica, D'Angelol Sergio, Metra' Cecilia, Sechi Giacomo R. Novel fault-tolerant adder design for FPGA-based systems. ...

). The design is synthesized using Xilinx Virtex4 XC4VLX200 device. The functional behavior is ve... more ). The design is synthesized using Xilinx Virtex4 XC4VLX200 device. The functional behavior is verified using Modelsim XE III 6.2 C. The delay and throughput values are obtained for variable payload sizes. Throughput-Power and Delay-Power characteristics are also verified for NoC.

The emphasizes on higher data rates and spectral efficiency has driven the industry towards linea... more The emphasizes on higher data rates and spectral efficiency has driven the industry towards linear modulation techniques such as QPSK, 64 QAM, or multicarrier configurations. The result is a signal with a fluctuating envelope which generates intermodulation (IM) distortion from the power amplifiers. Since most of the IM power appears as interference in adjacent channels, it is important to use a highly linear power amplifier. This paper describes a new approach of using a Diode as a predistorter in view of minimizing non linear distortion introduced by the high power amplifier in microwave radio links. The approach is based on preventing the base-collector junction from becoming forward biased also preventing VDS > VGS-Vt in case of MOSFETs / pHEMTs. This approach has two advantages 1) It prevents the transistor to go into saturation 2) Reduces the effect of nonlinear terms generated by the active device.

In wireless sensor networks (WSN), nodes are randomly deployed. Most of all protocols in WSN are ... more In wireless sensor networks (WSN), nodes are randomly deployed. Most of all protocols in WSN are designed for its random deployment. Projective geometry can be used for the fixed-geometrical deployment of wireless sensor nodes. This strategy can be used for deploying nodes in smart houses, hotels, offices, underground mines etc. For environmental monitoring on large geographical area random deployment is used. In random deployment many redundant sensors are used which increases the cost. In fixed geometrical deployment calculated number of nodes with their exact location can be deployed. This reduces the cost and optimization of network can be achieved. The paper proposes the use of perfect difference set (PDS) - networks in the paradigm of WSN. In PDS - network nodes are interconnected to give minimum number of hops during communication. Any node can send data to cluster head node within a hop count of one or two. The lifetime of WSN with 50 nodes is computed for cooperative routin...

Wireless Sensor Networks(WSN) are battery powered. Hence every aspect of WSN is to be designed wi... more Wireless Sensor Networks(WSN) are battery powered. Hence every aspect of WSN is to be designed with energy constrain. Communication is the largest consumer of energy in WSN. Hence energy consumption during communication must be reduced to the minimum possible. This paper focuses on reduced energy consumption on communication. Classification techniques are used to classify sensor data to reduce communication cost. Cooperative routing is used to communicate data. The co-operative routing protocol is designed for communication in a distributed environment. In a distributed environment, the data routing takes place in multiple hops and all the nodes take part in communication. This protocol has been designed for wireless sensor networks. The main objective is to achieve a uniform dissipation of energy for all the nodes in the whole network. The paper discusses classification technique using ART1 and Fuzzy ART neural network models. The classified sensor data is communicated further usin...

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006

Thermal distribution has become an important reliability concern for today's integrated c... more Thermal distribution has become an important reliability concern for today's integrated circuits. In traditional design flows, the temperature of the chip is assumed to be uniform across the substrate. However, non-uniform thermal distribution can be a major source of inaccuracy in delay and clock skew computations, and can have an impact on electro-migration reliability and self-heating effects. Hence, it has

Multimedia Tools and Applications, 2015

ABSTRACT

Lecture Notes in Electrical Engineering, 2008

Page 1. Chapter 4 Classification Techniques Using Neural Networks and Clustering Architecture for... more Page 1. Chapter 4 Classification Techniques Using Neural Networks and Clustering Architecture for Wireless Sensor Networks Sudhir G. Akojwar and Rajendra M. Patrikar 4.1 Introduction Wireless sensor networks are becoming ...

2007 IEEE International Symposium on Industrial Electronics, 2007

ABSTRACT

Using NEGF for solving Schrödinger-Poisson equations for an ultra thin body MOSFET in Quantum- Me... more Using NEGF for solving Schrödinger-Poisson equations for an ultra thin body MOSFET in Quantum- Mechanical domain and the WKB approximation for calculating the tunneling probability, the direct tunneling current across stacked gate dielectrics has been modeled. With the trapping in scaled devices assuming serious proportions, the effect of traps on the drain current output of the device has also been

Grid computing is a means of allocating the computational power of a large number of computers to... more Grid computing is a means of allocating the computational power of a large number of computers to complex difficult computation or problem. Grid computing is a distributed computing paradigm that differs from traditional distributed computing in that it is aimed toward large scale systems that even span organizational boundaries. We propose a novel method to achieve maximum fault tolerance in

In today's new technology era, cluster has become a necessity for the modern computing and da... more In today's new technology era, cluster has become a necessity for the modern computing and data applications since many applications take more time (even days or months) for computation. Although after parallelization, computation speeds up, still time required for much application can be more. Thus, reliability of the cluster becomes very important issue and implementation of fault tolerant mechanism becomes

Summary Network-on-Chip (NoC) is a new paradigm for designing core based System-on-Chip. Network-... more Summary Network-on-Chip (NoC) is a new paradigm for designing core based System-on-Chip. Network-on-Chip has been proposed as a solution for addressing the design challenges of future high performance nanoscale architectures. Innovative system-level performance models are required for designing NoC based architectures. In this paper, we discuss the possibility of achieving the energy-aware NoC architecture based on the mathematical notion of

Microsystem Technologies, 2015

2014 8th Asia Modelling Symposium, 2014

Communications in Computer and Information Science, 2013

ABSTRACT The potential impact of fin width and graded channel doping on the analog performance of... more ABSTRACT The potential impact of fin width and graded channel doping on the analog performance of 22nm n-channel FinFET are studied using well calibrated 3D TCAD simulations. It is ascertained that for FinFETs, lesser the fin width, better the characteristics. But limitations in lithography process curb the fin width to be scaled beyond 10nm. Stability of the fins patterned beyond 10nm width is to be viewed with suspected eyes. It is observed that Graded doping of the channel will improve threshold voltage and hence the ratio of Ion to Ioff will also increase, which is desired for enhanced performance in analog applications.

The Network-on-Chip (NoC) is Network-version of Systemon-Chip (SoC) means that on-chip communicat... more The Network-on-Chip (NoC) is Network-version of Systemon-Chip (SoC) means that on-chip communication is done through packet based networks. In NOC topology, routing algorithm and switching are main terminology .The routing algorithm is one of the key factor in NOC architecture. The routing algorithm ,which defines as the path taken by a packet between the source and the destination .As XY routing algorithm mainly used in NOC because of its simplicity. This paper basically review of XY routing algorithm in which we study a different type of XY routing algorithm. The classification of XY routing algorithm is totally depend upon the environment and requirement. Such that IX/Y routing algorithm is for less collision in network, for deadlock-free and livelock-free DyXY is used, for fault-tolerant XYX routing algorithm is proposed and Adaptive XY routing algorithm is used for fully utilization of network resource.

In The Network on chip (NoC) is an approach to designing the communication subsystem between IP c... more In The Network on chip (NoC) is an approach to designing the communication subsystem between IP cores in System on Chip (SoC). Network on chip provides an attractive alternative solution to traditional bus based interconnection scheme. NoC architectural design has ability by which various IP cores communicate with one another through router & switching mechanism. The switching mechanism plays a vital role to move the data from an input channel and place it on an output channel. Virtual cut through (VCT) and wormhole (WH) switching techniques are widely used in NoC architecture. In this paper, virtual cut through switching technique has been proposed for Network on chip architecture and its performance is analyzed using the parameters such as latency & power.

Microelectronics Reliability

... 173–178. [2] PK Lala, Self-checking and fault-tolerant digital system design, Morgan Kauffman... more ... 173–178. [2] PK Lala, Self-checking and fault-tolerant digital system design, Morgan Kauffman Publishers, San Francisco (2001). [3] Alderighi' Monica, D'Angelol Sergio, Metra' Cecilia, Sechi Giacomo R. Novel fault-tolerant adder design for FPGA-based systems. ...

). The design is synthesized using Xilinx Virtex4 XC4VLX200 device. The functional behavior is ve... more ). The design is synthesized using Xilinx Virtex4 XC4VLX200 device. The functional behavior is verified using Modelsim XE III 6.2 C. The delay and throughput values are obtained for variable payload sizes. Throughput-Power and Delay-Power characteristics are also verified for NoC.

The emphasizes on higher data rates and spectral efficiency has driven the industry towards linea... more The emphasizes on higher data rates and spectral efficiency has driven the industry towards linear modulation techniques such as QPSK, 64 QAM, or multicarrier configurations. The result is a signal with a fluctuating envelope which generates intermodulation (IM) distortion from the power amplifiers. Since most of the IM power appears as interference in adjacent channels, it is important to use a highly linear power amplifier. This paper describes a new approach of using a Diode as a predistorter in view of minimizing non linear distortion introduced by the high power amplifier in microwave radio links. The approach is based on preventing the base-collector junction from becoming forward biased also preventing VDS > VGS-Vt in case of MOSFETs / pHEMTs. This approach has two advantages 1) It prevents the transistor to go into saturation 2) Reduces the effect of nonlinear terms generated by the active device.

In wireless sensor networks (WSN), nodes are randomly deployed. Most of all protocols in WSN are ... more In wireless sensor networks (WSN), nodes are randomly deployed. Most of all protocols in WSN are designed for its random deployment. Projective geometry can be used for the fixed-geometrical deployment of wireless sensor nodes. This strategy can be used for deploying nodes in smart houses, hotels, offices, underground mines etc. For environmental monitoring on large geographical area random deployment is used. In random deployment many redundant sensors are used which increases the cost. In fixed geometrical deployment calculated number of nodes with their exact location can be deployed. This reduces the cost and optimization of network can be achieved. The paper proposes the use of perfect difference set (PDS) - networks in the paradigm of WSN. In PDS - network nodes are interconnected to give minimum number of hops during communication. Any node can send data to cluster head node within a hop count of one or two. The lifetime of WSN with 50 nodes is computed for cooperative routin...

Wireless Sensor Networks(WSN) are battery powered. Hence every aspect of WSN is to be designed wi... more Wireless Sensor Networks(WSN) are battery powered. Hence every aspect of WSN is to be designed with energy constrain. Communication is the largest consumer of energy in WSN. Hence energy consumption during communication must be reduced to the minimum possible. This paper focuses on reduced energy consumption on communication. Classification techniques are used to classify sensor data to reduce communication cost. Cooperative routing is used to communicate data. The co-operative routing protocol is designed for communication in a distributed environment. In a distributed environment, the data routing takes place in multiple hops and all the nodes take part in communication. This protocol has been designed for wireless sensor networks. The main objective is to achieve a uniform dissipation of energy for all the nodes in the whole network. The paper discusses classification technique using ART1 and Fuzzy ART neural network models. The classified sensor data is communicated further usin...

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006

Thermal distribution has become an important reliability concern for today's integrated c... more Thermal distribution has become an important reliability concern for today's integrated circuits. In traditional design flows, the temperature of the chip is assumed to be uniform across the substrate. However, non-uniform thermal distribution can be a major source of inaccuracy in delay and clock skew computations, and can have an impact on electro-migration reliability and self-heating effects. Hence, it has

Multimedia Tools and Applications, 2015

ABSTRACT

Lecture Notes in Electrical Engineering, 2008

Page 1. Chapter 4 Classification Techniques Using Neural Networks and Clustering Architecture for... more Page 1. Chapter 4 Classification Techniques Using Neural Networks and Clustering Architecture for Wireless Sensor Networks Sudhir G. Akojwar and Rajendra M. Patrikar 4.1 Introduction Wireless sensor networks are becoming ...

2007 IEEE International Symposium on Industrial Electronics, 2007

ABSTRACT

Using NEGF for solving Schrödinger-Poisson equations for an ultra thin body MOSFET in Quantum- Me... more Using NEGF for solving Schrödinger-Poisson equations for an ultra thin body MOSFET in Quantum- Mechanical domain and the WKB approximation for calculating the tunneling probability, the direct tunneling current across stacked gate dielectrics has been modeled. With the trapping in scaled devices assuming serious proportions, the effect of traps on the drain current output of the device has also been

Grid computing is a means of allocating the computational power of a large number of computers to... more Grid computing is a means of allocating the computational power of a large number of computers to complex difficult computation or problem. Grid computing is a distributed computing paradigm that differs from traditional distributed computing in that it is aimed toward large scale systems that even span organizational boundaries. We propose a novel method to achieve maximum fault tolerance in

In today's new technology era, cluster has become a necessity for the modern computing and da... more In today's new technology era, cluster has become a necessity for the modern computing and data applications since many applications take more time (even days or months) for computation. Although after parallelization, computation speeds up, still time required for much application can be more. Thus, reliability of the cluster becomes very important issue and implementation of fault tolerant mechanism becomes

Summary Network-on-Chip (NoC) is a new paradigm for designing core based System-on-Chip. Network-... more Summary Network-on-Chip (NoC) is a new paradigm for designing core based System-on-Chip. Network-on-Chip has been proposed as a solution for addressing the design challenges of future high performance nanoscale architectures. Innovative system-level performance models are required for designing NoC based architectures. In this paper, we discuss the possibility of achieving the energy-aware NoC architecture based on the mathematical notion of