Chapter 6 Notes (original) (raw)

s x1 x0 | z     s | z                 x1x0 0 0  0 | 0     0 | x0              s \00 01 11 10 0 0  1 | 1     1 | x1               0| 0| 1| 1| 0|            0 1  0 | 0                          1| 0| 0| 1| 1| 0 1  1 | 1 1 0  0 | 0                           z = x1s + x0s' 1 0  1 | 0 1 1  0 | 1 1 1  1 | 1

The gate network to implement a two input mux and symbol is:

From the text example,
z = x3(x1+x2x0) = x3x1+x3x2x0
f(x3,x2,x1,0) = x3x1x0'+x3x20 = x3x11 + 0 = x3x1x0'
f(x3,x2,x1,1) = x3x1x0+x3x2x0= x3x11+x3x21 = x3x1x0+ x3x2x0
so z = x3x1x0' + x3x1x0+ x3x2x0 = x3x1x0' + x3(x1+x2)x0

This was implemented by:

The algebraic expression for a four-input multiplexer is: z = x3s1s0+ x2s1s0'+x1s1's0+x0s1's0' which would have 6 inputs and 64 rows for a truth table solution. The functional behavior for the 4-input multiplexer and modular implementation would be:

s1 s0 | Output 0 0 x0 0 1 x1 1 0 x2 1 1 x3