UltraSPARC Processors Documentation (original) (raw)

• Architecture Specifications
• Manuals
• Datasheets
• Whitepapers

Architecture Specifications

UltraSPARC Architecture 2005

• Privileged Edition
• Hyperprivileged Edition Back to top

Manuals

UltraSPARC T1 Processor Supplement to UltraSPARC Architecture 2005

• Privileged Edition
• Hyperprivileged Edition

UltraSPARC IV+ Processor

• UltraSPARC IV+ Processor User's Manual Supplement

UltraSPARC IV Processor

• UltraSPARC IV Processor User's Manual Supplement

UltraSPARC III Processor

• UltraSPARC III Processor User's Manual

UltraSPARC IIIi Processor

• UltraSPARC IIIi Processor User's Manual version 1.0

UltraSPARC IIi Processor

• UltraSPARC IIi Processor User's Manual
• UltraSPARC IIi Processor Addendum to UltraSPARC IIi Processor Manual
• UltraSPARC IIe Processor Supplement to UltraSPARC IIi Processor Manual
  • UltraSPARC IIi 550/650 Processor Addendum to UltraSPARC IIe Processor

ASICs

• Neptune (Network Interface Chip)
• Schizo Errata
• Schizo (Safari to UPA and PCI host bridge)
• GEM (First Generation PCI Gigabit Ethernet) User's Manual
• Cassini (Second Generation PCI Gigabit Ethernet) User's Manual
• Fire (JBus to PCI-Express root complex)
• Fire Errata
• Fire Delta
• Tomatillo - JIO PRM
• PCIO, PCI Input Output Controller User's Manual
• U2P UPA to PCI User's Manual
• RIC, Reset Interrupt/Clock Controller User's Manual
• XB1 User's Manual
• USC Uniprocessor System Controller User's Manual
• Advanced PCI Bridge Chip User's Manual
• VIS Instruction Set User's Manual Back to top

Datasheets

ASICs:

• DSC (Dual Processor System Controller)
• FEPS (Fast Ethernet, Parallel port)
• PCIO (Multifunction PCI Bus Device)
• RIC (Reset, Interrupt and Clock Controller)
• U2P (UPA to PCI Adapter Bus)
• USC (Uniprocessor System Controller)
• XB1 (UPA Data to Cross Bar Switch)
• APB (Advanced PCI Bridge)

Modules:

• UltraSPARC II 400 MHz 2MB CPU Module
• UltraSPARC II 400 MHz 4MB CPU Module
• UltraSPARC II 480 MHz 8MB CPU Module Back to top

White Papers

• The UltraSPARC T1 Processor - High Bandwidth For Throughput Computing
  December 2005
• The UltraSPARC T1 Processor - Reliability, Availability, and Serviceability
  December 2005
• Power Savings in the UltraSPARC T1 Processor
  December 2005
• The UltraSPARC T1 Processor - Power Efficient Throughput Computing
  December 2005
• UltraSPARC IV Processor Architecture Overview
  February 2004
  An overview of Sun's UltraSPARC IV processor.
• Introduction to Throughput Computing
  February 2003
  An overview of Sun's Revolutionary UltraSPARC processor strategy for driving down the cost and complexity of network computing.
• An Overview of the UltraSPARC III Cu processor
  June 2002
  Important new technology in the UltraSPARC III Cu processor, specifically as it serves to maintain compatibility, increase scalability, accelerate performance, and improve RAS (Reliability, Availability and Serviceability) in SPARC-based systems designed for enterprise network computing. (24 pages)
• UltraSPARC IIIi Architecture Overview
  April 2004
  Overview of the important new technology of the UltraSPARC IIIi processor.
• JBus Architecture Overview
  April 2003
  Overview of the JBus architecture.
• The VIS Instruction Set
  June 2002 An overview of the VIS Instruction Set, the UltraSPARC[R] processor single instruction multiple data (SIMD) implementation designed to accelerate processes where multiple data can be processed in parallel. (34 pages)
• Interval Arithmetic in High performance Technical Computing
  September 2002
  Interval Arithmetic is a computing system that makes it possible to: automatically perform rigorous error analysis by computing mathematical bounds on the set of all possible problem solutions, and solve nonlinear problems that were previously thought to be impossible to solve. Sun Microsystems, Inc. is one of the few computer companies to currently offer both language and hardware support for computing with intervals. (22 pages)

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