An Open Source Processor used in Sun SPARC Servers (original) (raw)
CMT Related Books Webcast: All About OpenSPARC The All About OpenSPARC Slidecast are 12 modules of on-line training by designers, developers, and programmers who worked on the creation of the UltraSPARC T1 and T2 microprocessors. These are made available to guide users as they develop their own OpenSPARC designs and to assist professors as they teach the next generation of processor designers. CMT Whitepaper
HOTCHIPS21: Sun's Next-Generation Multi-threaded Processor - Rainbow Falls Abstract: Presentation made at the HOT CHIPS 21, on August 23-25, 2009, Stanford, CA. Authors: Sanjay Patel, Stephen Phillips and Allan Strong Presentation: 'Sun's Next-Generation Multi-threaded Processor - Rainbow Falls' HOTCHIPS21: Sun's 3rd generation on-chip UltraSPARC security accelerator Abstract: Presentation made at the HOT CHIPS 21, on August 23-25, 2009, Stanford, CA. **Author:**Lawrence Spracklen Presentation: 'Sun's 3rd generation on-chip UltraSPARC security accelerator ' OpenSPARC T2 HW 1.3 Released UltraSPARC T2 - Click to enlarge The OpenSPARC T2 processor is based on the UltraSPARC T2 processor, the world's fastest commodity processor with eight cores and eight threads per core. In HW release 1.3, a fully synthesizable, reduced footprint, System-level model has been developed, suitable for FPGA and Emulation Platforms. This model has single OpenSPARC T2 core, crossbar interconnect, and WISHBONE Memory Controller ( from www.opencores.org). This environment supports RTL Simulation, FPGA Synthesis and Gate-level simulation with a one-to-one correspondence (i.e a given test runs unchanged in the RTL & Gate environments.) This environment is hardware platform neutral and can be ported on any FPGA prototyping board. The software tools portion of the download is at release 1.2. Read more for new features in HW release 1.3 and SW release 1.2 **Download HW 1.3 and SW Release 1.2**and OpenSPARC T2 specifications Synthesizing OpenSPARC design using Synopsys 90nm Technology Library This course is created by Synopsys Inc. and is made available from the Synopsys University Program. This package includes design, documentation, and scripts to synthesize OpenSPARC T1 Floating-Point Unit (FPU) using Synopsys Inc, Electronic Design Automation (EDA) tools. Primary goal of this package is to provide students sand-box environment within which they can learn and apply logic synthesis concepts on a real world design example. This lab requires the following software and libraries: Synopsys Design Compiler version B-2008.09 or later Synopsys 90nm generic library OpenSPARC T1 version 1.6 or later Synopsys supported Compute Platform OpenSPARC T1 HW 1.7 Released New Features in the HW Release 1.7 of OpenSPARC T1 More Xilinx FPGA support for Virtex 5 FPGAs Support for a dual-core system using two OpenSPARC development boards Support for Ubuntu Linux boot Support for BEE3 Improved CCX Firmware code Improved performance when running regressions of diagnostic tests For details read more...Download HW 1.7 and SW 1.5 and OpenSPARC T1 Specfications Nangate 45nm Open Cell Library supports OpenSPARC **Nangate and Sun Microsystems, Inc. are delighted to announce the interoperability of industry leading open-source 64-bit Chip Multi-threading (CMT) microprocessor design by Sun with Nangate's 45nm Open Cell Library. Users can now synthesize and optimize state-of-the-art OpenSPARC T1 and OpenSPARC T2 design blocks, using industry standard synthesis tools, on a 45nm technology supplied by Nangate. We believe this combination will facilitate research and experimentation in modern VLSI design topics like timing and noise, reliability, and process variation among other things. We also believe the open-source nature of these two offerings will allow researchers to modify and test new ideas in a consistent and reproducible manner. Read more... European Universities Join OpenSPARC Sun Microsystems, Inc. and Europractice today announced a three-year collaboration to promote OpenSPARC CMT (Chip Multithreading) technology -- one of the only open sourced multi-core, multithreaded processor architectures--as a reference design among 650 universities and research institutions across 38 countries in the European region. Europractice is a European Union-backed non-profit microelectronics design stimulation project managed by the STFC Rutherford Appleton Laboratory. Sun and Xilinx Unveil FPGA Board At the International Conference for Field Programmable Logic and Applications today, Sun Microsystems, Inc. and Xilinx, Inc. unveiled a feature-rich, high-performance programmable OpenSPARC evaluation platform. The platform provides academic researchers and hardware developers with a flexible OpenSPARC-based platform to create, customize and deploy next-generation applications for a broad set of end markets including supercomputers, industrial, scientific and medical (ISM), aerospace & defense, and storage and networking. "Our collaboration with industry leaders such as Xilinx will continue to drive the momentum and expansion of the UltraSPARC ecosystem," said Mike Knudsen, vice president, business development and marketing for Sun's Microelectronics unit. "The microprocessor industry is steadily shifting towards CMT architectures, and this new OpenSPARC FPGA evaluation platform puts us in a prime position to enable faster time-to-market for our customers." OpenSPARC Centers of Excellence Ten major universities are now official OpenSPARC Technology Centers of Excellence: University of California, Santa Cruz, USA University of Texas, Austin, USA University of Michigan, Ann Arbor University of Illinois, Urbana-Champaign, USA Carnegie Mellon University, USA Stanford University, USA University of Otago, Dunedin, New Zealand Peking University, China Tsinghua University, China University of Sao Paulo, Brazil Each Center of Excellence has a minimum two-year commitment, during which time they'll execute chip design research and course work based on Sun's chip multi-threading (CMT) design. Visit our Centers of Excellence web page. OpenSPARC Course Material Collaborate and share course material related to OpenSPARC, chip multi-threading, multi-core in many areas including hardware design, design tools, CMT Architecture, software systems design, operating systems, concurrent computing and other related areas. We're looking for professors who have a passion for teaching and contributing to their field of study by sharing their course material with others. Take a look at site we are developing and the course materials already available: http://wiki.opensparc.net/bin/view.pl/CourseMaterial. We thankful for the support and generosity of professors who choose to share their research, pedagogy, and knowledge to benefit others. What's New OpenSPARC T2 HW 1.3 Released UltraSPARC T2 - Click to enlarge The OpenSPARC T2 processor is based on the UltraSPARC T2 processor, the world's fastest commodity processor with eight cores and eight threads per core. In... Read more... OpenSPARC T1 HW 1.7 Released New Features in the HW Release 1.7 of OpenSPARC T1 More Xilinx FPGA support for Virtex 5 FPGAs Support for a dual-core system using two OpenSPARC development boards Support for ... Read more... OpenSPARC T2 SW 1.2 Released UltraSPARC T2 - Click to enlarge The OpenSPARC T2 processor is based on the UltraSPARC T2 processor, the world's fastest commodity processor with eight cores and eight threads per core. Th... Read more... Free Introductory Workshop - Brussels, Belgium EUROPRACTICE Software Service and Sun Microsystems, Inc. Invite you to the OpenSPARC Free Introductory Workshop Brussels, Belgium on April 23rd and 24th Find out more... ... Read more... The OpenBSD 4.4 Release Much more platform support. Machines using the UltraSPARC IV/T1/T2 and Fujitsu SPARC64-V/VI/VII are now supported. Read the original article: http://openbsd.org/44.html ... Read more... Latest News SPARC processor delivers 90 MIPS @100MHz Atmel Corp. has developed a new processor designed for the extreme conditions of space applications. The AT697F radiation-hardened SPARC processor delivers 90 MIPs at 100MHz over full temperature a... Read more... Sun And Fujitsu Boost SPARC Enterprise Server Performance And Virtualization Capabilities CMT Servers with New 1.6GHz UltraSPARC T2/T2 Plus Processors Set World Records on Enterprise Benchmarks; Enhanced Logical Domains Software Leverages the Solaris Operating System to Help Increase Da... Read more... The Register: Sun cranks clocks on Sparc T2 and T2+ The executives at server and operating system maker Sun Microsystems have been uncharacteristically quiet since the $5.6bn Oracle deal was announced back in April. And they've been silent since Sun's... Read more... EE Times: CPUs gear up for--and some avoid--Hot Chips The preliminary program for the annual Hot Chips conference says a lot about the state of the microprocessor industry both for what's on it, and for what's not. All the top server CPU vendors--Adv... Read more... New York Times: Sun Is Said to Cancel Big Chip Project Sun Microsystems may have dropped a bit of weight by the time Oracle officially acquires the company. According to two people briefed on Sun’s plans, the company has canceled its Rock chip project... Read more... Latest Blogs Octave Orgeron: Fujitsu Out-Sourcing to TSMC Well according to reports, Fujitsu is divesting itself of semi-conductor fabrication and out-sourcing it to TSMC. This is not as surprising if you consider the amount of consolidation in the technol... Read more... Durgam Vahia: Announcing OpenSPARC V1.7 We are delighted to announce the availability of OpenSPARC T1 version 1.7. With this release, community can port a truly multi-core multi-thread 64bit commercial processor design on FPGAs. Additionall... Read more... Aditya: monitoring core/vcpu usage on Sun CMT machines Sun Sun provides the /usr/local/bin/corestat CLI tool for their CMT (T1 and T2 Ultrasparc) machines which outputs in a loop with a line per core, however the output isn't suitable for long-term monitor... Read more... Durgam Vahia: OpenSPARC Center of Excellence - University of Sao Paulo, Brazil We are delighted to announce that University of Sao Paulo, Brazil is now the first OpenSPARC Center of Excellence in the Latin America. USP is one of the largest institutions of higher education in Br... Read more... Paul Murphy: P570 vs T5220 As part of JesperFrimann’s challenge with respect to the options available to a company with two aging p690s running Sybase, he suggested that: It’s 256 threads per box on the T5440 versus 1... Read more...
UltraSPARC T2 - Click to enlarge The OpenSPARC T2 processor is based on the UltraSPARC T2 processor, the world's fastest commodity processor with eight cores and eight threads per core. In HW release 1.3, a fully synthesizable, reduced footprint, System-level model has been developed, suitable for FPGA and Emulation Platforms. This model has single OpenSPARC T2 core, crossbar interconnect, and WISHBONE Memory Controller ( from www.opencores.org). This environment supports RTL Simulation, FPGA Synthesis and Gate-level simulation with a one-to-one correspondence (i.e a given test runs unchanged in the RTL & Gate environments.) This environment is hardware platform neutral and can be ported on any FPGA prototyping board. The software tools portion of the download is at release 1.2. Read more for new features in HW release 1.3 and SW release 1.2 **Download HW 1.3 and SW Release 1.2**and OpenSPARC T2 specifications Synthesizing OpenSPARC design using Synopsys 90nm Technology Library This course is created by Synopsys Inc. and is made available from the Synopsys University Program. This package includes design, documentation, and scripts to synthesize OpenSPARC T1 Floating-Point Unit (FPU) using Synopsys Inc, Electronic Design Automation (EDA) tools. Primary goal of this package is to provide students sand-box environment within which they can learn and apply logic synthesis concepts on a real world design example. This lab requires the following software and libraries: Synopsys Design Compiler version B-2008.09 or later Synopsys 90nm generic library OpenSPARC T1 version 1.6 or later Synopsys supported Compute Platform OpenSPARC T1 HW 1.7 Released New Features in the HW Release 1.7 of OpenSPARC T1 More Xilinx FPGA support for Virtex 5 FPGAs Support for a dual-core system using two OpenSPARC development boards Support for Ubuntu Linux boot Support for BEE3 Improved CCX Firmware code Improved performance when running regressions of diagnostic tests For details read more... Download HW 1.7 and SW 1.5 and OpenSPARC T1 Specfications Nangate 45nm Open Cell Library supports OpenSPARC **Nangate and Sun Microsystems, Inc. are delighted to announce the interoperability of industry leading open-source 64-bit Chip Multi-threading (CMT) microprocessor design by Sun with Nangate's 45nm Open Cell Library. Users can now synthesize and optimize state-of-the-art OpenSPARC T1 and OpenSPARC T2 design blocks, using industry standard synthesis tools, on a 45nm technology supplied by Nangate. We believe this combination will facilitate research and experimentation in modern VLSI design topics like timing and noise, reliability, and process variation among other things. We also believe the open-source nature of these two offerings will allow researchers to modify and test new ideas in a consistent and reproducible manner. Read more... European Universities Join OpenSPARC 
Sun Microsystems, Inc. and Europractice today announced a three-year collaboration to promote OpenSPARC CMT (Chip Multithreading) technology -- one of the only open sourced multi-core, multithreaded processor architectures--as a reference design among 650 universities and research institutions across 38 countries in the European region. Europractice is a European Union-backed non-profit microelectronics design stimulation project managed by the STFC Rutherford Appleton Laboratory. Sun and Xilinx Unveil FPGA Board 
At the International Conference for Field Programmable Logic and Applications today, Sun Microsystems, Inc. and Xilinx, Inc. unveiled a feature-rich, high-performance programmable OpenSPARC evaluation platform. The platform provides academic researchers and hardware developers with a flexible OpenSPARC-based platform to create, customize and deploy next-generation applications for a broad set of end markets including supercomputers, industrial, scientific and medical (ISM), aerospace & defense, and storage and networking. "Our collaboration with industry leaders such as Xilinx will continue to drive the momentum and expansion of the UltraSPARC ecosystem," said Mike Knudsen, vice president, business development and marketing for Sun's Microelectronics unit. "The microprocessor industry is steadily shifting towards CMT architectures, and this new OpenSPARC FPGA evaluation platform puts us in a prime position to enable faster time-to-market for our customers." OpenSPARC Centers of Excellence Ten major universities are now official OpenSPARC Technology Centers of Excellence: University of California, Santa Cruz, USA University of Texas, Austin, USA University of Michigan, Ann Arbor University of Illinois, Urbana-Champaign, USA Carnegie Mellon University, USA Stanford University, USA University of Otago, Dunedin, New Zealand Peking University, China Tsinghua University, China University of Sao Paulo, Brazil Each Center of Excellence has a minimum two-year commitment, during which time they'll execute chip design research and course work based on Sun's chip multi-threading (CMT) design. Visit our Centers of Excellence web page. OpenSPARC Course Material Collaborate and share course material related to OpenSPARC, chip multi-threading, multi-core in many areas including hardware design, design tools, CMT Architecture, software systems design, operating systems, concurrent computing and other related areas. We're looking for professors who have a passion for teaching and contributing to their field of study by sharing their course material with others. Take a look at site we are developing and the course materials already available: http://wiki.opensparc.net/bin/view.pl/CourseMaterial. We thankful for the support and generosity of professors who choose to share their research, pedagogy, and knowledge to benefit others. What's New OpenSPARC T2 HW 1.3 Released UltraSPARC T2 - Click to enlarge The OpenSPARC T2 processor is based on the UltraSPARC T2 processor, the world's fastest commodity processor with eight cores and eight threads per core. In... Read more... OpenSPARC T1 HW 1.7 Released New Features in the HW Release 1.7 of OpenSPARC T1 More Xilinx FPGA support for Virtex 5 FPGAs Support for a dual-core system using two OpenSPARC development boards Support for ... Read more... OpenSPARC T2 SW 1.2 Released UltraSPARC T2 - Click to enlarge The OpenSPARC T2 processor is based on the UltraSPARC T2 processor, the world's fastest commodity processor with eight cores and eight threads per core. Th... Read more... Free Introductory Workshop - Brussels, Belgium EUROPRACTICE Software Service and Sun Microsystems, Inc. Invite you to the OpenSPARC Free Introductory Workshop Brussels, Belgium on April 23rd and 24th Find out more... ... Read more... The OpenBSD 4.4 Release Much more platform support. Machines using the UltraSPARC IV/T1/T2 and Fujitsu SPARC64-V/VI/VII are now supported. Read the original article: http://openbsd.org/44.html ... Read more... Latest News SPARC processor delivers 90 MIPS @100MHz Atmel Corp. has developed a new processor designed for the extreme conditions of space applications. The AT697F radiation-hardened SPARC processor delivers 90 MIPs at 100MHz over full temperature a... Read more... Sun And Fujitsu Boost SPARC Enterprise Server Performance And Virtualization Capabilities CMT Servers with New 1.6GHz UltraSPARC T2/T2 Plus Processors Set World Records on Enterprise Benchmarks; Enhanced Logical Domains Software Leverages the Solaris Operating System to Help Increase Da... Read more... The Register: Sun cranks clocks on Sparc T2 and T2+ The executives at server and operating system maker Sun Microsystems have been uncharacteristically quiet since the $5.6bn Oracle deal was announced back in April. And they've been silent since Sun's... Read more... EE Times: CPUs gear up for--and some avoid--Hot Chips The preliminary program for the annual Hot Chips conference says a lot about the state of the microprocessor industry both for what's on it, and for what's not. All the top server CPU vendors--Adv... Read more... New York Times: Sun Is Said to Cancel Big Chip Project Sun Microsystems may have dropped a bit of weight by the time Oracle officially acquires the company. According to two people briefed on Sun’s plans, the company has canceled its Rock chip project... Read more... Latest Blogs Octave Orgeron: Fujitsu Out-Sourcing to TSMC Well according to reports, Fujitsu is divesting itself of semi-conductor fabrication and out-sourcing it to TSMC. This is not as surprising if you consider the amount of consolidation in the technol... Read more... Durgam Vahia: Announcing OpenSPARC V1.7 We are delighted to announce the availability of OpenSPARC T1 version 1.7. With this release, community can port a truly multi-core multi-thread 64bit commercial processor design on FPGAs. Additionall... Read more... Aditya: monitoring core/vcpu usage on Sun CMT machines Sun Sun provides the /usr/local/bin/corestat CLI tool for their CMT (T1 and T2 Ultrasparc) machines which outputs in a loop with a line per core, however the output isn't suitable for long-term monitor... Read more... Durgam Vahia: OpenSPARC Center of Excellence - University of Sao Paulo, Brazil We are delighted to announce that University of Sao Paulo, Brazil is now the first OpenSPARC Center of Excellence in the Latin America. USP is one of the largest institutions of higher education in Br... Read more... Paul Murphy: P570 vs T5220 As part of JesperFrimann’s challenge with respect to the options available to a company with two aging p690s running Sybase, he suggested that: It’s 256 threads per box on the T5440 versus 1... Read more...