Yves Durand | Commissariat à l'Energie Atomique (CEA) (original) (raw)
Papers by Yves Durand
2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019
The popularity and community-driven development model of RISC-V have opened many areas of investi... more The popularity and community-driven development model of RISC-V have opened many areas of investigation to researchers and engineers. To overcome some of the IEEE 754 standard's limitations, one currently emerging avenue for computer architecture and systems research is the area of alternative floating-point computation. The UNUM format, for instance, offers variable precision and much flexibility useful to scientific computing or computational geometry. Programmers usually rely on arbitrary precision libraries such as MPFR (itself depending on GMP). However, there is currently no specialized RISC-V support for these libraries, and little support for variable precision arithmetic across the tool chain in general. We propose a framework to explore the potential of variable precision arithmetic in scientific computing applications on RISC-V processors. This work comprises: (i) a floating-point RISC-V copro-cessor which improve accuracy using the UNUM format; (ii) an ISA extension ...
Proceedings of the Conference for Next Generation Arithmetic 2019, 2019
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, Mar 1, 2017
A very large internal accumulation register has been proposed to increase the accuracy of scienti... more A very large internal accumulation register has been proposed to increase the accuracy of scientific code. However, there is a general class of iterative kernels where a vector of high-precision data must be saved from one iteration to the next. Saving the large internal accumulator to memory is impractical in such cases. This work proposes a Variable Precision (VP) Floating Point (FP) arithmetic co-processor architecture based on RISC-V, which 1/ supports legacy IEEE formats for input and output variables, 2/ uses variable length internal registers (up to 512 bits of mantissa) for inner loop multiply-add and 3/ supports loads and stores of intermediate results to cache memory with a dynamically adjustable precision (up to 256 bits of mantissa). It exploits the UNUM type I floating point format, proposing solutions to address some of its pitfalls such as the variable latency of the internal operation, and the variable memory footprint of the intermediate variables. This work is inte...
EURASIP Journal on Wireless Communications and Networking
5G systems and networks are expected to provide unprecedented data-rate to final users and servic... more 5G systems and networks are expected to provide unprecedented data-rate to final users and services, in combination with increased coverage and density. The traffic generated at the edges of the network should be hauled through high capacity data-conveyors. Extremely high data-rate links able to provide optical-fiber like performance in the order of 100 Gbps are required to reduce the cost and increase the flexibility of the network infrastructure deployment. This paper presents a full transceiver architecture based on a channel-bonding radio-frequency front-end operating at millimeter-wave frequencies and digital baseband processing units able to provide such data-rates with a feasible implementation in low-cost CMOS technologies. The baseband section of the receiver includes digital compensation algorithms that allow to cope with some of the radio front-end impairments. The main functionalities of the proposed transceiver architecture are validated in hardware.
Proceedings of the 2014 International Workshop, Dec 13, 2014
Lecture Notes in Computer Science, 2006
Considering the complexity of the future 4G telecommunication systems, power consumption manageme... more Considering the complexity of the future 4G telecommunication systems, power consumption management becomes a major challenge for the designers, particularly for base-band modem functionalities. System level low-power policies which optimize dynamically the consumption, achieve major power savings compared to low level optimisations (e.g gated clock or transistor optimisation). We present an innovative power modeling methodology of a 4G modem which
2009 IEEE International Symposium on Parallel & Distributed Processing, 2009
... des Arts, 69621 Villeurbanne Cedex, France {riadh.ben-abdallah, tanguy.risset, antoine.frabou... more ... des Arts, 69621 Villeurbanne Cedex, France {riadh.ben-abdallah, tanguy.risset, antoine.fraboulet}@insa-lyon.fr ... 2005. IEEE Computer Society. [6] J. Eker, JW Janneck, EA Lee, J. Liu, X. Liu, J. Lud-vig, S. Neuendorffer, S. Sachs, and Y. Xiong. ...
2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019
The popularity and community-driven development model of RISC-V have opened many areas of investi... more The popularity and community-driven development model of RISC-V have opened many areas of investigation to researchers and engineers. To overcome some of the IEEE 754 standard's limitations, one currently emerging avenue for computer architecture and systems research is the area of alternative floating-point computation. The UNUM format, for instance, offers variable precision and much flexibility useful to scientific computing or computational geometry. Programmers usually rely on arbitrary precision libraries such as MPFR (itself depending on GMP). However, there is currently no specialized RISC-V support for these libraries, and little support for variable precision arithmetic across the tool chain in general. We propose a framework to explore the potential of variable precision arithmetic in scientific computing applications on RISC-V processors. This work comprises: (i) a floating-point RISC-V copro-cessor which improve accuracy using the UNUM format; (ii) an ISA extension ...
Proceedings of the Conference for Next Generation Arithmetic 2019, 2019
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, Mar 1, 2017
A very large internal accumulation register has been proposed to increase the accuracy of scienti... more A very large internal accumulation register has been proposed to increase the accuracy of scientific code. However, there is a general class of iterative kernels where a vector of high-precision data must be saved from one iteration to the next. Saving the large internal accumulator to memory is impractical in such cases. This work proposes a Variable Precision (VP) Floating Point (FP) arithmetic co-processor architecture based on RISC-V, which 1/ supports legacy IEEE formats for input and output variables, 2/ uses variable length internal registers (up to 512 bits of mantissa) for inner loop multiply-add and 3/ supports loads and stores of intermediate results to cache memory with a dynamically adjustable precision (up to 256 bits of mantissa). It exploits the UNUM type I floating point format, proposing solutions to address some of its pitfalls such as the variable latency of the internal operation, and the variable memory footprint of the intermediate variables. This work is inte...
EURASIP Journal on Wireless Communications and Networking
5G systems and networks are expected to provide unprecedented data-rate to final users and servic... more 5G systems and networks are expected to provide unprecedented data-rate to final users and services, in combination with increased coverage and density. The traffic generated at the edges of the network should be hauled through high capacity data-conveyors. Extremely high data-rate links able to provide optical-fiber like performance in the order of 100 Gbps are required to reduce the cost and increase the flexibility of the network infrastructure deployment. This paper presents a full transceiver architecture based on a channel-bonding radio-frequency front-end operating at millimeter-wave frequencies and digital baseband processing units able to provide such data-rates with a feasible implementation in low-cost CMOS technologies. The baseband section of the receiver includes digital compensation algorithms that allow to cope with some of the radio front-end impairments. The main functionalities of the proposed transceiver architecture are validated in hardware.
Proceedings of the 2014 International Workshop, Dec 13, 2014
Lecture Notes in Computer Science, 2006
Considering the complexity of the future 4G telecommunication systems, power consumption manageme... more Considering the complexity of the future 4G telecommunication systems, power consumption management becomes a major challenge for the designers, particularly for base-band modem functionalities. System level low-power policies which optimize dynamically the consumption, achieve major power savings compared to low level optimisations (e.g gated clock or transistor optimisation). We present an innovative power modeling methodology of a 4G modem which
2009 IEEE International Symposium on Parallel & Distributed Processing, 2009
... des Arts, 69621 Villeurbanne Cedex, France {riadh.ben-abdallah, tanguy.risset, antoine.frabou... more ... des Arts, 69621 Villeurbanne Cedex, France {riadh.ben-abdallah, tanguy.risset, antoine.fraboulet}@insa-lyon.fr ... 2005. IEEE Computer Society. [6] J. Eker, JW Janneck, EA Lee, J. Liu, X. Liu, J. Lud-vig, S. Neuendorffer, S. Sachs, and Y. Xiong. ...