Layers for High-Performance Nanoscale (original) (raw)

Over the past several years, the inherent scaling limitations of silicon (Si) electron devices have fuelled the exploration of alternative semiconductors, with high carrier mobility, to further enhance device performance 1-8. In particular, compound semiconductors heterogeneously integrated on Si substrates have been actively studied 7,9,10 : such devices combine the high mobility of III-V semiconductors and the well established, low-cost processing of Si technology. This integration, however, presents significant challenges. Conventionally, heteroepitaxial growth of complex multilayers on Si has been explored 9,11-13-but besides complexity, high defect densities and junction leakage currents present limitations in this approach. Motivated by this challenge, here we use an epitaxial transfer method for the integration of ultrathin layers of single-crystal InAs on Si/ SiO 2 substrates. As a parallel with silicon-on-insulator (SOI) technology 14 , we use 'XOI' to represent our compound semiconductoron-insulator platform. Through experiments and simulation, the electrical properties of InAs XOI transistors are explored, elucidating the critical role of quantum confinement in the transport properties of ultrathin XOI layers. Importantly, a high-quality InAs/ dielectric interface is obtained by the use of a novel thermally grown interfacial InAsO x layer (1 nm thick). The fabricated field-effect transistors exhibit a peak transconductance of 1.6 mS mm 21 at a drain-source voltage of 0.5 V, with an on/off current ratio of greater than 10,000. Epitaxial lift-off and transfer of crystalline microstructures to various support substrates has been shown to be a versatile technique for applications ranging from optoelectronics to large-area electronics 15-18. Specifically, high-performance, mechanically flexible macro-electronics and photovoltaics have been demonstrated on plastic, rubber and glass substrates by this method 19-21. Here we use a modified epitaxial transfer scheme for integrating ultrathin InAs layers (with nanometre-scale thicknesses) on Si/SiO 2 substrates for use as high-performance nanoscale transistors. These InAs layers are fully depleted, which is an important criterion for achieving high-performance field-effect transistors (FETs) with respectable 'off' currents based on small bandgap semiconductors. The transfer is achieved without the use of adhesive layers, thereby allowing the use of purely inorganic interfaces with low interface trap densities and high stability. Figure 1a shows a diagram of the fabrication process for InAs XOI substrates (see Methods for details). We used atomic force microscopy (AFM) to characterize the surface morphology and uniformity of the fabricated XOI substrates. Figure 1b and c shows representative AFM images of an array of InAs nanoribbons (,18 nm thick) on a Si/SiO 2 substrate, clearly depicting the smooth surfaces (,1 nm surface roughness) and high uniformity of the enabled structures over large areas. Uniquely, the process readily enables the heterogeneous integration of different III-V materials and structures on a single substrate through a multi-step epitaxial transfer process. To demonstrate this capability, a two-step transfer process was used to form ordered arrays of 18-and 48-nm-thick InAs nanoribbons that are perpendicularly oriented on the surface of a Si/SiO 2 substrate (Fig. 1d, e). This result demonstrates the potential capacity of the proposed XOI technology for generic heterogeneous and/or hierarchical assembly of crystalline semiconducting materials. In the future, a similar scheme may be used to enable the fabrication of both p-and n-type transistors on the same chip for complementary electronics based on the optimal III-V semiconductors.