Reviews on Algorithms and Architectures for Efficient Design of MIMO Accelerator (original) (raw)

Performance Analysis of Low Power MIMO Decoding Accelerator using Euclidean Orthogonal Architecture

This paper proposes the MIMO Decoder Accelerator which targets multiple-input-multiple output (MIMO) decoding tasks of orthogonal frequency-division multiplexing (OFDM) systems. The MIMO Decoding Accelerator is designed using a Way Tag Detection Unit to reduce the power consumption. The MIMO accelerator is a software-programmable device that specializes in MIMO decoding and MIMO signal processing for OFDM systems. The main objective of the proposed design of MIMO decoder accelerator is to reduce the power consumption in multichannel environment. The Way Tag Detection unit is designed instead of FSM controller. It is used to enable the clock signal. The performance analysis is done between the conventional design, QR Decomposition method and proposed method. The Power Consumption of the proposed MIMO Decoding Accelerator was measured to be 267 mW at a clock frequency of 100-MHz clock frequency off of a 1-V supply. When compared to the conventional method the power consumption is reduced by 10% in the proposed MIMO Decoding Accelerator.

Energy Efficient Programmable MIMO Decoder Accelerator Chip in 65-nm CMOS

This paper presents an energy efficient programmable hardware accelerator that targets multiple-input-multipleoutput (MIMO) decoding tasks of orthogonal frequency-division multiplexing (OFDM) systems. The work is motivated by the adoption of MIMO and OFDM by almost all existing and emerging high-speed wireless data communication systems. The accelerator was fabricated in 65-nm CMOS technology and occupies a core area of 2.48 mm 2 . It delivers full programmability across different wireless standards (i.e., WiFi, 3G-long term evolution, and WiMax) as well as different MIMO decoding algorithms (i.e., minimum mean square error, singular value decomposition, and maximum likelihood) with extreme energy efficiency. The energy efficiency of our MIMO accelerator chip was compared against dedicated application specific integrated circuits for 4 × 4 QR decomposition, 4 × 4 singular value decomposition, and 2 × 2 minimum mean square error decoding. Despite the programmable nature of our design, it delivered energy efficiencies that were 18% to 28% better than the dedicated solutions reported in the literature. This paper presents the VLSI implementation of the architecture discussed in [14]- . It discusses the implementation decisions and tradeoffs used to ensure minimum overall energy consumption of the resulting accelerator chip without sacrificing programmability. Given its programmability and extreme energy efficiency, the accelerator is an ideal solution for today's smart phones that implement multiple MIMO-OFDM waveforms on the same platform.

Theoretical Design of Mimo Transceiver and Implementation Its Transmitter Using Fpga

Diyala Journal of Engineering Sciences, 2014

The use of multiple transmit and receive antennas (MIMO system) is widely accepted in recent years, as a promising technology for future wireless communication, to achieve higher data rates independently of transmission power and bandwidth, with improve system reliability through increasing diversity. This research presents the design and implementation of a multiple antenna wireless communications system using Xilinx Field Programmable Gate Array (FPGA) .The proposed design based on Alamouti’s transmit diversity scheme which is a space-time block code (STBC) with two transmit antennas and an arbitrary number of receive antennas. The implementation demonstrates the space-time code in a baseband system with two antennas for transmitter and receiver. The encoding and decoding algorithms are implemented using VHDL, Spartan 3A /3AN is used to implement transmitter part, where the Virtex2P is used to complete the receiver part design theoretically. Finally the design MIMO systems are imp...

A Real-Time FPGA-Based Implementation of a High-Performance MIMO-OFDM Mobile WiMAX Transmitter

Mobile Lightweight Wireless Systems, 2012

The Multiple Input Multiple Output (MIMO)-Orthogonal Frequency Division Multiplexing (OFDM) is considered a key technology in modern wireless-access communication systems. The IEEE 802.16e standard, also denoted as mobile WiMAX, utilizes the MIMO-OFDM technology and it was one of the first initiatives towards the roadmap of fourth generation systems. This paper presents the PHY-layer design, implementation and validation of a high-performance real-time 2x2 MIMO mobile WiMAX transmitter that accounts for low-level deployment issues and signal impairments. The focus is mainly laid on the impact of the selected high bandwidth, which scales the implementation complexity of the baseband signal processing algorithms. The latter also requires an advanced pipelined memory architecture to timely address the datapath operations that involve high memory utilization. We present in this paper a first evaluation of the extracted results that demonstrate the performance of the system using a 2x2 MIMO channel emulation.

Hardware Implementation of OFDM Transceiver Using Simulink Blocks for MIMO Systems

River Publishers, 2023

In wireless communication applications, the MIMO-OFDM system plays a vital role. The multiple inputs and multiple outputs components of the MIMO process were the focal points. The communication process aims to reduce energy consumption at the original transmission input signal level while also improving the effectiveness of wireless communication applications. The hardware-based VLSI architecture will be used to modify this technology. This architecture is designed to improve the performance of the transceivers in 802.11 MIMO-OFDM systems. This system uses Matlab Simulink software and a hardware FPGA board to construct a 4x4 MIMO OFDM architecture. Matlab simulation is used to convert VHDL code and verify the output for the VLSI simulation graph. To optimize the transmission timing in the MIMO architecture process, design the blocks in the Simulink unit and alter the block layout in the overall OFDM-MIMO unit, as well as build the sub-system functions. The hardware architecture for the Simulink 802.11 MIMO-OFDM system design is implemented using the system generator and Xilinx software. The design technique for optimizing the hardware program design process for MIMO encode and decode processes, as well as transceiver operations, uses VHDL code. The goal of the simulation is to organize the MIMO-OFDM blocks and increase the energy efficiency of wireless communication systems.

CELLA: FPGA Based Candidate Execution with Low Latency Approach for Soft MIMO Detector

Circuits and Systems, 2016

This paper describes the design and Field Programmable Gate Array (FPGA) based 4 × 4 breadth heuristic Multiple-Input-Multiple-Output (MIMO) decoder using 16 and 64 Quadrature Amplitude Modulation (QAM) schemes. The intention of this work is to observe the performance of Candidate Execution with Low Latency Approach for soft MIMO detector in FPGA (CELLA). The Smart Ordering and Candidate Adding (SOCA), Parallel Candidate Adding (PCA) and Backward Candidate Adding (BCA) give better performance in terms of Bit Error Rate (BER) or chip level service. In order to attain both BER and FPGA level performance in a single system, CELLA is developed in this work. Simulation and experimental results demonstrate the effectiveness of the proposed work under the system 4 × 4 MIMO-OFDM employing 16 QAM and 64 QAM. The proposed experiment is implemented in Xilinx Virtex 5 C5VSX240T. The performance results, in terms of FPGA level 76% slice reduction, 58.76% throughput improvement, 75% power reduction and 87% latency reduction, are achieved. The BER performance is observed and compared with the conventional algorithms. Thus, the proposed work achieves better outcome than the conventional work.

Design and Implementation of a Hardware Module for MIMO Decoding in a 4G Wireless Receiver

VLSI Design, 2008

Future 4th Generation (4G) wireless multiuser communication systems will have to provide advanced multimedia services to an increasing number of users, making good use of the scarce spectrum resources. Thus, 4G system design should pursue both higher-transmission bit rates and higher spectral efficiencies. To achieve this goal, multiple antenna systems are called to play a crucial role. In this contribution we address the implementation in FPGAs of a multiple-input multiple-output (MIMO) decoder embedded in a prototype of a 4G mobile receiver. This MIMO decoder is part of a multicarrier code-division multiple-access (MC-CDMA) radio system, equipped with multiple antennas at both ends of the link, that is able to handle up to 32 users and provides raw transmission bit-rates up to 125 Mbps. The task of the MIMO decoder is to appropriately combine the signals simultaneously received on all antennas to construct an improved signal, free of interference, from which to estimate the transm...

IJERT-FPGA Implementation of Channel Estimation Technique in MIMO-OFDM System

International Journal of Engineering Research and Technology (IJERT), 2014

https://www.ijert.org/fpga-implementation-of-channel-estimation-technique-in-mimo-ofdm-system https://www.ijert.org/research/fpga-implementation-of-channel-estimation-technique-in-mimo-ofdm-system-IJERTV3IS051794.pdf Supporting high mobility will be an important character of the future wireless communication systems. It challenges the channel estimaton technique a lot and there are two tough problems in front of us, they are multipath fading channel and bandwidth efficiency. Orthogonal Frequency Division Multiplexing (OFDM) technique changed the frequency selective multipath fading channels into flat fading channel in frequency domain, which effectively mitigates the effects of multipath propogation and, hence, increases data rate. We summarize and analyse the exciting channel estimation methods in mimoofdm system. In this paper, we propose a new hardware implementation of channel estimation for MIMO-OFDM. Our target is to minimize hardware resource utilization. At first, proper algorithm is chosen in consideration of hardware feature as well as communication theory for fast proto typing. Based on the algorithm, our architecture performs channel estimation by simple calculation logic without redundancy. Theoretical analysis and numerical results show that the new channel estimation scheme can offer a good performance and a high ability to track the time varying channel. Index Terms-FPGA,OFDM , mimo-ofdm, channel estimation I .INRODUCTION Multiple-input multiple-output (MIMO) and orthogonal frequency division multiplexing (OFDM) are two key techniques for broadband wireless mobile communications. Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) technology is an attractive transmission technique for wireless communication systems with multiple antennas at transmitter and receiver. The core of this technology is that it divides one data stream to many. Hence, data rate, Dr. Ramesh Assoc. Prof ECE Department CMR Institute of Technology, Bangalore reliability and diversity can be increased along with the stability for multi-path signals. Future wireless communication system have to be designed to integrate features such as high data rates, high quality of service and multimedia in the existing communication framework. Increased demand in wireless communication system has led to demand for higher network capacity and performance. Higher bandwidth, optimized modulation offer practically limited potential to increase the spectral efficiency. Hence MIMO systems utilizes space multiplex by using array of antenna's for enhancing the efficiency at particular utilized bandwidth. MIMO use multiple inputs multiple outputs from single channel. These systems defined by spectral diversity and spatial multiplexing. The aim of this paper is to design and implement of channel estimation method and modulation technique for MIMO system. The design specifications are obtained using MATLAB. The RTL coding is carried for the design to be implemented on Xilinx FPGA. Next generation broadband wireless communications systems will be based on multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) [1] in order to deliver constantly increasing multimedia contents. MIMO-OFDM is a promising technique due to its different modulation schemes, implementation flexibility and robustness against channel frequency selectivity. In order to achieve a preset quality of service in MIMO-OFDM systems, channel estimation and detection techniquesare mandatory. In the literature, depending on the type of MIMO-OFDM system, several channel estimation and detection techniques have been proposed [2][3]. Bit error rate (BER) and implementation complexity are the main performance aspects when comparing their performances. In [2], reduced complexity single-input single-output OFDM (SISO-OFDM) channel estimation techniques have been proposed minimum mean square error (MMSE). The same procedure has been applied also to least squares (LS) type leading to an improvement in performance with a little increase in complexity. In this paper, an extension of these algorithms has been applied to MIMO-OFDM systems. Moreover, a rapid prototyping of these channel estimation techniques is proposed in order to compare hardware resources needed in case of FPGA implementations of these algorithms. The rest of the paper is organized as follows: in section 2, the SISO-OFDM and MIMO-OFDM systems are

A real-time MIMO-OFDM mobile WiMAX receiver: Architecture, design and FPGA implementation

Computer Networks, 2011

The IEEE 802.16e-2005 standard, also denoted as mobile WIMAX, was introduced as one of the first real efforts towards the deployment of fourth generation communication systems providing fixed and mobile broadband wireless access. Mobile WiMAX supports Multiple Input Multiple Output (MIMO) antenna techniques which are considered a key technology in wireless communication systems for increasing both data rates and system performance. This paper presents a real-time 2x2 MIMO mobile WiMAX receiver with a detailed description of the architecture, design and implementation steps. The complexity of the real-time baseband signal processing has been scaled-up due to the high channel bandwidth that was adopted. Numerous equipment and instrumentation comprising our high performance experimental MIMO testbed were used to validate the operation of the mobile WiMAX receiver. The paper includes a subset of results that demonstrate the system-performance using standard 2x2 MIMO mobile channels.

FFT/IFFT Processor Design for 5G MIMO OFDM Systems

International Journal of Wireless Communications and Network Technologies

In this paper, a Fast Fourier Transform (FFT) or inverse FFT processor for Fifth-Generation (5G) Multiple Input Multiple Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) system’s baseband processor is implemented. The proposed 128-point FFT/IFFT processor employs mixed-radix (radix-2 and radix-2 3 )algorithm to reduce the number of complex multiplications. The pipelined FFT architecture with Multipath Delay Feedback (MDF) is chosen for FFT/IFFT processor implementation to have very high throughput rate and minimum power consumption. The resulting Mixed-Radix MDF (MRMDF) architecture provides a very high throughput rates for 1-8 simultaneous data sequences to meet new emerging standards of the MIMO-OFDM based systems. The hardware description is developed using Verilog and synthesized using Xilinx Virtex 5 FPGA family aiming to optimize the design in terms of area and speed at low frequency.