Modeling Modern Micro-architectures using CASL (original) (raw)

CASL: A rapid-prototyping language for modern micro-architectures

Computer Languages, Systems & Structures, 2008

We introduce CASL, the CoGenT Architecture Specification Language, a mixed behavioral-structure architecture description language designed to facilitate fast-prototyping and tool generation for computer architectures with deep pipelines and complicated timing. We motivate a number of CASL features using examples drawn from modeling the IBM Cell Broadband Engine, including implicit connection of components, pipeline support, dynamic information contexts, contention, and timing annotations. We also describe a number of different applications for CASL, including generating timing simulators and instruction schedulers.

ArchC: A SystemC-Based Architecture Description Language

2004

This paper presents an architecture description language (ADL) called ArchC, which is an open-source SystemCbased language that is specialized for processor architecture description. Its main goal is to provide enough information, at the right level of abstraction, in order to allow users to explore and verify new architectures, by automatically generating software tools like simulators and coverification interfaces. ArchC's key features are a storagebased co-verification mechanism that automatically checks the consistency of a refined ArchC model against a reference (functional) description, memory hierarchy modeling capability, the possibility of integration with other SystemC IPs and the automatic generation of high-level SystemC simulators. We have used ArchC to synthesize both functional and cycle-based simulators for the MIPS, Intel 8051 and SPARC V8 processors, as well as functional models of modern architectures like TMS320C62x, XScale and PowerPC.

xMAML: a modeling language for dynamically reconfigurable architectures

2009

Abstract Constant evolution of norms and applications, usually implemented on system-on-chip (SOC), increases architecture performance and flexibility requirements. Current architectures are consequently becoming more complex and difficult to develop. One of the solutions is to develop design frameworks based on high-level architecture description languages (ADL). These ADLs are useful for a rapid description of the hardware that should be implemented on an architecture.

Three-Tiered Specification of Micro-architectures

Lecture Notes in Computer Science, 2002

A three-tiered specification approach is developed to formally specify collections of collaborating objects, say micro-architectures. (i) The structural properties to be maintained in the collaboration are specified in the lowest tier.

A microthreaded architecture and its compiler

2006

A different approach to ILP based on code fragmentation, first proposed some 10 years ago, is being used for novel CMP processor designs. The technique, called microthreading, enables binary compatibility across arbitrary schedules. Chip architectures have been proposed that contain many simple pipelines with hardware support for ultra-fast context switching. The concurrency described in the binary code is parametric and a typical microthread is an iteration of a loop. The ISA contains instructions to create a family of micro-threads, i.e., the collection of all loop iterations. In case a microthread encounters a (possibly) long latency operation (e.g., a load that may miss in the cache) this thread is switched out and another thread is switched in under program control. In this way, latencies can effectively be hidden, if there are a sufficient number of threads available. The creation of families of threads is the responsibility of the compiler. In this presentation, we give an overview of the microthreaded model of computation and we show by some small examples that it provides an efficient way of executing loops. Moreover, we show that this model has excellent scaling properties. Finally, we discuss the compiler support required and propose some compiler transformations that can be used to expose large families of threads.

Architecture Description Languages

Customizable Embedded Processors, 2007

Modeling plays a central role in design automation of embedded processors. It is necessary to develop a specification language that can model complex processors at a higher level of abstraction and enable automatic analysis and generation of efficient tools and prototypes. The language should be powerful enough to capture high-level description of the processor architectures. On the other hand, the language should be simple enough to allow correlation of the information between the specification and the architecture manual.

A formal model of computer architectures for digital system design environments

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990

Abslracl-The process by which computer systems are designed and implemented has become a topic of considerable interest in recent years. Work in this area includes techniques for the automatic generation and optimization of microcode, synthesis of datapaths and control units, and machine description and simulation tools. An important aspect of 'The exo-architecture abstraction level is the view o f a computing syatern taken by an assembler language programmer or compiler writer [ 121.

Architecture description language driven validation of processor, memory, and co-processor pipelines

2001

As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. A significant bottleneck in the validation of such systems is the lack of a golden reference model. Thus, many existing techniques employ a bottom-up approach to architecture validation, where the functionality of an existing pipelined architecture is, in essence, reverse-engineered from its implementation. Our validation technique is complementary to these bottom-up approaches. Our approach leverages the system architect's knowledge about the behavior of the pipelined architecture, through Architecture Description Language (ADL) constructs, and thus allows a powerful top-down approach to architecture validation. The most important requirement in top-down validation process is to ensure that the specification (reference model) is golden. Earlier, we have developed validation techniques to ensure that the static behavior of the pipeline is well-formed by analyzing the structural aspects of the specification using a graph based model. In this paper, we verify the dynamic behavior by analyzing the instruction flow in the pipeline using a Finite State Machine (FSM) based model to validate several important architectural properties such as determinism, finiteness, and execution style (e.g., in-order execution) in the presence of hazards and multiple exceptions. We applied this methodology to the specification of a representative pipelined processor to demonstrate the usefulness of our approach.

MiADL: Architecture description language for design space exploration

3rd IFAC Workshop on Discrete-Event System Design (2006), 2006

The paper presents a novel language, MiADL, which allows the specification of a wide class of ISAs using an expressive and natural description. MiADL explores the common features of instructions to allow compact descriptions. The description's efficiency and expressiveness is demonstrated with some examples, comparing them with other related works, using a complex ISA of a contemporary real-world processor-ARM. The language allows a clear specification of complex instruction formats. Some of its syntax constructs foster the early detection of specification's incoherence improving the description's consistency.

An Architecture Description Language for Embedded Hardware Platforms

Embedded software development relies on various tools-compilers, simulators, execution time estimators-that encapsulate a more-or-less detailed knowledge of the target hardware platform. These tools can be costly to develop and maintain: significant benefits could be expected if they were automatically generated from models expressed in a dedicated modeling language. In contrast with Hardware Description Languages (HDLs), that focus on the internal structure and behavior of an electronic board of chip, Hardware Architecture Description Languages consider hardware as a platform for software execution. Such a platform will be described in terms of low-level programming interface (processor instruction set), resources (processing elements, memory and peripheral devices) and elementary services (arithmetic and logic operations, bus transactions). This paper gives an overview of HARMLESS (Hardware ARchitecture Modeling Language for Embedded Software Simulation), a new domain-specific language for modeling embedded hardware platforms. HARMLESS and its associated tools follow the Model-Driven Engineering philosophy: metamodeling and model transformations have been successfully applied to the automatic generation of processor simulators.