Design and Development of a 32bitALU.pdf (original) (raw)

Design And Synthesis Of 32 BIT ALU Using Xilinx ISE V9.1i

2013

The paper presents Design and Synthesis of 32-BIT Arithmetic Logic Unit (ALU). The design has been implemented using VHDL Xilinx Synthesis tool ISE 9.1i and targeted for Spartan device. ALU is designed to perform Arithmetic operations such as addition, subtraction, overflow; logical operations such as AND, OR, XOR, XNOR and NOT operations, Parity check, 1's and 2's complement operations, compare, etc. The ALU is a fundamental building block of the Central Processing Unit (CPU) of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers. The processors found inside modern CPUs and Graphics Processing Units (GPUs) accommodate very powerful and very complex ALUs; a single component may contain a number of ALUs. Flags like Zero, Carry and Odd Parity show the status of each Flag for result of the ALU's operation in each clock cycle. Zero Counter counts number of zeros in the result. The modern ALU must be capable to perform all the binary arithmetic and logical operations to meet the requirements of modern VLSI industry. So, the paper is a forward step to design the ALU and meets the demand of present FPGA based technology. The paper presents a number of new operations (Parity,Overflow,Zero,Zero counter etc.) that an ALU can perform than so far designed ALU in VHDL.

HIGH SPEED LOW POWER 32 BIT ALU IMPLEMENTATION

The main objective of project is to design and verify different operations of Arithmetic and Logical Unit (ALU). We have designed an 32 bit ALU which accepts two 32 bits numbers and the code corresponding to the operation which it has to perform from the user. The ALU performs the desired operation and generates the result accordingly. The different operations are arithmetical, the coding was written in VHDL and verified in I-Sim. The waveforms were obtained successfully. After the coding was done, the synthesis of the code was performed using Xilinx-ISE. KEYWORDS: logic unit, arithmetic unit, shift unit, arithimatic and logic unit.

Design and Synthesis of Reversible Arithmetic and Logic Unit (ALU)

IEEE International Conference on Computer, Communications, and Control Technology (I4CT), 2014

In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design.

Design and Implementation of Optimized 32-Bit Reversible Arithmetic Logic Unit

With the growing advent of VLSI technology, the device size is shrinking and the complexity of the circuit is increasing exponentially. Power dissipation is considered as one of the most important design parameter. Reversible logic is an emerging and promising technology that provides almost zero power dissipation. Power consumption is also considered as an important parameter in digital circuits. In this paper, an efficient fault tolerant 32-bit reversible arithmetic and logic unit is designed and implemented using some parity preserving gates. The proposed design is better in terms of quantum cost and power dissipation. The number of garbage outputs are reduced by using them as an arithmetic or logical operation. The design can perform three arithmetic operations: Adder, Subtractor, Multiplier and four logical operations: Transfer A, Transfer B, Bitwise AND, XOR operation. The results of the proposed design are then compared with the existing design.

Arithmetic & Logic Unit ( ALU ) Design using Reversible Control Unit

2012

55 Abstract—Reversible logic has received great attention in the recent years due to its ability to reduce the power dissipation which is the main requirement in low power digital design. It has wide applications in advanced computing, low power CMOS design, Optical information processing, DNA computing, bio information, quantum computation and nanotechnology. Conventional digital circuits dissipate a significant amount of energy because bits of information are erased during the logic operations. Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced dramatically. The information bits are not lost in case of a reversible computation. This has led to the development of reversible gates. ALU is a fundamental building block of a central processing unit (CPU) in any computing system; reversible arithmetic unit has a high power optimization on the offer. By using suitable control logic to one of the input variables of para...

Design and Simulation of 64 Bit FPGA Based Arithmetic Logic Unit

Electrica, 2019

Arithmetic Logic Unit (ALU) is the essential part of the Central Processing Unit (CPU) core which performs arithmetical operations such as addition, subtraction, division, multiplication etc., logical operations such as and, or, xor etc. and shift-rotate operations. The CPU performance is directly related to the performance of ALU. In this study, the 64-bit ALU has been designed by using the Very High Speed Integrated Circuits Hardware Description Language (VHDL) and Altera Field Programmable Gate Array (FPGA) families, synthesized and simulated with the help of Altera Quartus II (Intel, Santa Clara, CA, USA) v13.0sp1 and Modelsim-Altera v10.1d (Intel, Santa Clara, CA, USA) software. Many different studies are given about ALU Design and Implementation with the use of FPGA architecture and VHDL language. The difference of this study from recent studies is that the proposed design allows the processing of the signed numbers. Also, Conditional Sum Adder (COSA) is used in addition operation instead of Carry Ripple Adder (CRA) or Carry Look-ahead Adder (CLA) because of its benefit in fast addition and less propagation delay of Carry Chain.

A VHDL Implementation of a Flexible 16-Bit Arithmetic and Logical Unit

2014

In this paper a VHDL structural design for Arithmetic and Logical Unit is proposed. This design of 16 bit ALU consists of two input pins for 16-bit operands along with one input pin for 5 selection lines at the input and at the output a pin for the 32-bit output and a pin for one bit carry or borrow. It may perform all the logical (bitwise) and arithmetic operations such as addition, multiplication, subtraction, division, shift, increment, comparison etc. In this design for 16bit addition and subtraction, the component used is 16-bit Parallel Adder. This 16-bit parallel design includes a 1-bit full adder. In this design multiplier is made of an algorithm called add and shift algorithm. This design may be made more compact using the statement "generic" in VHDL which also makes the design more flexible. These design units are yet independent but using structural modeling these may be simulated through a single design. In this unit the bitwise operations are also added for different selection lines for the logical operations. In this design the multiplexers may be used to select the appropriate inputs for the arithmetic and logic design units. These multiplexers may be used to perform some simple logical operations like programmable shifter or to invert the operands. In accordance with the selection line we may find out about the operations to be performed on the given input. This VHDL design proves to be very flexible and efficient when it is required to add some new complex operations in it.

Design and Implementation of Novel 4-Bit Alu

Lecture Notes in Electrical Engineering, 2020

The paper's main concern is to reduce the power of the adder and multiplier modules, which are significant ALU functional units, thus reducing the overall power utilization without compromising the processor's speed. The ALU circuit ensures that arithmetic or logical operation is carried out only at the same time so that only one set of circuits is active at the same time. Adders constitute a necessary part of every modern integrated circuit. The requirement of an adder is that in terms of power consumption and chip size, it is primarily fast and secondary efficient. The adder topology used in this work is the ripple carrying adder, the look-ahead adder, the adder carrying skip, the adder carrying selection, the adder carrying increase, the adder carrying save and the adder carrying bypass. The Verilog compares module functionality and presentation problems such as area, power dissipation and propagation delay. Every processor's performance depends on its power and delay. To get an effective processor, the power and delay should be lower. The most commonly used architecture in processors is multiplier. If the multiplier power and delay are reduced, then the efficient processor can be generated.