CMOS Technology (original) (raw)

System-level design for nano-electronics

2007 14th Ieee International Conference on Electronics, Circuits and Systems, Vols 1-4, 2007

Latest fabrication technologies of self-assembly nano-circuits (carbon nanotubes, silicon nanowires, etc.) have deployed bottom-up techniques that reach feature sizes well below 65nm, holding great promise for future large silicon-based integrated circuits. However, new nano-devices intrinsically have much higher failure rates than CMOS-based ones. Thus, new design methodologies must address the combination of devicelevel error-prone technologies with system integration constraints (low power, performance) to deliver competitive devices at the nanometer scale. In this paper we show that a very promising way to achieve nano-scale devices is combining imperfectionaware design techniques during fabrication with gate defect modeling at circuit level. Our results using this approach to define a Carbon Nanotube Field-Effect Transistor (CNFET)-based design flow for nanoscale logic circuits attain more than 3× energydelay-product advantage compared to 65nm CMOS-based ones.

Scalable Defect Tolerance for Molecular Electronics

Chemically assembled electronic nanotechnology (CAEN) is a promising alternative to CMOS-based computing. However, CAEN-based circuits are expected to have huge defect densities. To solve this problem CAEN can be used to build reconfigurable fabrics which, assuming the defects can be found, are inherently defect tolerant. In this paper, we propose a scalable testing methodology for finding defects in reconfigurable devices.

Transistor-level based defect tolerance for reliable nanoelectronics

2008 IEEE/ACS International Conference on Computer Systems and Applications, 2008

Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by quaddedtransistor structure that guarantees defect tolerance of all single defects and a large number of multiple defects as validated by theoretical analysis and simulation. As demonstrated by extensive simulation results using ISCAS 85 and 89 benchmark circuits, the investigated technique achieves significantly higher defect tolerance than recently reported nanoelectronics defect-tolerant techniques (even with up to 4 to 5 times more transistor defect probability) and at reduced area overhead.

Defect-tolerant N2-transistor structure for reliable nanoelectronic designs

IET Computers & Digital Techniques, 2009

Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by N 2 -transistor structure (N≥2) that guarantees defect tolerance of all N-1 defects as validated by theoretical analysis and simulation. As demonstrated by extensive simulation results using ISCAS 85 and 89 benchmark circuits, the investigated technique achieves significantly higher defect tolerance than recently reported nanoelectronics defect-tolerant techniques (even with up to 4 to 5 times more transistor defect probability) and at reduced area overhead. For example, the quadded-transistor structure technique requires nearly half the area of the quadded logic technique.

Defect-Tolerant N 2-Transistor Structure for Reliable Design at the Nanoscale

Nanodevices based circuit design will be based on the acceptance that a high percentage of devices in the design will be defective. In this work, we investigate a defect tolerant technique that adds redundancy at the transistor level and provides built-in immunity to permanent defects (stuck-open, stuck-short and bridges). The proposed technique is based on replacing each transistor by N 2 -transistor structure (N≥2) that guarantees defect tolerance of all N-1 defects as validated by theoretical analysis and simulation. As demonstrated by extensive simulation results using ISCAS 85 and 89 benchmark circuits, the investigated technique achieves significantly higher defect tolerance than recently reported nanoelectronics defect-tolerant techniques (even with up to 4 to 5 times more transistor defect probability) and at reduced area overhead. For example, the quadded-transistor structure technique requires nearly half the area of the quadded logic technique.

Strategies for nanoelectronics

Microelectronic …, 2005

Denoting with ÔnanodeviceÕ any device with size in one dimension at least in the nanometre length scale (NLS), the basic constituent of integrated circuits (ICs), the metal-oxide-semiconductor (MOS) field-effect transistor (FET), is by several years a nanodevice. In fact, the thickness of the SiO 2 gate dielectric is around 3 nm for logics or 5 nm for nonvolatile memories. However, since the factors limiting the IC integration are horizontal sizes, in electronics one speaks of nanodevice when its size in one horizontal dimension at least is in the NLS. The definition of features in the NLS is impossible via optical lithography, but can be done using electron-or ion-beam lithography. These techniques, however, are very expensive and still in their fancy, at least for what concerns their exploitation in the industry practice. Geometries in the NLS can however be produced with relative ease by the spacer patterning technique, i.e., transforming vertical features (like film thickness) in the vicinity of a step of a sacrificial layer into horizontal features. The ultimate length producible in this way is controlled by: the steepness of the step defining the sacrificial layer; the uniformity of the deposited or grown films; and the anisotropy of its etching. While useful for the preparation of a few devices with special needs, the above trick does not allow by itself the development of a nanotechnology, where each layer useful for defining the FET should be in the NLS and aligned on the underlying geometries with tolerances in the NLS. Setting up such a nanotechnology is a major problem which will involve the IC industry in the post-Roadmap era. Irrespective of the detailed structure of the basic constituents of nanoICs (molecules, supramolecular structures, clusters, etc.), any nanoIC can hardly be prepared without the ability to produce arrays of conductive strips with pitch in the NLS. This work is devoted to describe a scheme (essentially based on the existing microelectronic technology) for their production without the use of electron-or ion-beam lithography and used as host of molecular devices.

“Bottom-up” Approaches for Nanoelectronics

Over the last 40 years, feature sizes in complementary metal oxide semiconductor (CMOS) technologies have been scaled from 3 μm to the current sub-50 nm using the "top-down" scaling techniques (Nowak, 2002). This "scaling" has resulted in an increased processing power and transistor density while reducing the cost per transistor (Chao Li et al., 2007). These classical methods employ a sequence of deposition, pattern definition, doping, lithographic and etching steps to build solid-state semiconductor devices and integrated circuits. As the process technologies scale beyond the sub-10nm feature sizes, above fabrication methods result in increased process costs, variability and longer fabrication turnaround times. To push the CMOS technology to its limits and to reap the benefits of scaling, non-traditional alternatives are needed while fabricating devices. One such approach is the use of "bottom-up" nanotechnologies or even a combination of the bottomup and the "top-down" fabrication methodologies (Wei et al., 2007). In the bottom-up approach, analogous to the biological systems, atoms or organic molecules are selfassembled to build electronic structures with novel electronic, optical, or magnetic properties. Integrated circuits obtained with this approach of molecular-level control of material composition and structure may lead to devices and fabrication strategies not possible with top-down methods (Amarchand Satyapalan et al., 2005). The field of self-assembled monolayers (SAMs), especially mono and multilayer assemblies of organic materials on various substrates has been most extensively studied in recent years. The compelling force for this research is the importance of such formations to nanoelectronic device fabrication, for modifying the surface wetting/adhesion properties, for sensor applications and for corrosion resistance and molecular electronics (Kaushik Nayak et al. 2007). With the limitations in lithography techniques, to get features smaller than 10 nm, the molecular self-assembly provides the route to both smaller features and lower costs. Because of the ability to form layers with atomic resolution thickness and spacing, they are used as ultra thin resists and passivating layers. CNTs, polyphenylenes, porphyrins and DNA strands are some of the molecules that are being actively researched for the above applications (Reimers et al., 1996).

Towards Defect-Tolerant Nanoscale Architectures

2006

Nanoscale computing systems show great potential but at the same time introduce new challenges not encountered in the world of conventional CMOS designs and manufacturing. For example, these systems need to work around layout and doping constraints resulting from unconventional bottom-up selfassembly, and need to cope with high manufacturing defect rates and transient faults. Unfortunately, most conventional defecttolerance techniques are not directly applicable in nanoscale systems because they have been designed for very small defect rates. In this paper, we explore built-in defect-tolerance techniques on 2-D semiconductor nanowire (NW) arrays to make designs self-healing. Our approach combines circuit and systemlevel techniques and it does not require defect map extraction, reconfigurable devices, or addressing each cross-point similar to reconfigurable approaches. We show that a defect-tolerant simple processor based on our approach would be still around 3X denser than an 18-nm CMOS version with equivalent functionality; a yield greater than 30% is achieved despite a fabric with 14% defective FETs.

Nanoscale Application Specific Integrated Circuits

2011

This fabric update summarizes recent advances for the Nanoscale Application Specific Integrated Circuits (NASICs) nanoscale computing fabric. We provide a brief overview of NASICs, and discuss recent work at all fabric levels. We present advances in device design and optimization including omega gated and junctionless nanowire field effect transistors, methodologies for validation of functionality and parameter variation evaluation, new circuit-level sequencing schemes and performance optimization techniques. We also discuss techniques for defect and parameter variation resilience, ongoing fabrication directions including prototyping and scalable assembly efforts, and directions for the future.