A formal high level synthesis approach for DSP architectures (original) (raw)

A framework for high level synthesis of digital architectures from u-recursive algorithms

Proceedings of the 1990 ACM annual conference on Cooperation - CSC '90, 1990

The major drawback of reported high level synthesis techniques is their limited applicability to a specific class of algoriehms without extendibility to general algorithms and the lack of a formal approach to prove the correctness of the such techniques. In this paper, we introduce a novel approach for high level synthesis from p-recursive alg+ rithms. Two features are provided by the approach: completeness and correctness. Completeness means the ability to use the approach for any general algorithm. Correctness is achieved by using a set of transformations that are proved to be correct. A formal framework for the synthesis procedure has been developed which can be easily automated. A given algorithm will be represented in a new developed language termed Algorithm Specification Language (ASL). ASL has the ability to describe any general algorithm.

A synthesis environment for designing DSP systems

IEEE Design & Test of Computers, 1989

Digital signal processing is a key technology with applications in commercial a n d military electronic systems. Automation in the design of signal processors is needed to reduce the overall product development cycle a n d cost. The a u t h o r s report o n work done a t GE to address the design of DSP syst e m s through the u s e of high-level synthesis tools. The key to success i n hardware synthesis i s to have the application drive the tool development a n d to focus synthesis algorithms to a well-defined hardware architecture or class of architectures.

A Logic Programming Approach For DSP Architectures Design

Twenty-Second Asilomar Conference on Signals, Systems and Computers, 1988

This paper introduces a logic programming approach for specifying, simulating, and testing Digital Signal Processing (DSP) systems. Prolog is used as a Hardware Description Language and a host one, too. Backtracking and patt,ern matching of Prolog are employed for simulation and testing, respectively. Prolog provides homogeneity to the developed system as it supports hierarchical development and mixing of description at various hierarchical levels. The developed system belongs to Algorithmic Specific CAD family. It can be employed for many DSP algorithms and applications development.

A formal framework for high level synthesis

Lecture Notes in Computer Science, 1995

In this paper, we propose a new approach to formal synthesis which focuses on the generation of verification-friendly circuits. Starting from a high-level implementation description, which may result from the application of usual scheduling and allocation algorithms, hardware is automatically synthesized. The target architecture is based on handshake processes, modules which communicate by a simple synchronizing handshake protocol. The circuits result from the application of only a few basic operations like synchronization, sequential execution or iteration of base handshake processes. Each process is guided by an abstract theorem that is used to derive proof obligations, to be justified after synthesis. Automation has been achieved to the extend that only those "relevant" proof obligations remain to be proven manually, e.g. theorems for data-dependent loops and lemmata about the used data types. The process-oriented implementation language is enriched by loop invariants. If those are given prior to the synthesis process and the underlying data types are only Booleans, i.e. finite-length bitvectors, then the complete synthesis and verification process runs automatically.

Automated Synthesis of Digital Hardware

IEEE Transactions on Computers, 1982

This part of the research involves the design and implementation of a data-memory allocator, consisting of a set of algorithms and data structures which synthesize hardware at the logical level from an ISPL language description. Preliminary results indicate the allocator's performance compares favorably with a human designer when designing an elevator controller and a reduced PDP-8/E. 1.0 INTRODUCTION The motivation behind the research described in this paper is to enhance the digital designer's capabilities by producing more powerful design tools. Digital logic design has progressed to the point that the operation of the logic can be functionally expressed by a variety of hardware descriptive languages, ISP being one of the more widely used behavioral languages. Functional simulators exist and are useful for verifying system operation and performance measurements (Barb77a). Thus, the state of the art in digital design is such that the next addition to design aids should be a synthesis program; a program that can design the STRUCTURE of a digital system, given its FUNCTION or The research described in this paper was supported by the U.S. Army Research Office under grant DAAG29-76-G-0224, and by a fellowship from IBM Corporation. A

Synthesis of ASIPs for DSP algorithms

Integration, the VLSI Journal, 1999

y This paper is an extended version of the results presented at VLSI Design'99 30]. a S. Ramanathan is currently with Philips Semiconductors, Bangalore (email: ramanathan.s@blr.sc.philips.com). b V. Visvanathan is currently with Cadence Design Systems, Allentown, PA (Abstract ASICs o er the best realization of DSP algorithms in terms of performance, but the cost is prohibitive, especially when the volumes involved are low. However, if the architecture synthesis trajectory for such algorithms is such that the target architecture can be identi ed as an interconnection of elementary parameterized computational structures, then it is possible to attain a close match, both in terms of performance and power with respect to an ASIC, for any algorithmic parameters of the given algorithm. Such an architecture is weakly programmable (con gurable) and can be viewed as an application speci c integrated processor (ASIP). In this work, we present a methodology to synthesize ASIPs for DSP algorithms.

Architectural synthesis for DSP silicon compilers

IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1989

Absfmcf-A novel design methodology for automated mapping of DSP algorithms into VLSI architectures is presented. The methodology takes into account explicit algorithm requirements on throughput and latency, in addition to VLSI technology constraints on silicon area and power dissipation. Algorithm structure, design style of functional units and parallelism of the architecture are all explored in the design space. The synthesized architecture is a multi-bus multi-functional unit processor matched to the implemented algorithm. The architecture has a linear topology and uses a lower number of interconnects and multiplexer inputs compared to other synthesized architectures with random topology having the same performance. The synthesized processor is a self-timed element externally, while it is internally synchronous. The methodology is implemented in a design aid tool called SPAID. Results obtained using SPAID for two DSP algorithms compare favorably over other synthesis techniques.

ASIC DSP compiler for optimized synthesis

International Conference on Signal Processing, 2000

This paper presents a high level DSP architecture compiler for cycle-constrained filters and datapath applications. The tool offers an easy way to get, from an equation representation of a filter, a synthetisable VHLD description of an application specific DSP architecture. Inputs of the DSP compiler are an equation file to define the filter structure and a resource definition file to specify the available resource units. The equation syntax is very comfortable. Resource mapping, scheduling, binding and furthermore the quantification of each operation is usually performed automatically, but can be controlled by the user. The result is a very fast filter synthesis time combined with highest flexibility for the users.

Synthesis of configurable architectures for DSP algorithms

Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), 1999

ASICs o er the best realization of DSP algorithms in terms of performance, but the cost is prohibitive, especially when the volumes involved are low. However, if the architecture synthesis trajectory for such algorithms is such that the target architecture can be identi ed as an interconnection of elementary parameterized computational structures, then it is possible to attain a close match, both in terms of performance and power with respect to an ASIC, for any algorithmic parameters of the given algorithm. Such an architecture is weakly programmable (con gurable) and can be viewed as an application speci c instruction-set processor (ASIP). In this work, we present a methodology to synthesize ASIPs for DSP algorithms.