Novel serial–parallel multipliers (original) (raw)
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IRJET- DESIGN OF A LOW POWER SERIAL-PARALLEL MULTIPLIER WITH LOW TRANSITION ADDITION
IRJET, 2020
This paper proposes a low power and low transition addition for the serial parallel multiplier for digital signal processing (DSP) and machine learning (ML) applications, dictating the area, delay, and overall performance of parallel implementations. In the proposed work a radix-4, serial-parallel multiplier using modified booths algorithm for accelerating applications such as digital filters, artificial neural networks, and other machine learning algorithms is designed. The Multiplication process is done by the serial-parallel (SP) modified radix-4 Booth multiplier that adds only the nonzero Booth encodings and skips over the zero operations, making the latency dependent on the multiplier value. Our optimizations can result in an improvement over the standard serial parallel Booth multiplier in terms of area-delay and power.
A low latency bi-directional serial-parallel multiplier architecture
2000
A new bi-directional bit serial-parallel multiplication architecture is presented. The proposed structure is regular and modular, and requires nearest neighbour communication links only, which makes it more efficient for VLSI implementation. Furthermore, a judicious deployment of latches in the circuit ensures that the multiplier operates on two coefficients of the multiplicand at the same time thus speeding up the process. Comparison of the new multiplier structure with previous ones has shown the superiority of the new architecture
There are mainly four series of Parallel Digital-Multipliers: Array, Vedic, Booth and Wallace series of multipliers. In this paper, a multiplier is proposed. This proposed multiplier has better performance than the other four types of series of multipliers. The proposed multiplier is actually a modified version of Wallace and Dadda multipliers. This paper presents a comparison of the proposed multiplier with these four types of series of multipliers. From each series, one multiplier which is the best among its series is selected for comparison by doing literature review of that series of multiplier. The comparison is in terms of delay, power and area. The selected multipliers with the proposed multiplier are implemented on front-end modeling using Verilog-HDL. For simulation, Modelsim is used and for synthesis and implementation Vivado is used. The target technology used for implementation is the FPGA, Z-board (xc7z020clg484-1).
DESIGN OF LOW POWER MULTIPLIER
The novel 32x32 multiplier design using Booth architecture and Vedic architecture is presented in this project. The Booth multiplier, which is the foundation of the Booth architecture, cuts the number of partial products generated in half. Vedic architecture benefits from simultaneous partial product production and adding. The 16x16 Vedic architecture is used to divide the 32x32 multiplicand and multiplier in order to increase the performance of the multiplication. In addition to Vedic design, this new 32x32 signed multiplier also has more benefits than the individual Booth multiplier and Vedic multiplier technique. Compared to a standard 16x16 Booth multiplier, it has a straightforward architecture. This new multiplier makes use of the Carry Select Adder and the Ripple Carry Adder (RCA). CSA to add the product that was partially generated. The performance has increased thanks to the new 32x32 signed multiplier's shorter overall propagation delay. The modern 32x32 multiplier design is more optimized compared to individual ones. This is due to the concurrent usage of Vedic architecture for both the partial product addition and the partial product production by the Booth multiplier. The proposed multiplier is designed using Xilinx ISE and Xilinx Vivado.
A Simple High-Speed Multiplier Design
IEEE Transactions on Computers, 2000
The performance of multiplication is crucial for multimedia applications such as 3D graphics and signal processing systems, which depend on the execution of large numbers of multiplications. Previously reported algorithms mainly focused on rapidly reducing the partial products rows down to final sums and carries used for the final accumulation. These techniques mostly rely on circuit optimization and minimization of the critical paths. In this paper, an algorithm to achieve fast multiplication in two's complement representation is presented. Rather than focusing on reducing the partial products rows down to final sums and carries, our approach strives to generate fewer partial products rows. In turn, this influences the speed of the multiplication, even before applying partial products reduction techniques. Fewer partial products rows are produced, thereby lowering the overall operation time. In addition to the speed improvement, our algorithm results in a true diamond-shape for the partial product tree, which is more efficient in terms of implementation. The synthesis results of our multiplication algorithm using the Artisan TSMC 0:13um 1.2-Volt standard-cell library show 13 percent improvement in speed and 14 percent improvement in power savings for 8-bit  8-bit multiplications (10 percent and 3 percent, respectively, for 16-bit  16-bit multiplications) when compared to conventional multiplication algorithms.
Design of Efficient and Fast Multiplier Using MB Recoding Techniques
International Journal of Emerging Research in Management &Technology , 2015
In Digital Signal processing applications, fast processing of a huge quantity of data in Digital form. Presently, multiplier plays a major role in Digital Signal Processors. Using three different schemes in Fused Add-Multiply (FAM) design for the reduction in terms of power and delay. Multiplier results of 7 bit and 11 bit (odd) for both signed and unsigned numbers to be produced using efficient modified booth recoding (EMBR) techniques in three different schemes of FAM design.
Design of 16-bit Multiplier Using Efficient Recoding Techniques
International Journal of Hybrid Information Technology, 2015
Multiplier is the major component for processing of large amount of data in DSP applications. Using different recoding schemes in Fused Add-Multiply (FAM) design for the reduction of power and look up tables. The performance of 16-bit signed and unsigned multipliers were designed and obtained results are tabulated using Efficient Modified Booth Recoding (EMBR) techniques, which can be used for low power applications.
High-speed Multiplier Design Using Multi-Operand Multipliers
2012
Multipliers are used in most arithmetic computing systems such as 3D graphics, signal processing, and etc. It is inherently a slow operation as a large number of partial products are added to produce the result. There has been much work done on designing multipliers [1]-[6]. In first stage, Multiplication is implemented by accumulation of partial products, each of which is conceptually produced via multiplying the whole multi-digit multiplicand by a weighted digit of multiplier. To compute partial products, most of the approaches employ the Modified Booth Encoding (MBE) approach [3]-[5], [7], for the first step because of its ability to cut the number of partial products rows in half. In next step the partial products are reduced to a row of sums and a row of caries which is called reduction stage.