Oversampling enhancement in sigma delta modulators (original) (raw)
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Oversampled delta-sigma modulators: Analysis, applications and novel topologies
2003
new method to obtain efficient architectures for time-interleaved Delta-Sigma modulators. Additionally, a novel parallel conversion technique, which we have dubbed as the "Zero-Insertion Time-Interleaving" concept is also proposed. In this approach, the input only needs to be sampled at the operating frequency of the parallel channels. Thus, the high sampling rate input multiplexer involved in the regular Time-Interleaved approach is completely eliminated resulting in further significant reductions in the hardware complexity. Such a multiple channel Delta-Sigma modulator may be very useful for implementing high-resolution converters for wide bandwidth input signals, at the expense of moderate increase in the hardware cost.
Iscas, 2002
¦¡-modulation is a proven method to realize high-resolution A/D converters. A particularly efficient way to implement such a modulator uses double-sampling where the sampling frequency is twice the master-clock frequency. Unfortunately path mismatch between both sampling branches causes a part of the quantisation noise to fold from the Nyquist frequency back in the signal band. This degrades the performance. In this paper we show that multi-bit quantisation provides a partial solution for this problem.
Design of Second Order Discrete Time Sigma Delta Modulator for High Resolution Applications
2017
Aim of This work is to Design a second order discrete time sigma delta modulator for low frequency high resolution applications, which can be used in data converters (sigma delta ADC) where high resolution is required for more accuracy in signal processing’s. A real world is analogue but easier to process digital data ex: speech, image processing’s. Analog signal contains too much unnecessary data ADC samples the data and splits into finite information. Sigma delta ADC is very much suitable for less area low frequency and high resolution data conversions. Now the aim is to design a sigma delta modulator in which these parameters plays major role 1) resolution 2) order 3) OSR 3) power consumption 4)SNR 5)SNDR 6)dynamic Range. This design is carried out with the 180nM CMOS technology at an operating voltage of ±700mV, and the results are tested with the help of Cadence Virtuoso Spectre Circuit Simulator.
Design of Multi-bit Sigma-Delta Modulators for Digital Wireless Communications
The ever advance of CMOS digital circuit process leads to the trend of digitizing an analog signal and performing digital signal processing as early as possible in a signal processing system, which in turn leads to an increasing requirement on analog-to-digital converter (ADC). A wireless transceiver is a such kind of signal processing system. Conventional transceivers manipulate (filter, amplify and mix) the signal mostly in analog domain. Since analog filters are difficult to design on-chip, the system integration level is low. Modern transceivers shift many of these tasks to digital domain, where the filtering and channel selection can be realized more accurately and more compactly. However the price for the high integration level is the critical requirement on the ADC, because the simplified analog part sends not only the weak signal but also the unwanted strong neighboring channel to the ADC. In order to digitize the needed signal in the presence of strong disturbances, a high dynamic-range and high-speed ADC is needed.
Delta-sigma modulators using frequency-modulated intermediate values
IEEE Journal of Solid-State Circuits, 1997
This paper describes a new first-and second-order delta-sigma modulator concept where the first integrator is extracted and implemented by a frequency modulator with the modulating signal as the input. The result is a simple delta-sigma modulator with no need for digital-to-analog converters, allowing straightforward multi-bit quantization. Without the frequency modulator, the circuit becomes a frequency-to-digital converter with delta-sigma noise shaping. An experimental first-and second-order modulator have been implemented in a 1.2-¼m standard digital CMOS process and the results confirm the theory. For the first-order modulator an input signal amplitude of 150mV resulted in a SQNR of ³115dB at 2MHz sampling frequency and signal bandwidth 500Hz.
Design techniques for high-resolution current-mode sigma-delta modulators
IEEE Journal of Solid-State Circuits, 1997
This paper describes techniques for the design of high-resolution oversampling analog-to-digital converters based on current memories. A key point is the reduction of nonlinearities, in particular those introduced by the current switches. A current-memory cell with very high precision and linearity has been designed and used in an experimental third-order 6-1 modulator in a 0.8-m digital CMOS process. A linearity of better than 14 b and a maximum signal-to-noise+distortion ratio (SNDR) of 80 dB has been measured for an oversampling ratio (OSR) of 64.
Preliminary Design and Comparative Analysis Between Different DT Sigma-Delta Modulators
Sigma-Delta analog-to-digital converters (ADCs) are known for providing high resolutions when compared to other ADC architectures. They are composed of a sigma-delta modulator and a digital decimation filter. This work focuses is in the high-level design of discrete-time sigma-delta modulators (DT-SDMs) whereas the design and implementation of first and second-order modulators are analyzed using Matlab. A complete performance analysis of each modulator is described using the cascade of integrators in feedback (CIFB) structure. It is worth mentioning that our study has a focus on medium bandwidth (BW) applications, as such audio applications. Besides, we target low-voltage operations. This work is at an early stage, thus only first and second-order modulators are investigated. This work considers a BW of 24 kHz, a sampling frequency of 6.144 MHz, and oversampling (OSR) of 128. Index Terms-sigma-delta modulators, sigma-delta ADC, DT-SDM CIFB structure.
An efficient technique to eliminate quantisation noise folding in double-sampling ΣΔ modulators
¦¡-modulation is a proven method to realize high-resolution A/D converters. A particularly efficient way to implement such a modulator uses double-sampling where the sampling frequency is twice the master-clock frequency. Unfortunately path mismatch between both sampling branches causes a part of the quantisation noise to fold from the Nyquist frequency back in the signal band. This degrades the performance. In this paper we show that multi-bit quantisation provides a partial solution for this problem.
Design and Implementation of Low-Oversampling Delta Sigma Modulators for High Frequency Applications
— The key factor making Delta-Sigma modulators (DSM) one of the most popular components in modern electronic circuits is its high linearity. This is achieved by using a high oversampling ratio which is unfortunately the limiting factor towards its application in high frequency circuits. The necessity of high processing speed and power, the increased cost and complexity and wastage of available bandwidth are some of the significant demerits of using a high oversampling ratio. This paper suggests that the delta sigma modulators require a high frequency processing and not high oversampling ratio. A parallel structure to perform the high frequency processing along with an adaptive method to improve the signal quality at the output is proposed. The suggested technique allows the simultaneous execution of fast and complex computations required for wireless systems. The analysis is performed using MATLAB simulations and the results claim a reduction in oversampling ratio by a factor of 16 while keeping the same signal to noise ratio. The proposed architecture is implemented on a field-programmable gate array (FPGA) board which is then validated with a code division multiple access signal. The output signal bandwidth is observed to be increasing four times without any increase in the sampling frequency. Keywords—Delta–sigma modulation, oversampling, parallel processing, field-programmable gate array (FPGA).
Analysis and simulation of a cascaded delta delta–sigma modulator
Computer Standards & Interfaces, 2001
This paper analyses and simulates a delta delta-sigma modulator, the cascade combination of a delta modulator and a delta-sigma modulator. Using prediction, the delta modulator reduces the dynamic range of a signal prior to quantisation. Using noise shaping, the delta-sigma modulator cancels the error of the delta modulator. Performance is evaluated with input signals from a random noise process, composed of a high dynamic range narrow-band process and a low dynamic range wide-band process. Integrator leakage in the delta modulator and DAC mismatch between the two modulators may complicate implementation. The cascaded modulator outperforms conventional modulators of similar order when there is a degree of correlation between consecutive samples of the input process.